1 /* 2 * Register definition file for Samsung MFC V5.1 Interface (FIMV) driver 3 * 4 * Kamil Debski, Copyright (c) 2010 Samsung Electronics 5 * http://www.samsung.com/ 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #ifndef _REGS_FIMV_H 13 #define _REGS_FIMV_H 14 15 #define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) 16 #define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4) 17 18 /* Number of bits that the buffer address should be shifted for particular 19 * MFC buffers. */ 20 #define S5P_FIMV_START_ADDR 0x0000 21 #define S5P_FIMV_END_ADDR 0xe008 22 23 #define S5P_FIMV_SW_RESET 0x0000 24 #define S5P_FIMV_RISC_HOST_INT 0x0008 25 26 /* Command from HOST to RISC */ 27 #define S5P_FIMV_HOST2RISC_CMD 0x0030 28 #define S5P_FIMV_HOST2RISC_ARG1 0x0034 29 #define S5P_FIMV_HOST2RISC_ARG2 0x0038 30 #define S5P_FIMV_HOST2RISC_ARG3 0x003c 31 #define S5P_FIMV_HOST2RISC_ARG4 0x0040 32 33 /* Command from RISC to HOST */ 34 #define S5P_FIMV_RISC2HOST_CMD 0x0044 35 #define S5P_FIMV_RISC2HOST_CMD_MASK 0x1FFFF 36 #define S5P_FIMV_RISC2HOST_ARG1 0x0048 37 #define S5P_FIMV_RISC2HOST_ARG2 0x004c 38 #define S5P_FIMV_RISC2HOST_ARG3 0x0050 39 #define S5P_FIMV_RISC2HOST_ARG4 0x0054 40 41 #define S5P_FIMV_FW_VERSION 0x0058 42 #define S5P_FIMV_SYS_MEM_SZ 0x005c 43 #define S5P_FIMV_FW_STATUS 0x0080 44 45 /* Memory controller register */ 46 #define S5P_FIMV_MC_DRAMBASE_ADR_A 0x0508 47 #define S5P_FIMV_MC_DRAMBASE_ADR_B 0x050c 48 #define S5P_FIMV_MC_STATUS 0x0510 49 50 /* Common register */ 51 #define S5P_FIMV_COMMON_BASE_A 0x0600 52 #define S5P_FIMV_COMMON_BASE_B 0x0700 53 54 /* Decoder */ 55 #define S5P_FIMV_DEC_CHROMA_ADR (S5P_FIMV_COMMON_BASE_A) 56 #define S5P_FIMV_DEC_LUMA_ADR (S5P_FIMV_COMMON_BASE_B) 57 58 /* H.264 decoding */ 59 #define S5P_FIMV_H264_VERT_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c) 60 /* vertical neighbor motion vector */ 61 #define S5P_FIMV_H264_NB_IP_ADR (S5P_FIMV_COMMON_BASE_A + 0x90) 62 /* neighbor pixels for intra pred */ 63 #define S5P_FIMV_H264_MV_ADR (S5P_FIMV_COMMON_BASE_B + 0x80) 64 /* H264 motion vector */ 65 66 /* MPEG4 decoding */ 67 #define S5P_FIMV_MPEG4_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c) 68 /* neighbor AC/DC coeff. */ 69 #define S5P_FIMV_MPEG4_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90) 70 /* upper neighbor motion vector */ 71 #define S5P_FIMV_MPEG4_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94) 72 /* subseq. anchor motion vector */ 73 #define S5P_FIMV_MPEG4_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98) 74 /* overlap transform line */ 75 #define S5P_FIMV_MPEG4_SP_ADR (S5P_FIMV_COMMON_BASE_A + 0xa8) 76 /* syntax parser */ 77 78 /* H.263 decoding */ 79 #define S5P_FIMV_H263_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c) 80 #define S5P_FIMV_H263_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90) 81 #define S5P_FIMV_H263_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94) 82 #define S5P_FIMV_H263_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98) 83 84 /* VC-1 decoding */ 85 #define S5P_FIMV_VC1_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c) 86 #define S5P_FIMV_VC1_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90) 87 #define S5P_FIMV_VC1_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94) 88 #define S5P_FIMV_VC1_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98) 89 #define S5P_FIMV_VC1_BITPLANE3_ADR (S5P_FIMV_COMMON_BASE_A + 0x9c) 90 /* bitplane3 */ 91 #define S5P_FIMV_VC1_BITPLANE2_ADR (S5P_FIMV_COMMON_BASE_A + 0xa0) 92 /* bitplane2 */ 93 #define S5P_FIMV_VC1_BITPLANE1_ADR (S5P_FIMV_COMMON_BASE_A + 0xa4) 94 /* bitplane1 */ 95 96 /* Encoder */ 97 #define S5P_FIMV_ENC_REF0_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x1c) 98 #define S5P_FIMV_ENC_REF1_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x20) 99 /* reconstructed luma */ 100 #define S5P_FIMV_ENC_REF0_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B) 101 #define S5P_FIMV_ENC_REF1_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x04) 102 /* reconstructed chroma */ 103 #define S5P_FIMV_ENC_REF2_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x10) 104 #define S5P_FIMV_ENC_REF2_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x08) 105 #define S5P_FIMV_ENC_REF3_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x14) 106 #define S5P_FIMV_ENC_REF3_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x0c) 107 108 /* H.264 encoding */ 109 #define S5P_FIMV_H264_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A) 110 /* upper motion vector */ 111 #define S5P_FIMV_H264_NBOR_INFO_ADR (S5P_FIMV_COMMON_BASE_A + 0x04) 112 /* entropy engine's neighbor info. */ 113 #define S5P_FIMV_H264_UP_INTRA_MD_ADR (S5P_FIMV_COMMON_BASE_A + 0x08) 114 /* upper intra MD */ 115 #define S5P_FIMV_H264_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10) 116 /* direct cozero flag */ 117 #define S5P_FIMV_H264_UP_INTRA_PRED_ADR (S5P_FIMV_COMMON_BASE_B + 0x40) 118 /* upper intra PRED */ 119 120 /* H.263 encoding */ 121 #define S5P_FIMV_H263_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A) 122 /* upper motion vector */ 123 #define S5P_FIMV_H263_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04) 124 /* upper Q coeff. */ 125 126 /* MPEG4 encoding */ 127 #define S5P_FIMV_MPEG4_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A) 128 /* upper motion vector */ 129 #define S5P_FIMV_MPEG4_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04) 130 /* upper Q coeff. */ 131 #define S5P_FIMV_MPEG4_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10) 132 /* direct cozero flag */ 133 134 #define S5P_FIMV_ENC_REF_B_LUMA_ADR 0x062c /* ref B Luma addr */ 135 #define S5P_FIMV_ENC_REF_B_CHROMA_ADR 0x0630 /* ref B Chroma addr */ 136 137 #define S5P_FIMV_ENC_CUR_LUMA_ADR 0x0718 /* current Luma addr */ 138 #define S5P_FIMV_ENC_CUR_CHROMA_ADR 0x071C /* current Chroma addr */ 139 140 /* Codec common register */ 141 #define S5P_FIMV_ENC_HSIZE_PX 0x0818 /* frame width at encoder */ 142 #define S5P_FIMV_ENC_VSIZE_PX 0x081c /* frame height at encoder */ 143 #define S5P_FIMV_ENC_PROFILE 0x0830 /* profile register */ 144 #define S5P_FIMV_ENC_PROFILE_H264_MAIN 0 145 #define S5P_FIMV_ENC_PROFILE_H264_HIGH 1 146 #define S5P_FIMV_ENC_PROFILE_H264_BASELINE 2 147 #define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE 0 148 #define S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE 1 149 #define S5P_FIMV_ENC_PIC_STRUCT 0x083c /* picture field/frame flag */ 150 #define S5P_FIMV_ENC_LF_CTRL 0x0848 /* loop filter control */ 151 #define S5P_FIMV_ENC_ALPHA_OFF 0x084c /* loop filter alpha offset */ 152 #define S5P_FIMV_ENC_BETA_OFF 0x0850 /* loop filter beta offset */ 153 #define S5P_FIMV_MR_BUSIF_CTRL 0x0854 /* hidden, bus interface ctrl */ 154 #define S5P_FIMV_ENC_PXL_CACHE_CTRL 0x0a00 /* pixel cache control */ 155 156 /* Channel & stream interface register */ 157 #define S5P_FIMV_SI_RTN_CHID 0x2000 /* Return CH inst ID register */ 158 #define S5P_FIMV_SI_CH0_INST_ID 0x2040 /* codec instance ID */ 159 #define S5P_FIMV_SI_CH1_INST_ID 0x2080 /* codec instance ID */ 160 /* Decoder */ 161 #define S5P_FIMV_SI_VRESOL 0x2004 /* vertical res of decoder */ 162 #define S5P_FIMV_SI_HRESOL 0x2008 /* horizontal res of decoder */ 163 #define S5P_FIMV_SI_BUF_NUMBER 0x200c /* number of frames in the 164 decoded pic */ 165 #define S5P_FIMV_SI_DISPLAY_Y_ADR 0x2010 /* luma addr of displayed pic */ 166 #define S5P_FIMV_SI_DISPLAY_C_ADR 0x2014 /* chroma addrof displayed pic */ 167 #define S5P_FIMV_SI_CONSUMED_BYTES 0x2018 /* Consumed number of bytes to 168 decode a frame */ 169 #define S5P_FIMV_SI_DISPLAY_STATUS 0x201c /* status of decoded picture */ 170 171 #define S5P_FIMV_SI_CH0_SB_ST_ADR 0x2044 /* start addr of stream buf */ 172 #define S5P_FIMV_SI_CH0_SB_FRM_SIZE 0x2048 /* size of stream buf */ 173 #define S5P_FIMV_SI_CH0_DESC_ADR 0x204c /* addr of descriptor buf */ 174 #define S5P_FIMV_SI_CH0_CPB_SIZE 0x2058 /* max size of coded pic. buf */ 175 #define S5P_FIMV_SI_CH0_DESC_SIZE 0x205c /* max size of descriptor buf */ 176 177 #define S5P_FIMV_SI_CH1_SB_ST_ADR 0x2084 /* start addr of stream buf */ 178 #define S5P_FIMV_SI_CH1_SB_FRM_SIZE 0x2088 /* size of stream buf */ 179 #define S5P_FIMV_SI_CH1_DESC_ADR 0x208c /* addr of descriptor buf */ 180 #define S5P_FIMV_SI_CH1_CPB_SIZE 0x2098 /* max size of coded pic. buf */ 181 #define S5P_FIMV_SI_CH1_DESC_SIZE 0x209c /* max size of descriptor buf */ 182 183 #define S5P_FIMV_CRC_LUMA0 0x2030 /* luma crc data per frame 184 (top field) */ 185 #define S5P_FIMV_CRC_CHROMA0 0x2034 /* chroma crc data per frame 186 (top field) */ 187 #define S5P_FIMV_CRC_LUMA1 0x2038 /* luma crc data per bottom 188 field */ 189 #define S5P_FIMV_CRC_CHROMA1 0x203c /* chroma crc data per bottom 190 field */ 191 192 /* Display status */ 193 #define S5P_FIMV_DEC_STATUS_DECODING_ONLY 0 194 #define S5P_FIMV_DEC_STATUS_DECODING_DISPLAY 1 195 #define S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 2 196 #define S5P_FIMV_DEC_STATUS_DECODING_EMPTY 3 197 #define S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK 7 198 #define S5P_FIMV_DEC_STATUS_PROGRESSIVE (0<<3) 199 #define S5P_FIMV_DEC_STATUS_INTERLACE (1<<3) 200 #define S5P_FIMV_DEC_STATUS_INTERLACE_MASK (1<<3) 201 #define S5P_FIMV_DEC_STATUS_CRC_NUMBER_TWO (0<<4) 202 #define S5P_FIMV_DEC_STATUS_CRC_NUMBER_FOUR (1<<4) 203 #define S5P_FIMV_DEC_STATUS_CRC_NUMBER_MASK (1<<4) 204 #define S5P_FIMV_DEC_STATUS_CRC_GENERATED (1<<5) 205 #define S5P_FIMV_DEC_STATUS_CRC_NOT_GENERATED (0<<5) 206 #define S5P_FIMV_DEC_STATUS_CRC_MASK (1<<5) 207 208 #define S5P_FIMV_DEC_STATUS_RESOLUTION_MASK (3<<4) 209 #define S5P_FIMV_DEC_STATUS_RESOLUTION_INC (1<<4) 210 #define S5P_FIMV_DEC_STATUS_RESOLUTION_DEC (2<<4) 211 212 /* Decode frame address */ 213 #define S5P_FIMV_DECODE_Y_ADR 0x2024 214 #define S5P_FIMV_DECODE_C_ADR 0x2028 215 216 /* Decoded frame tpe */ 217 #define S5P_FIMV_DECODE_FRAME_TYPE 0x2020 218 #define S5P_FIMV_DECODE_FRAME_MASK 7 219 220 #define S5P_FIMV_DECODE_FRAME_SKIPPED 0 221 #define S5P_FIMV_DECODE_FRAME_I_FRAME 1 222 #define S5P_FIMV_DECODE_FRAME_P_FRAME 2 223 #define S5P_FIMV_DECODE_FRAME_B_FRAME 3 224 #define S5P_FIMV_DECODE_FRAME_OTHER_FRAME 4 225 226 /* Sizes of buffers required for decoding */ 227 #define S5P_FIMV_DEC_NB_IP_SIZE (32 * 1024) 228 #define S5P_FIMV_DEC_VERT_NB_MV_SIZE (16 * 1024) 229 #define S5P_FIMV_DEC_NB_DCAC_SIZE (16 * 1024) 230 #define S5P_FIMV_DEC_UPNB_MV_SIZE (68 * 1024) 231 #define S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE (136 * 1024) 232 #define S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE (32 * 1024) 233 #define S5P_FIMV_DEC_VC1_BITPLANE_SIZE (2 * 1024) 234 #define S5P_FIMV_DEC_STX_PARSER_SIZE (68 * 1024) 235 236 #define S5P_FIMV_DEC_BUF_ALIGN (8 * 1024) 237 #define S5P_FIMV_ENC_BUF_ALIGN (8 * 1024) 238 #define S5P_FIMV_NV12M_HALIGN 16 239 #define S5P_FIMV_NV12M_LVALIGN 16 240 #define S5P_FIMV_NV12M_CVALIGN 8 241 #define S5P_FIMV_NV12MT_HALIGN 128 242 #define S5P_FIMV_NV12MT_VALIGN 32 243 #define S5P_FIMV_NV12M_SALIGN 2048 244 #define S5P_FIMV_NV12MT_SALIGN 8192 245 246 /* Sizes of buffers required for encoding */ 247 #define S5P_FIMV_ENC_UPMV_SIZE 0x10000 248 #define S5P_FIMV_ENC_COLFLG_SIZE 0x10000 249 #define S5P_FIMV_ENC_INTRAMD_SIZE 0x10000 250 #define S5P_FIMV_ENC_INTRAPRED_SIZE 0x4000 251 #define S5P_FIMV_ENC_NBORINFO_SIZE 0x10000 252 #define S5P_FIMV_ENC_ACDCCOEF_SIZE 0x10000 253 254 /* Encoder */ 255 #define S5P_FIMV_ENC_SI_STRM_SIZE 0x2004 /* stream size */ 256 #define S5P_FIMV_ENC_SI_PIC_CNT 0x2008 /* picture count */ 257 #define S5P_FIMV_ENC_SI_WRITE_PTR 0x200c /* write pointer */ 258 #define S5P_FIMV_ENC_SI_SLICE_TYPE 0x2010 /* slice type(I/P/B/IDR) */ 259 #define S5P_FIMV_ENC_SI_SLICE_TYPE_NON_CODED 0 260 #define S5P_FIMV_ENC_SI_SLICE_TYPE_I 1 261 #define S5P_FIMV_ENC_SI_SLICE_TYPE_P 2 262 #define S5P_FIMV_ENC_SI_SLICE_TYPE_B 3 263 #define S5P_FIMV_ENC_SI_SLICE_TYPE_SKIPPED 4 264 #define S5P_FIMV_ENC_SI_SLICE_TYPE_OTHERS 5 265 #define S5P_FIMV_ENCODED_Y_ADDR 0x2014 /* the addr of the encoded 266 luma pic */ 267 #define S5P_FIMV_ENCODED_C_ADDR 0x2018 /* the addr of the encoded 268 chroma pic */ 269 270 #define S5P_FIMV_ENC_SI_CH0_SB_ADR 0x2044 /* addr of stream buf */ 271 #define S5P_FIMV_ENC_SI_CH0_SB_SIZE 0x204c /* size of stream buf */ 272 #define S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR 0x2050 /* current Luma addr */ 273 #define S5P_FIMV_ENC_SI_CH0_CUR_C_ADR 0x2054 /* current Chroma addr */ 274 #define S5P_FIMV_ENC_SI_CH0_FRAME_INS 0x2058 /* frame insertion */ 275 276 #define S5P_FIMV_ENC_SI_CH1_SB_ADR 0x2084 /* addr of stream buf */ 277 #define S5P_FIMV_ENC_SI_CH1_SB_SIZE 0x208c /* size of stream buf */ 278 #define S5P_FIMV_ENC_SI_CH1_CUR_Y_ADR 0x2090 /* current Luma addr */ 279 #define S5P_FIMV_ENC_SI_CH1_CUR_C_ADR 0x2094 /* current Chroma addr */ 280 #define S5P_FIMV_ENC_SI_CH1_FRAME_INS 0x2098 /* frame insertion */ 281 282 #define S5P_FIMV_ENC_PIC_TYPE_CTRL 0xc504 /* pic type level control */ 283 #define S5P_FIMV_ENC_B_RECON_WRITE_ON 0xc508 /* B frame recon write ctrl */ 284 #define S5P_FIMV_ENC_MSLICE_CTRL 0xc50c /* multi slice control */ 285 #define S5P_FIMV_ENC_MSLICE_MB 0xc510 /* MB number in the one slice */ 286 #define S5P_FIMV_ENC_MSLICE_BIT 0xc514 /* bit count for one slice */ 287 #define S5P_FIMV_ENC_CIR_CTRL 0xc518 /* number of intra refresh MB */ 288 #define S5P_FIMV_ENC_MAP_FOR_CUR 0xc51c /* linear or tiled mode */ 289 #define S5P_FIMV_ENC_PADDING_CTRL 0xc520 /* padding control */ 290 291 #define S5P_FIMV_ENC_RC_CONFIG 0xc5a0 /* RC config */ 292 #define S5P_FIMV_ENC_RC_BIT_RATE 0xc5a8 /* bit rate */ 293 #define S5P_FIMV_ENC_RC_QBOUND 0xc5ac /* max/min QP */ 294 #define S5P_FIMV_ENC_RC_RPARA 0xc5b0 /* rate control reaction coeff */ 295 #define S5P_FIMV_ENC_RC_MB_CTRL 0xc5b4 /* MB adaptive scaling */ 296 297 /* Encoder for H264 only */ 298 #define S5P_FIMV_ENC_H264_ENTROPY_MODE 0xd004 /* CAVLC or CABAC */ 299 #define S5P_FIMV_ENC_H264_ALPHA_OFF 0xd008 /* loop filter alpha offset */ 300 #define S5P_FIMV_ENC_H264_BETA_OFF 0xd00c /* loop filter beta offset */ 301 #define S5P_FIMV_ENC_H264_NUM_OF_REF 0xd010 /* number of reference for P/B */ 302 #define S5P_FIMV_ENC_H264_TRANS_FLAG 0xd034 /* 8x8 transform flag in PPS & 303 high profile */ 304 305 #define S5P_FIMV_ENC_RC_FRAME_RATE 0xd0d0 /* frame rate */ 306 307 /* Encoder for MPEG4 only */ 308 #define S5P_FIMV_ENC_MPEG4_QUART_PXL 0xe008 /* qpel interpolation ctrl */ 309 310 /* Additional */ 311 #define S5P_FIMV_SI_CH0_DPB_CONF_CTRL 0x2068 /* DPB Config Control Register */ 312 #define S5P_FIMV_SLICE_INT_MASK 1 313 #define S5P_FIMV_SLICE_INT_SHIFT 31 314 #define S5P_FIMV_DDELAY_ENA_SHIFT 30 315 #define S5P_FIMV_DDELAY_VAL_MASK 0xff 316 #define S5P_FIMV_DDELAY_VAL_SHIFT 16 317 #define S5P_FIMV_DPB_COUNT_MASK 0xffff 318 #define S5P_FIMV_DPB_FLUSH_MASK 1 319 #define S5P_FIMV_DPB_FLUSH_SHIFT 14 320 321 322 #define S5P_FIMV_SI_CH0_RELEASE_BUF 0x2060 /* DPB release buffer register */ 323 #define S5P_FIMV_SI_CH0_HOST_WR_ADR 0x2064 /* address of shared memory */ 324 325 /* Codec numbers */ 326 #define S5P_FIMV_CODEC_NONE -1 327 328 #define S5P_FIMV_CODEC_H264_DEC 0 329 #define S5P_FIMV_CODEC_VC1_DEC 1 330 #define S5P_FIMV_CODEC_MPEG4_DEC 2 331 #define S5P_FIMV_CODEC_MPEG2_DEC 3 332 #define S5P_FIMV_CODEC_H263_DEC 4 333 #define S5P_FIMV_CODEC_VC1RCV_DEC 5 334 335 #define S5P_FIMV_CODEC_H264_ENC 16 336 #define S5P_FIMV_CODEC_MPEG4_ENC 17 337 #define S5P_FIMV_CODEC_H263_ENC 18 338 339 /* Channel Control Register */ 340 #define S5P_FIMV_CH_SEQ_HEADER 1 341 #define S5P_FIMV_CH_FRAME_START 2 342 #define S5P_FIMV_CH_LAST_FRAME 3 343 #define S5P_FIMV_CH_INIT_BUFS 4 344 #define S5P_FIMV_CH_FRAME_START_REALLOC 5 345 #define S5P_FIMV_CH_MASK 7 346 #define S5P_FIMV_CH_SHIFT 16 347 348 349 /* Host to RISC command */ 350 #define S5P_FIMV_H2R_CMD_EMPTY 0 351 #define S5P_FIMV_H2R_CMD_OPEN_INSTANCE 1 352 #define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE 2 353 #define S5P_FIMV_H2R_CMD_SYS_INIT 3 354 #define S5P_FIMV_H2R_CMD_FLUSH 4 355 #define S5P_FIMV_H2R_CMD_SLEEP 5 356 #define S5P_FIMV_H2R_CMD_WAKEUP 6 357 358 #define S5P_FIMV_R2H_CMD_EMPTY 0 359 #define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET 1 360 #define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET 2 361 #define S5P_FIMV_R2H_CMD_RSV_RET 3 362 #define S5P_FIMV_R2H_CMD_SEQ_DONE_RET 4 363 #define S5P_FIMV_R2H_CMD_FRAME_DONE_RET 5 364 #define S5P_FIMV_R2H_CMD_SLICE_DONE_RET 6 365 #define S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET 7 366 #define S5P_FIMV_R2H_CMD_SYS_INIT_RET 8 367 #define S5P_FIMV_R2H_CMD_FW_STATUS_RET 9 368 #define S5P_FIMV_R2H_CMD_SLEEP_RET 10 369 #define S5P_FIMV_R2H_CMD_WAKEUP_RET 11 370 #define S5P_FIMV_R2H_CMD_FLUSH_RET 12 371 #define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET 15 372 #define S5P_FIMV_R2H_CMD_EDFU_INIT_RET 16 373 #define S5P_FIMV_R2H_CMD_ERR_RET 32 374 375 /* Error handling defines */ 376 #define S5P_FIMV_ERR_WARNINGS_START 145 377 #define S5P_FIMV_ERR_DEC_MASK 0xFFFF 378 #define S5P_FIMV_ERR_DEC_SHIFT 0 379 #define S5P_FIMV_ERR_DSPL_MASK 0xFFFF0000 380 #define S5P_FIMV_ERR_DSPL_SHIFT 16 381 382 /* Shared memory registers' offsets */ 383 384 /* An offset of the start position in the stream when 385 * the start position is not aligned */ 386 #define S5P_FIMV_SHARED_CROP_INFO_H 0x0020 387 #define S5P_FIMV_SHARED_CROP_LEFT_MASK 0xFFFF 388 #define S5P_FIMV_SHARED_CROP_LEFT_SHIFT 0 389 #define S5P_FIMV_SHARED_CROP_RIGHT_MASK 0xFFFF0000 390 #define S5P_FIMV_SHARED_CROP_RIGHT_SHIFT 16 391 #define S5P_FIMV_SHARED_CROP_INFO_V 0x0024 392 #define S5P_FIMV_SHARED_CROP_TOP_MASK 0xFFFF 393 #define S5P_FIMV_SHARED_CROP_TOP_SHIFT 0 394 #define S5P_FIMV_SHARED_CROP_BOTTOM_MASK 0xFFFF0000 395 #define S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT 16 396 #define S5P_FIMV_SHARED_SET_FRAME_TAG 0x0004 397 #define S5P_FIMV_SHARED_GET_FRAME_TAG_TOP 0x0008 398 #define S5P_FIMV_SHARED_GET_FRAME_TAG_BOT 0x000C 399 #define S5P_FIMV_SHARED_START_BYTE_NUM 0x0018 400 #define S5P_FIMV_SHARED_RC_VOP_TIMING 0x0030 401 #define S5P_FIMV_SHARED_LUMA_DPB_SIZE 0x0064 402 #define S5P_FIMV_SHARED_CHROMA_DPB_SIZE 0x0068 403 #define S5P_FIMV_SHARED_MV_SIZE 0x006C 404 #define S5P_FIMV_SHARED_PIC_TIME_TOP 0x0010 405 #define S5P_FIMV_SHARED_PIC_TIME_BOTTOM 0x0014 406 #define S5P_FIMV_SHARED_EXT_ENC_CONTROL 0x0028 407 #define S5P_FIMV_SHARED_P_B_FRAME_QP 0x0070 408 #define S5P_FIMV_SHARED_ASPECT_RATIO_IDC 0x0074 409 #define S5P_FIMV_SHARED_EXTENDED_SAR 0x0078 410 #define S5P_FIMV_SHARED_H264_I_PERIOD 0x009C 411 #define S5P_FIMV_SHARED_RC_CONTROL_CONFIG 0x00A0 412 413 #endif /* _REGS_FIMV_H */ 414