1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interconnect/qcom,msm8974.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8974.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/reset/qcom,gcc-msm8974.h> 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 xo_board: xo_board { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <19200000>; 22 }; 23 24 sleep_clk: sleep_clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <32768>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 interrupts = <GIC_PPI 9 0xf04>; 35 36 CPU0: cpu@0 { 37 compatible = "qcom,krait"; 38 enable-method = "qcom,kpss-acc-v2"; 39 device_type = "cpu"; 40 reg = <0>; 41 next-level-cache = <&L2>; 42 qcom,acc = <&acc0>; 43 qcom,saw = <&saw0>; 44 cpu-idle-states = <&CPU_SPC>; 45 }; 46 47 CPU1: cpu@1 { 48 compatible = "qcom,krait"; 49 enable-method = "qcom,kpss-acc-v2"; 50 device_type = "cpu"; 51 reg = <1>; 52 next-level-cache = <&L2>; 53 qcom,acc = <&acc1>; 54 qcom,saw = <&saw1>; 55 cpu-idle-states = <&CPU_SPC>; 56 }; 57 58 CPU2: cpu@2 { 59 compatible = "qcom,krait"; 60 enable-method = "qcom,kpss-acc-v2"; 61 device_type = "cpu"; 62 reg = <2>; 63 next-level-cache = <&L2>; 64 qcom,acc = <&acc2>; 65 qcom,saw = <&saw2>; 66 cpu-idle-states = <&CPU_SPC>; 67 }; 68 69 CPU3: cpu@3 { 70 compatible = "qcom,krait"; 71 enable-method = "qcom,kpss-acc-v2"; 72 device_type = "cpu"; 73 reg = <3>; 74 next-level-cache = <&L2>; 75 qcom,acc = <&acc3>; 76 qcom,saw = <&saw3>; 77 cpu-idle-states = <&CPU_SPC>; 78 }; 79 80 L2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 qcom,saw = <&saw_l2>; 84 }; 85 86 idle-states { 87 CPU_SPC: spc { 88 compatible = "qcom,idle-state-spc", 89 "arm,idle-state"; 90 entry-latency-us = <150>; 91 exit-latency-us = <200>; 92 min-residency-us = <2000>; 93 }; 94 }; 95 }; 96 97 firmware { 98 scm { 99 compatible = "qcom,scm-msm8974", "qcom,scm"; 100 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 101 clock-names = "core", "bus", "iface"; 102 }; 103 }; 104 105 memory { 106 device_type = "memory"; 107 reg = <0x0 0x0>; 108 }; 109 110 pmu { 111 compatible = "qcom,krait-pmu"; 112 interrupts = <GIC_PPI 7 0xf04>; 113 }; 114 115 reserved-memory { 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges; 119 120 mpss_region: mpss@8000000 { 121 reg = <0x08000000 0x5100000>; 122 no-map; 123 }; 124 125 mba_region: mba@d100000 { 126 reg = <0x0d100000 0x100000>; 127 no-map; 128 }; 129 130 wcnss_region: wcnss@d200000 { 131 reg = <0x0d200000 0xa00000>; 132 no-map; 133 }; 134 135 adsp_region: adsp@dc00000 { 136 reg = <0x0dc00000 0x1900000>; 137 no-map; 138 }; 139 140 venus_region: memory@f500000 { 141 reg = <0x0f500000 0x500000>; 142 no-map; 143 }; 144 145 smem_region: smem@fa00000 { 146 reg = <0xfa00000 0x200000>; 147 no-map; 148 }; 149 150 tz_region: memory@fc00000 { 151 reg = <0x0fc00000 0x160000>; 152 no-map; 153 }; 154 155 rfsa_mem: memory@fd60000 { 156 reg = <0x0fd60000 0x20000>; 157 no-map; 158 }; 159 160 rmtfs@fd80000 { 161 compatible = "qcom,rmtfs-mem"; 162 reg = <0x0fd80000 0x180000>; 163 no-map; 164 165 qcom,client-id = <1>; 166 }; 167 }; 168 169 smem { 170 compatible = "qcom,smem"; 171 172 memory-region = <&smem_region>; 173 qcom,rpm-msg-ram = <&rpm_msg_ram>; 174 175 hwlocks = <&tcsr_mutex 3>; 176 }; 177 178 smp2p-adsp { 179 compatible = "qcom,smp2p"; 180 qcom,smem = <443>, <429>; 181 182 interrupt-parent = <&intc>; 183 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 184 185 qcom,ipc = <&apcs 8 10>; 186 187 qcom,local-pid = <0>; 188 qcom,remote-pid = <2>; 189 190 adsp_smp2p_out: master-kernel { 191 qcom,entry-name = "master-kernel"; 192 #qcom,smem-state-cells = <1>; 193 }; 194 195 adsp_smp2p_in: slave-kernel { 196 qcom,entry-name = "slave-kernel"; 197 198 interrupt-controller; 199 #interrupt-cells = <2>; 200 }; 201 }; 202 203 smp2p-modem { 204 compatible = "qcom,smp2p"; 205 qcom,smem = <435>, <428>; 206 207 interrupt-parent = <&intc>; 208 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 209 210 qcom,ipc = <&apcs 8 14>; 211 212 qcom,local-pid = <0>; 213 qcom,remote-pid = <1>; 214 215 modem_smp2p_out: master-kernel { 216 qcom,entry-name = "master-kernel"; 217 #qcom,smem-state-cells = <1>; 218 }; 219 220 modem_smp2p_in: slave-kernel { 221 qcom,entry-name = "slave-kernel"; 222 223 interrupt-controller; 224 #interrupt-cells = <2>; 225 }; 226 }; 227 228 smp2p-wcnss { 229 compatible = "qcom,smp2p"; 230 qcom,smem = <451>, <431>; 231 232 interrupt-parent = <&intc>; 233 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 234 235 qcom,ipc = <&apcs 8 18>; 236 237 qcom,local-pid = <0>; 238 qcom,remote-pid = <4>; 239 240 wcnss_smp2p_out: master-kernel { 241 qcom,entry-name = "master-kernel"; 242 243 #qcom,smem-state-cells = <1>; 244 }; 245 246 wcnss_smp2p_in: slave-kernel { 247 qcom,entry-name = "slave-kernel"; 248 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 }; 252 }; 253 254 smsm { 255 compatible = "qcom,smsm"; 256 257 #address-cells = <1>; 258 #size-cells = <0>; 259 260 qcom,ipc-1 = <&apcs 8 13>; 261 qcom,ipc-2 = <&apcs 8 9>; 262 qcom,ipc-3 = <&apcs 8 19>; 263 264 apps_smsm: apps@0 { 265 reg = <0>; 266 267 #qcom,smem-state-cells = <1>; 268 }; 269 270 modem_smsm: modem@1 { 271 reg = <1>; 272 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 273 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 }; 277 278 adsp_smsm: adsp@2 { 279 reg = <2>; 280 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 281 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 }; 285 286 wcnss_smsm: wcnss@7 { 287 reg = <7>; 288 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 289 290 interrupt-controller; 291 #interrupt-cells = <2>; 292 }; 293 }; 294 295 smd { 296 compatible = "qcom,smd"; 297 298 rpm { 299 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 300 qcom,ipc = <&apcs 8 0>; 301 qcom,smd-edge = <15>; 302 303 rpm_requests: rpm_requests { 304 compatible = "qcom,rpm-msm8974"; 305 qcom,smd-channels = "rpm_requests"; 306 307 rpmcc: clock-controller { 308 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; 309 #clock-cells = <1>; 310 }; 311 }; 312 }; 313 }; 314 315 soc: soc { 316 #address-cells = <1>; 317 #size-cells = <1>; 318 ranges; 319 compatible = "simple-bus"; 320 321 intc: interrupt-controller@f9000000 { 322 compatible = "qcom,msm-qgic2"; 323 interrupt-controller; 324 #interrupt-cells = <3>; 325 reg = <0xf9000000 0x1000>, 326 <0xf9002000 0x1000>; 327 }; 328 329 apcs: syscon@f9011000 { 330 compatible = "syscon"; 331 reg = <0xf9011000 0x1000>; 332 }; 333 334 timer@f9020000 { 335 #address-cells = <1>; 336 #size-cells = <1>; 337 ranges; 338 compatible = "arm,armv7-timer-mem"; 339 reg = <0xf9020000 0x1000>; 340 clock-frequency = <19200000>; 341 342 frame@f9021000 { 343 frame-number = <0>; 344 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 346 reg = <0xf9021000 0x1000>, 347 <0xf9022000 0x1000>; 348 }; 349 350 frame@f9023000 { 351 frame-number = <1>; 352 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 353 reg = <0xf9023000 0x1000>; 354 status = "disabled"; 355 }; 356 357 frame@f9024000 { 358 frame-number = <2>; 359 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 360 reg = <0xf9024000 0x1000>; 361 status = "disabled"; 362 }; 363 364 frame@f9025000 { 365 frame-number = <3>; 366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 367 reg = <0xf9025000 0x1000>; 368 status = "disabled"; 369 }; 370 371 frame@f9026000 { 372 frame-number = <4>; 373 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 374 reg = <0xf9026000 0x1000>; 375 status = "disabled"; 376 }; 377 378 frame@f9027000 { 379 frame-number = <5>; 380 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 381 reg = <0xf9027000 0x1000>; 382 status = "disabled"; 383 }; 384 385 frame@f9028000 { 386 frame-number = <6>; 387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 388 reg = <0xf9028000 0x1000>; 389 status = "disabled"; 390 }; 391 }; 392 393 saw0: power-controller@f9089000 { 394 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 395 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; 396 }; 397 398 saw1: power-controller@f9099000 { 399 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 400 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; 401 }; 402 403 saw2: power-controller@f90a9000 { 404 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 405 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; 406 }; 407 408 saw3: power-controller@f90b9000 { 409 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; 410 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; 411 }; 412 413 saw_l2: power-controller@f9012000 { 414 compatible = "qcom,saw2"; 415 reg = <0xf9012000 0x1000>; 416 regulator; 417 }; 418 419 acc0: clock-controller@f9088000 { 420 compatible = "qcom,kpss-acc-v2"; 421 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; 422 }; 423 424 acc1: clock-controller@f9098000 { 425 compatible = "qcom,kpss-acc-v2"; 426 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; 427 }; 428 429 acc2: clock-controller@f90a8000 { 430 compatible = "qcom,kpss-acc-v2"; 431 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; 432 }; 433 434 acc3: clock-controller@f90b8000 { 435 compatible = "qcom,kpss-acc-v2"; 436 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; 437 }; 438 439 sdhc_1: mmc@f9824900 { 440 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 441 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 442 reg-names = "hc", "core"; 443 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 445 interrupt-names = "hc_irq", "pwr_irq"; 446 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 447 <&gcc GCC_SDCC1_APPS_CLK>, 448 <&xo_board>; 449 clock-names = "iface", "core", "xo"; 450 bus-width = <8>; 451 non-removable; 452 453 status = "disabled"; 454 }; 455 456 sdhc_3: mmc@f9864900 { 457 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 458 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 459 reg-names = "hc", "core"; 460 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 462 interrupt-names = "hc_irq", "pwr_irq"; 463 clocks = <&gcc GCC_SDCC3_AHB_CLK>, 464 <&gcc GCC_SDCC3_APPS_CLK>, 465 <&xo_board>; 466 clock-names = "iface", "core", "xo"; 467 bus-width = <4>; 468 469 #address-cells = <1>; 470 #size-cells = <0>; 471 472 status = "disabled"; 473 }; 474 475 sdhc_2: mmc@f98a4900 { 476 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 477 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 478 reg-names = "hc", "core"; 479 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-names = "hc_irq", "pwr_irq"; 482 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 483 <&gcc GCC_SDCC2_APPS_CLK>, 484 <&xo_board>; 485 clock-names = "iface", "core", "xo"; 486 bus-width = <4>; 487 488 #address-cells = <1>; 489 #size-cells = <0>; 490 491 status = "disabled"; 492 }; 493 494 blsp1_uart1: serial@f991d000 { 495 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 496 reg = <0xf991d000 0x1000>; 497 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 499 clock-names = "core", "iface"; 500 status = "disabled"; 501 }; 502 503 blsp1_uart2: serial@f991e000 { 504 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 505 reg = <0xf991e000 0x1000>; 506 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 508 clock-names = "core", "iface"; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&blsp1_uart2_default>; 511 status = "disabled"; 512 }; 513 514 blsp1_i2c1: i2c@f9923000 { 515 status = "disabled"; 516 compatible = "qcom,i2c-qup-v2.1.1"; 517 reg = <0xf9923000 0x1000>; 518 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 520 clock-names = "core", "iface"; 521 pinctrl-names = "default", "sleep"; 522 pinctrl-0 = <&blsp1_i2c1_default>; 523 pinctrl-1 = <&blsp1_i2c1_sleep>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 }; 527 528 blsp1_i2c2: i2c@f9924000 { 529 status = "disabled"; 530 compatible = "qcom,i2c-qup-v2.1.1"; 531 reg = <0xf9924000 0x1000>; 532 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 534 clock-names = "core", "iface"; 535 pinctrl-names = "default", "sleep"; 536 pinctrl-0 = <&blsp1_i2c2_default>; 537 pinctrl-1 = <&blsp1_i2c2_sleep>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 }; 541 542 blsp1_i2c3: i2c@f9925000 { 543 status = "disabled"; 544 compatible = "qcom,i2c-qup-v2.1.1"; 545 reg = <0xf9925000 0x1000>; 546 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 548 clock-names = "core", "iface"; 549 pinctrl-names = "default", "sleep"; 550 pinctrl-0 = <&blsp1_i2c3_default>; 551 pinctrl-1 = <&blsp1_i2c3_sleep>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 }; 555 556 blsp1_i2c6: i2c@f9928000 { 557 status = "disabled"; 558 compatible = "qcom,i2c-qup-v2.1.1"; 559 reg = <0xf9928000 0x1000>; 560 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 562 clock-names = "core", "iface"; 563 pinctrl-names = "default", "sleep"; 564 pinctrl-0 = <&blsp1_i2c6_default>; 565 pinctrl-1 = <&blsp1_i2c6_sleep>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 }; 569 570 blsp2_dma: dma-controller@f9944000 { 571 compatible = "qcom,bam-v1.4.0"; 572 reg = <0xf9944000 0x19000>; 573 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 575 clock-names = "bam_clk"; 576 #dma-cells = <1>; 577 qcom,ee = <0>; 578 }; 579 580 blsp2_uart1: serial@f995d000 { 581 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 582 reg = <0xf995d000 0x1000>; 583 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 585 clock-names = "core", "iface"; 586 pinctrl-names = "default", "sleep"; 587 pinctrl-0 = <&blsp2_uart1_default>; 588 pinctrl-1 = <&blsp2_uart1_sleep>; 589 status = "disabled"; 590 }; 591 592 blsp2_uart2: serial@f995e000 { 593 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 594 reg = <0xf995e000 0x1000>; 595 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 597 clock-names = "core", "iface"; 598 status = "disabled"; 599 }; 600 601 blsp2_uart4: serial@f9960000 { 602 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 603 reg = <0xf9960000 0x1000>; 604 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 606 clock-names = "core", "iface"; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&blsp2_uart4_default>; 609 status = "disabled"; 610 }; 611 612 blsp2_i2c2: i2c@f9964000 { 613 status = "disabled"; 614 compatible = "qcom,i2c-qup-v2.1.1"; 615 reg = <0xf9964000 0x1000>; 616 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 618 clock-names = "core", "iface"; 619 pinctrl-names = "default", "sleep"; 620 pinctrl-0 = <&blsp2_i2c2_default>; 621 pinctrl-1 = <&blsp2_i2c2_sleep>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 }; 625 626 blsp2_i2c5: i2c@f9967000 { 627 status = "disabled"; 628 compatible = "qcom,i2c-qup-v2.1.1"; 629 reg = <0xf9967000 0x1000>; 630 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 632 clock-names = "core", "iface"; 633 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 634 dma-names = "tx", "rx"; 635 pinctrl-names = "default", "sleep"; 636 pinctrl-0 = <&blsp2_i2c5_default>; 637 pinctrl-1 = <&blsp2_i2c5_sleep>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 }; 641 642 blsp2_i2c6: i2c@f9968000 { 643 status = "disabled"; 644 compatible = "qcom,i2c-qup-v2.1.1"; 645 reg = <0xf9968000 0x1000>; 646 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 648 clock-names = "core", "iface"; 649 pinctrl-names = "default", "sleep"; 650 pinctrl-0 = <&blsp2_i2c6_default>; 651 pinctrl-1 = <&blsp2_i2c6_sleep>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 }; 655 656 otg: usb@f9a55000 { 657 compatible = "qcom,ci-hdrc"; 658 reg = <0xf9a55000 0x200>, 659 <0xf9a55200 0x200>; 660 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 662 <&gcc GCC_USB_HS_SYSTEM_CLK>; 663 clock-names = "iface", "core"; 664 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 665 assigned-clock-rates = <75000000>; 666 resets = <&gcc GCC_USB_HS_BCR>; 667 reset-names = "core"; 668 phy_type = "ulpi"; 669 dr_mode = "otg"; 670 ahb-burst-config = <0>; 671 phy-names = "usb-phy"; 672 status = "disabled"; 673 #reset-cells = <1>; 674 675 ulpi { 676 usb_hs1_phy: phy@a { 677 compatible = "qcom,usb-hs-phy-msm8974", 678 "qcom,usb-hs-phy"; 679 #phy-cells = <0>; 680 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 681 clock-names = "ref", "sleep"; 682 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; 683 reset-names = "phy", "por"; 684 status = "disabled"; 685 }; 686 687 usb_hs2_phy: phy@b { 688 compatible = "qcom,usb-hs-phy-msm8974", 689 "qcom,usb-hs-phy"; 690 #phy-cells = <0>; 691 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>; 692 clock-names = "ref", "sleep"; 693 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>; 694 reset-names = "phy", "por"; 695 status = "disabled"; 696 }; 697 }; 698 }; 699 700 rng@f9bff000 { 701 compatible = "qcom,prng"; 702 reg = <0xf9bff000 0x200>; 703 clocks = <&gcc GCC_PRNG_AHB_CLK>; 704 clock-names = "core"; 705 }; 706 707 pronto: remoteproc@fb21b000 { 708 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 709 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; 710 reg-names = "ccu", "dxe", "pmu"; 711 712 memory-region = <&wcnss_region>; 713 714 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 715 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 716 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 717 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 718 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 719 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 720 721 qcom,smem-states = <&wcnss_smp2p_out 0>; 722 qcom,smem-state-names = "stop"; 723 724 status = "disabled"; 725 726 iris { 727 compatible = "qcom,wcn3680"; 728 729 clocks = <&rpmcc RPM_SMD_CXO_A2>; 730 clock-names = "xo"; 731 }; 732 733 smd-edge { 734 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 735 736 qcom,ipc = <&apcs 8 17>; 737 qcom,smd-edge = <6>; 738 739 wcnss { 740 compatible = "qcom,wcnss"; 741 qcom,smd-channels = "WCNSS_CTRL"; 742 status = "disabled"; 743 744 qcom,mmio = <&pronto>; 745 746 bt { 747 compatible = "qcom,wcnss-bt"; 748 }; 749 750 wifi { 751 compatible = "qcom,wcnss-wlan"; 752 753 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 754 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 755 interrupt-names = "tx", "rx"; 756 757 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 758 qcom,smem-state-names = "tx-enable", 759 "tx-rings-empty"; 760 }; 761 }; 762 }; 763 }; 764 765 sram@fc190000 { 766 compatible = "qcom,msm8974-rpm-stats"; 767 reg = <0xfc190000 0x10000>; 768 }; 769 770 etf@fc307000 { 771 compatible = "arm,coresight-tmc", "arm,primecell"; 772 reg = <0xfc307000 0x1000>; 773 774 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 775 clock-names = "apb_pclk", "atclk"; 776 777 out-ports { 778 port { 779 etf_out: endpoint { 780 remote-endpoint = <&replicator_in>; 781 }; 782 }; 783 }; 784 785 in-ports { 786 port { 787 etf_in: endpoint { 788 remote-endpoint = <&merger_out>; 789 }; 790 }; 791 }; 792 }; 793 794 tpiu@fc318000 { 795 compatible = "arm,coresight-tpiu", "arm,primecell"; 796 reg = <0xfc318000 0x1000>; 797 798 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 799 clock-names = "apb_pclk", "atclk"; 800 801 in-ports { 802 port { 803 tpiu_in: endpoint { 804 remote-endpoint = <&replicator_out1>; 805 }; 806 }; 807 }; 808 }; 809 810 funnel@fc31a000 { 811 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 812 reg = <0xfc31a000 0x1000>; 813 814 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 815 clock-names = "apb_pclk", "atclk"; 816 817 in-ports { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 821 /* 822 * Not described input ports: 823 * 0 - not-connected 824 * 1 - connected trought funnel to Multimedia CPU 825 * 2 - connected to Wireless CPU 826 * 3 - not-connected 827 * 4 - not-connected 828 * 6 - not-connected 829 * 7 - connected to STM 830 */ 831 port@5 { 832 reg = <5>; 833 funnel1_in5: endpoint { 834 remote-endpoint = <&kpss_out>; 835 }; 836 }; 837 }; 838 839 out-ports { 840 port { 841 funnel1_out: endpoint { 842 remote-endpoint = <&merger_in1>; 843 }; 844 }; 845 }; 846 }; 847 848 funnel@fc31b000 { 849 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 850 reg = <0xfc31b000 0x1000>; 851 852 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 853 clock-names = "apb_pclk", "atclk"; 854 855 in-ports { 856 #address-cells = <1>; 857 #size-cells = <0>; 858 859 /* 860 * Not described input ports: 861 * 0 - connected trought funnel to Audio, Modem and 862 * Resource and Power Manager CPU's 863 * 2...7 - not-connected 864 */ 865 port@1 { 866 reg = <1>; 867 merger_in1: endpoint { 868 remote-endpoint = <&funnel1_out>; 869 }; 870 }; 871 }; 872 873 out-ports { 874 port { 875 merger_out: endpoint { 876 remote-endpoint = <&etf_in>; 877 }; 878 }; 879 }; 880 }; 881 882 replicator@fc31c000 { 883 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 884 reg = <0xfc31c000 0x1000>; 885 886 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 887 clock-names = "apb_pclk", "atclk"; 888 889 out-ports { 890 #address-cells = <1>; 891 #size-cells = <0>; 892 893 port@0 { 894 reg = <0>; 895 replicator_out0: endpoint { 896 remote-endpoint = <&etr_in>; 897 }; 898 }; 899 port@1 { 900 reg = <1>; 901 replicator_out1: endpoint { 902 remote-endpoint = <&tpiu_in>; 903 }; 904 }; 905 }; 906 907 in-ports { 908 port { 909 replicator_in: endpoint { 910 remote-endpoint = <&etf_out>; 911 }; 912 }; 913 }; 914 }; 915 916 etr@fc322000 { 917 compatible = "arm,coresight-tmc", "arm,primecell"; 918 reg = <0xfc322000 0x1000>; 919 920 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 921 clock-names = "apb_pclk", "atclk"; 922 923 in-ports { 924 port { 925 etr_in: endpoint { 926 remote-endpoint = <&replicator_out0>; 927 }; 928 }; 929 }; 930 }; 931 932 etm@fc33c000 { 933 compatible = "arm,coresight-etm4x", "arm,primecell"; 934 reg = <0xfc33c000 0x1000>; 935 936 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 937 clock-names = "apb_pclk", "atclk"; 938 939 cpu = <&CPU0>; 940 941 out-ports { 942 port { 943 etm0_out: endpoint { 944 remote-endpoint = <&kpss_in0>; 945 }; 946 }; 947 }; 948 }; 949 950 etm@fc33d000 { 951 compatible = "arm,coresight-etm4x", "arm,primecell"; 952 reg = <0xfc33d000 0x1000>; 953 954 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 955 clock-names = "apb_pclk", "atclk"; 956 957 cpu = <&CPU1>; 958 959 out-ports { 960 port { 961 etm1_out: endpoint { 962 remote-endpoint = <&kpss_in1>; 963 }; 964 }; 965 }; 966 }; 967 968 etm@fc33e000 { 969 compatible = "arm,coresight-etm4x", "arm,primecell"; 970 reg = <0xfc33e000 0x1000>; 971 972 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 973 clock-names = "apb_pclk", "atclk"; 974 975 cpu = <&CPU2>; 976 977 out-ports { 978 port { 979 etm2_out: endpoint { 980 remote-endpoint = <&kpss_in2>; 981 }; 982 }; 983 }; 984 }; 985 986 etm@fc33f000 { 987 compatible = "arm,coresight-etm4x", "arm,primecell"; 988 reg = <0xfc33f000 0x1000>; 989 990 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 991 clock-names = "apb_pclk", "atclk"; 992 993 cpu = <&CPU3>; 994 995 out-ports { 996 port { 997 etm3_out: endpoint { 998 remote-endpoint = <&kpss_in3>; 999 }; 1000 }; 1001 }; 1002 }; 1003 1004 /* KPSS funnel, only 4 inputs are used */ 1005 funnel@fc345000 { 1006 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1007 reg = <0xfc345000 0x1000>; 1008 1009 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1010 clock-names = "apb_pclk", "atclk"; 1011 1012 in-ports { 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 1016 port@0 { 1017 reg = <0>; 1018 kpss_in0: endpoint { 1019 remote-endpoint = <&etm0_out>; 1020 }; 1021 }; 1022 port@1 { 1023 reg = <1>; 1024 kpss_in1: endpoint { 1025 remote-endpoint = <&etm1_out>; 1026 }; 1027 }; 1028 port@2 { 1029 reg = <2>; 1030 kpss_in2: endpoint { 1031 remote-endpoint = <&etm2_out>; 1032 }; 1033 }; 1034 port@3 { 1035 reg = <3>; 1036 kpss_in3: endpoint { 1037 remote-endpoint = <&etm3_out>; 1038 }; 1039 }; 1040 }; 1041 1042 out-ports { 1043 port { 1044 kpss_out: endpoint { 1045 remote-endpoint = <&funnel1_in5>; 1046 }; 1047 }; 1048 }; 1049 }; 1050 1051 gcc: clock-controller@fc400000 { 1052 compatible = "qcom,gcc-msm8974"; 1053 #clock-cells = <1>; 1054 #reset-cells = <1>; 1055 #power-domain-cells = <1>; 1056 reg = <0xfc400000 0x4000>; 1057 }; 1058 1059 rpm_msg_ram: memory@fc428000 { 1060 compatible = "qcom,rpm-msg-ram"; 1061 reg = <0xfc428000 0x4000>; 1062 }; 1063 1064 bimc: interconnect@fc380000 { 1065 reg = <0xfc380000 0x6a000>; 1066 compatible = "qcom,msm8974-bimc"; 1067 #interconnect-cells = <1>; 1068 clock-names = "bus", "bus_a"; 1069 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 1070 <&rpmcc RPM_SMD_BIMC_A_CLK>; 1071 }; 1072 1073 snoc: interconnect@fc460000 { 1074 reg = <0xfc460000 0x4000>; 1075 compatible = "qcom,msm8974-snoc"; 1076 #interconnect-cells = <1>; 1077 clock-names = "bus", "bus_a"; 1078 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 1079 <&rpmcc RPM_SMD_SNOC_A_CLK>; 1080 }; 1081 1082 pnoc: interconnect@fc468000 { 1083 reg = <0xfc468000 0x4000>; 1084 compatible = "qcom,msm8974-pnoc"; 1085 #interconnect-cells = <1>; 1086 clock-names = "bus", "bus_a"; 1087 clocks = <&rpmcc RPM_SMD_PNOC_CLK>, 1088 <&rpmcc RPM_SMD_PNOC_A_CLK>; 1089 }; 1090 1091 ocmemnoc: interconnect@fc470000 { 1092 reg = <0xfc470000 0x4000>; 1093 compatible = "qcom,msm8974-ocmemnoc"; 1094 #interconnect-cells = <1>; 1095 clock-names = "bus", "bus_a"; 1096 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1097 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; 1098 }; 1099 1100 mmssnoc: interconnect@fc478000 { 1101 reg = <0xfc478000 0x4000>; 1102 compatible = "qcom,msm8974-mmssnoc"; 1103 #interconnect-cells = <1>; 1104 clock-names = "bus", "bus_a"; 1105 clocks = <&mmcc MMSS_S0_AXI_CLK>, 1106 <&mmcc MMSS_S0_AXI_CLK>; 1107 }; 1108 1109 cnoc: interconnect@fc480000 { 1110 reg = <0xfc480000 0x4000>; 1111 compatible = "qcom,msm8974-cnoc"; 1112 #interconnect-cells = <1>; 1113 clock-names = "bus", "bus_a"; 1114 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 1115 <&rpmcc RPM_SMD_CNOC_A_CLK>; 1116 }; 1117 1118 tsens: thermal-sensor@fc4a9000 { 1119 compatible = "qcom,msm8974-tsens"; 1120 reg = <0xfc4a9000 0x1000>, /* TM */ 1121 <0xfc4a8000 0x1000>; /* SROT */ 1122 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 1123 nvmem-cell-names = "calib", "calib_backup"; 1124 #qcom,sensors = <11>; 1125 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1126 interrupt-names = "uplow"; 1127 #thermal-sensor-cells = <1>; 1128 }; 1129 1130 restart@fc4ab000 { 1131 compatible = "qcom,pshold"; 1132 reg = <0xfc4ab000 0x4>; 1133 }; 1134 1135 qfprom: qfprom@fc4bc000 { 1136 compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; 1137 reg = <0xfc4bc000 0x1000>; 1138 #address-cells = <1>; 1139 #size-cells = <1>; 1140 tsens_calib: calib@d0 { 1141 reg = <0xd0 0x18>; 1142 }; 1143 tsens_backup: backup@440 { 1144 reg = <0x440 0x10>; 1145 }; 1146 }; 1147 1148 spmi_bus: spmi@fc4cf000 { 1149 compatible = "qcom,spmi-pmic-arb"; 1150 reg-names = "core", "intr", "cnfg"; 1151 reg = <0xfc4cf000 0x1000>, 1152 <0xfc4cb000 0x1000>, 1153 <0xfc4ca000 0x1000>; 1154 interrupt-names = "periph_irq"; 1155 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1156 qcom,ee = <0>; 1157 qcom,channel = <0>; 1158 #address-cells = <2>; 1159 #size-cells = <0>; 1160 interrupt-controller; 1161 #interrupt-cells = <4>; 1162 }; 1163 1164 bam_dmux_dma: dma-controller@fc834000 { 1165 compatible = "qcom,bam-v1.4.0"; 1166 reg = <0xfc834000 0x7000>; 1167 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1168 #dma-cells = <1>; 1169 qcom,ee = <0>; 1170 1171 num-channels = <6>; 1172 qcom,num-ees = <1>; 1173 qcom,powered-remotely; 1174 }; 1175 1176 remoteproc_mss: remoteproc@fc880000 { 1177 compatible = "qcom,msm8974-mss-pil"; 1178 reg = <0xfc880000 0x100>, <0xfc820000 0x020>; 1179 reg-names = "qdsp6", "rmb"; 1180 1181 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1182 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1183 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1184 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1185 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1186 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1187 1188 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1189 <&gcc GCC_MSS_CFG_AHB_CLK>, 1190 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1191 <&xo_board>; 1192 clock-names = "iface", "bus", "mem", "xo"; 1193 1194 resets = <&gcc GCC_MSS_RESTART>; 1195 reset-names = "mss_restart"; 1196 1197 qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; 1198 1199 qcom,smem-states = <&modem_smp2p_out 0>; 1200 qcom,smem-state-names = "stop"; 1201 1202 status = "disabled"; 1203 1204 mba { 1205 memory-region = <&mba_region>; 1206 }; 1207 1208 mpss { 1209 memory-region = <&mpss_region>; 1210 }; 1211 1212 bam_dmux: bam-dmux { 1213 compatible = "qcom,bam-dmux"; 1214 1215 interrupt-parent = <&modem_smsm>; 1216 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1217 interrupt-names = "pc", "pc-ack"; 1218 1219 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1220 qcom,smem-state-names = "pc", "pc-ack"; 1221 1222 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1223 dma-names = "tx", "rx"; 1224 }; 1225 1226 smd-edge { 1227 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1228 1229 qcom,ipc = <&apcs 8 12>; 1230 qcom,smd-edge = <0>; 1231 1232 label = "modem"; 1233 }; 1234 }; 1235 1236 tcsr_mutex_block: syscon@fd484000 { 1237 compatible = "syscon"; 1238 reg = <0xfd484000 0x2000>; 1239 }; 1240 1241 tcsr: syscon@fd4a0000 { 1242 compatible = "syscon"; 1243 reg = <0xfd4a0000 0x10000>; 1244 }; 1245 1246 tlmm: pinctrl@fd510000 { 1247 compatible = "qcom,msm8974-pinctrl"; 1248 reg = <0xfd510000 0x4000>; 1249 gpio-controller; 1250 gpio-ranges = <&tlmm 0 0 146>; 1251 #gpio-cells = <2>; 1252 interrupt-controller; 1253 #interrupt-cells = <2>; 1254 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1255 1256 sdc1_off: sdc1-off { 1257 clk { 1258 pins = "sdc1_clk"; 1259 bias-disable; 1260 drive-strength = <2>; 1261 }; 1262 1263 cmd { 1264 pins = "sdc1_cmd"; 1265 bias-pull-up; 1266 drive-strength = <2>; 1267 }; 1268 1269 data { 1270 pins = "sdc1_data"; 1271 bias-pull-up; 1272 drive-strength = <2>; 1273 }; 1274 }; 1275 1276 sdc2_off: sdc2-off { 1277 clk { 1278 pins = "sdc2_clk"; 1279 bias-disable; 1280 drive-strength = <2>; 1281 }; 1282 1283 cmd { 1284 pins = "sdc2_cmd"; 1285 bias-pull-up; 1286 drive-strength = <2>; 1287 }; 1288 1289 data { 1290 pins = "sdc2_data"; 1291 bias-pull-up; 1292 drive-strength = <2>; 1293 }; 1294 1295 cd { 1296 pins = "gpio54"; 1297 bias-disable; 1298 drive-strength = <2>; 1299 }; 1300 }; 1301 1302 blsp1_uart2_default: blsp1-uart2-default { 1303 rx { 1304 pins = "gpio5"; 1305 function = "blsp_uart2"; 1306 drive-strength = <2>; 1307 bias-pull-up; 1308 }; 1309 1310 tx { 1311 pins = "gpio4"; 1312 function = "blsp_uart2"; 1313 drive-strength = <4>; 1314 bias-disable; 1315 }; 1316 }; 1317 1318 blsp2_uart1_default: blsp2-uart1-default { 1319 tx-rts { 1320 pins = "gpio41", "gpio44"; 1321 function = "blsp_uart7"; 1322 drive-strength = <2>; 1323 bias-disable; 1324 }; 1325 1326 rx-cts { 1327 pins = "gpio42", "gpio43"; 1328 function = "blsp_uart7"; 1329 drive-strength = <2>; 1330 bias-pull-up; 1331 }; 1332 }; 1333 1334 blsp2_uart1_sleep: blsp2-uart1-sleep { 1335 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1336 function = "gpio"; 1337 drive-strength = <2>; 1338 bias-pull-down; 1339 }; 1340 1341 blsp2_uart4_default: blsp2-uart4-default { 1342 tx-rts { 1343 pins = "gpio53", "gpio56"; 1344 function = "blsp_uart10"; 1345 drive-strength = <2>; 1346 bias-disable; 1347 }; 1348 1349 rx-cts { 1350 pins = "gpio54", "gpio55"; 1351 function = "blsp_uart10"; 1352 drive-strength = <2>; 1353 bias-pull-up; 1354 }; 1355 }; 1356 1357 blsp1_i2c1_default: blsp1-i2c1-default { 1358 pins = "gpio2", "gpio3"; 1359 function = "blsp_i2c1"; 1360 drive-strength = <2>; 1361 bias-disable; 1362 }; 1363 1364 blsp1_i2c1_sleep: blsp1-i2c1-sleep { 1365 pins = "gpio2", "gpio3"; 1366 function = "blsp_i2c1"; 1367 drive-strength = <2>; 1368 bias-pull-up; 1369 }; 1370 1371 blsp1_i2c2_default: blsp1-i2c2-default { 1372 pins = "gpio6", "gpio7"; 1373 function = "blsp_i2c2"; 1374 drive-strength = <2>; 1375 bias-disable; 1376 }; 1377 1378 blsp1_i2c2_sleep: blsp1-i2c2-sleep { 1379 pins = "gpio6", "gpio7"; 1380 function = "blsp_i2c2"; 1381 drive-strength = <2>; 1382 bias-pull-up; 1383 }; 1384 1385 blsp1_i2c3_default: blsp1-i2c3-default { 1386 pins = "gpio10", "gpio11"; 1387 function = "blsp_i2c3"; 1388 drive-strength = <2>; 1389 bias-disable; 1390 }; 1391 1392 blsp1_i2c3_sleep: blsp1-i2c3-sleep { 1393 pins = "gpio10", "gpio11"; 1394 function = "blsp_i2c3"; 1395 drive-strength = <2>; 1396 bias-pull-up; 1397 }; 1398 1399 /* BLSP1_I2C4 info is missing */ 1400 1401 /* BLSP1_I2C5 info is missing */ 1402 1403 blsp1_i2c6_default: blsp1-i2c6-default { 1404 pins = "gpio29", "gpio30"; 1405 function = "blsp_i2c6"; 1406 drive-strength = <2>; 1407 bias-disable; 1408 }; 1409 1410 blsp1_i2c6_sleep: blsp1-i2c6-sleep { 1411 pins = "gpio29", "gpio30"; 1412 function = "blsp_i2c6"; 1413 drive-strength = <2>; 1414 bias-pull-up; 1415 }; 1416 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1417 1418 /* BLSP2_I2C1 info is missing */ 1419 1420 blsp2_i2c2_default: blsp2-i2c2-default { 1421 pins = "gpio47", "gpio48"; 1422 function = "blsp_i2c8"; 1423 drive-strength = <2>; 1424 bias-disable; 1425 }; 1426 1427 blsp2_i2c2_sleep: blsp2-i2c2-sleep { 1428 pins = "gpio47", "gpio48"; 1429 function = "blsp_i2c8"; 1430 drive-strength = <2>; 1431 bias-pull-up; 1432 }; 1433 1434 /* BLSP2_I2C3 info is missing */ 1435 1436 /* BLSP2_I2C4 info is missing */ 1437 1438 blsp2_i2c5_default: blsp2-i2c5-default { 1439 pins = "gpio83", "gpio84"; 1440 function = "blsp_i2c11"; 1441 drive-strength = <2>; 1442 bias-disable; 1443 }; 1444 1445 blsp2_i2c5_sleep: blsp2-i2c5-sleep { 1446 pins = "gpio83", "gpio84"; 1447 function = "blsp_i2c11"; 1448 drive-strength = <2>; 1449 bias-pull-up; 1450 }; 1451 1452 blsp2_i2c6_default: blsp2-i2c6-default { 1453 pins = "gpio87", "gpio88"; 1454 function = "blsp_i2c12"; 1455 drive-strength = <2>; 1456 bias-disable; 1457 }; 1458 1459 blsp2_i2c6_sleep: blsp2-i2c6-sleep { 1460 pins = "gpio87", "gpio88"; 1461 function = "blsp_i2c12"; 1462 drive-strength = <2>; 1463 bias-pull-up; 1464 }; 1465 1466 spi8_default: spi8_default { 1467 mosi { 1468 pins = "gpio45"; 1469 function = "blsp_spi8"; 1470 }; 1471 miso { 1472 pins = "gpio46"; 1473 function = "blsp_spi8"; 1474 }; 1475 cs { 1476 pins = "gpio47"; 1477 function = "blsp_spi8"; 1478 }; 1479 clk { 1480 pins = "gpio48"; 1481 function = "blsp_spi8"; 1482 }; 1483 }; 1484 }; 1485 1486 mmcc: clock-controller@fd8c0000 { 1487 compatible = "qcom,mmcc-msm8974"; 1488 #clock-cells = <1>; 1489 #reset-cells = <1>; 1490 #power-domain-cells = <1>; 1491 reg = <0xfd8c0000 0x6000>; 1492 }; 1493 1494 mdss: mdss@fd900000 { 1495 compatible = "qcom,mdss"; 1496 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 1497 reg-names = "mdss_phys", "vbif_phys"; 1498 1499 power-domains = <&mmcc MDSS_GDSC>; 1500 1501 clocks = <&mmcc MDSS_AHB_CLK>, 1502 <&mmcc MDSS_AXI_CLK>, 1503 <&mmcc MDSS_VSYNC_CLK>; 1504 clock-names = "iface", "bus", "vsync"; 1505 1506 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1507 1508 interrupt-controller; 1509 #interrupt-cells = <1>; 1510 1511 status = "disabled"; 1512 1513 #address-cells = <1>; 1514 #size-cells = <1>; 1515 ranges; 1516 1517 mdp: mdp@fd900000 { 1518 compatible = "qcom,mdp5"; 1519 reg = <0xfd900100 0x22000>; 1520 reg-names = "mdp_phys"; 1521 1522 interrupt-parent = <&mdss>; 1523 interrupts = <0>; 1524 1525 clocks = <&mmcc MDSS_AHB_CLK>, 1526 <&mmcc MDSS_AXI_CLK>, 1527 <&mmcc MDSS_MDP_CLK>, 1528 <&mmcc MDSS_VSYNC_CLK>; 1529 clock-names = "iface", "bus", "core", "vsync"; 1530 1531 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>; 1532 interconnect-names = "mdp0-mem"; 1533 1534 ports { 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 1538 port@0 { 1539 reg = <0>; 1540 mdp5_intf1_out: endpoint { 1541 remote-endpoint = <&dsi0_in>; 1542 }; 1543 }; 1544 }; 1545 }; 1546 1547 dsi0: dsi@fd922800 { 1548 compatible = "qcom,mdss-dsi-ctrl"; 1549 reg = <0xfd922800 0x1f8>; 1550 reg-names = "dsi_ctrl"; 1551 1552 interrupt-parent = <&mdss>; 1553 interrupts = <4>; 1554 1555 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1556 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1557 1558 clocks = <&mmcc MDSS_MDP_CLK>, 1559 <&mmcc MDSS_AHB_CLK>, 1560 <&mmcc MDSS_AXI_CLK>, 1561 <&mmcc MDSS_BYTE0_CLK>, 1562 <&mmcc MDSS_PCLK0_CLK>, 1563 <&mmcc MDSS_ESC0_CLK>, 1564 <&mmcc MMSS_MISC_AHB_CLK>; 1565 clock-names = "mdp_core", 1566 "iface", 1567 "bus", 1568 "byte", 1569 "pixel", 1570 "core", 1571 "core_mmss"; 1572 1573 phys = <&dsi0_phy>; 1574 phy-names = "dsi-phy"; 1575 1576 status = "disabled"; 1577 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 1581 ports { 1582 #address-cells = <1>; 1583 #size-cells = <0>; 1584 1585 port@0 { 1586 reg = <0>; 1587 dsi0_in: endpoint { 1588 remote-endpoint = <&mdp5_intf1_out>; 1589 }; 1590 }; 1591 1592 port@1 { 1593 reg = <1>; 1594 dsi0_out: endpoint { 1595 }; 1596 }; 1597 }; 1598 }; 1599 1600 dsi0_phy: dsi-phy@fd922a00 { 1601 compatible = "qcom,dsi-phy-28nm-hpm"; 1602 reg = <0xfd922a00 0xd4>, 1603 <0xfd922b00 0x280>, 1604 <0xfd922d80 0x30>; 1605 reg-names = "dsi_pll", 1606 "dsi_phy", 1607 "dsi_phy_regulator"; 1608 1609 #clock-cells = <1>; 1610 #phy-cells = <0>; 1611 1612 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1613 clock-names = "iface", "ref"; 1614 1615 status = "disabled"; 1616 }; 1617 }; 1618 1619 gpu: adreno@fdb00000 { 1620 compatible = "qcom,adreno-330.1", "qcom,adreno"; 1621 reg = <0xfdb00000 0x10000>; 1622 reg-names = "kgsl_3d0_reg_memory"; 1623 1624 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1625 interrupt-names = "kgsl_3d0_irq"; 1626 1627 clocks = <&mmcc OXILI_GFX3D_CLK>, 1628 <&mmcc OXILICX_AHB_CLK>, 1629 <&mmcc OXILICX_AXI_CLK>; 1630 clock-names = "core", "iface", "mem_iface"; 1631 1632 sram = <&gmu_sram>; 1633 power-domains = <&mmcc OXILICX_GDSC>; 1634 operating-points-v2 = <&gpu_opp_table>; 1635 1636 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>, 1637 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>; 1638 interconnect-names = "gfx-mem", "ocmem"; 1639 1640 // iommus = <&gpu_iommu 0>; 1641 1642 status = "disabled"; 1643 1644 gpu_opp_table: opp-table { 1645 compatible = "operating-points-v2"; 1646 1647 opp-320000000 { 1648 opp-hz = /bits/ 64 <320000000>; 1649 }; 1650 1651 opp-200000000 { 1652 opp-hz = /bits/ 64 <200000000>; 1653 }; 1654 1655 opp-27000000 { 1656 opp-hz = /bits/ 64 <27000000>; 1657 }; 1658 }; 1659 }; 1660 1661 sram@fdd00000 { 1662 compatible = "qcom,msm8974-ocmem"; 1663 reg = <0xfdd00000 0x2000>, 1664 <0xfec00000 0x180000>; 1665 reg-names = "ctrl", "mem"; 1666 ranges = <0 0xfec00000 0x180000>; 1667 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1668 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 1669 clock-names = "core", "iface"; 1670 1671 #address-cells = <1>; 1672 #size-cells = <1>; 1673 1674 gmu_sram: gmu-sram@0 { 1675 reg = <0x0 0x100000>; 1676 }; 1677 }; 1678 1679 remoteproc_adsp: remoteproc@fe200000 { 1680 compatible = "qcom,msm8974-adsp-pil"; 1681 reg = <0xfe200000 0x100>; 1682 1683 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 1684 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1685 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1686 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1687 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1688 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1689 1690 clocks = <&xo_board>; 1691 clock-names = "xo"; 1692 1693 memory-region = <&adsp_region>; 1694 1695 qcom,smem-states = <&adsp_smp2p_out 0>; 1696 qcom,smem-state-names = "stop"; 1697 1698 status = "disabled"; 1699 1700 smd-edge { 1701 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 1702 1703 qcom,ipc = <&apcs 8 8>; 1704 qcom,smd-edge = <1>; 1705 label = "lpass"; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 }; 1709 }; 1710 1711 imem: sram@fe805000 { 1712 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; 1713 reg = <0xfe805000 0x1000>; 1714 1715 reboot-mode { 1716 compatible = "syscon-reboot-mode"; 1717 offset = <0x65c>; 1718 }; 1719 }; 1720 }; 1721 1722 tcsr_mutex: tcsr-mutex { 1723 compatible = "qcom,tcsr-mutex"; 1724 syscon = <&tcsr_mutex_block 0 0x80>; 1725 1726 #hwlock-cells = <1>; 1727 }; 1728 1729 thermal-zones { 1730 cpu0-thermal { 1731 polling-delay-passive = <250>; 1732 polling-delay = <1000>; 1733 1734 thermal-sensors = <&tsens 5>; 1735 1736 trips { 1737 cpu_alert0: trip0 { 1738 temperature = <75000>; 1739 hysteresis = <2000>; 1740 type = "passive"; 1741 }; 1742 cpu_crit0: trip1 { 1743 temperature = <110000>; 1744 hysteresis = <2000>; 1745 type = "critical"; 1746 }; 1747 }; 1748 }; 1749 1750 cpu1-thermal { 1751 polling-delay-passive = <250>; 1752 polling-delay = <1000>; 1753 1754 thermal-sensors = <&tsens 6>; 1755 1756 trips { 1757 cpu_alert1: trip0 { 1758 temperature = <75000>; 1759 hysteresis = <2000>; 1760 type = "passive"; 1761 }; 1762 cpu_crit1: trip1 { 1763 temperature = <110000>; 1764 hysteresis = <2000>; 1765 type = "critical"; 1766 }; 1767 }; 1768 }; 1769 1770 cpu2-thermal { 1771 polling-delay-passive = <250>; 1772 polling-delay = <1000>; 1773 1774 thermal-sensors = <&tsens 7>; 1775 1776 trips { 1777 cpu_alert2: trip0 { 1778 temperature = <75000>; 1779 hysteresis = <2000>; 1780 type = "passive"; 1781 }; 1782 cpu_crit2: trip1 { 1783 temperature = <110000>; 1784 hysteresis = <2000>; 1785 type = "critical"; 1786 }; 1787 }; 1788 }; 1789 1790 cpu3-thermal { 1791 polling-delay-passive = <250>; 1792 polling-delay = <1000>; 1793 1794 thermal-sensors = <&tsens 8>; 1795 1796 trips { 1797 cpu_alert3: trip0 { 1798 temperature = <75000>; 1799 hysteresis = <2000>; 1800 type = "passive"; 1801 }; 1802 cpu_crit3: trip1 { 1803 temperature = <110000>; 1804 hysteresis = <2000>; 1805 type = "critical"; 1806 }; 1807 }; 1808 }; 1809 1810 q6-dsp-thermal { 1811 polling-delay-passive = <250>; 1812 polling-delay = <1000>; 1813 1814 thermal-sensors = <&tsens 1>; 1815 1816 trips { 1817 q6_dsp_alert0: trip-point0 { 1818 temperature = <90000>; 1819 hysteresis = <2000>; 1820 type = "hot"; 1821 }; 1822 }; 1823 }; 1824 1825 modemtx-thermal { 1826 polling-delay-passive = <250>; 1827 polling-delay = <1000>; 1828 1829 thermal-sensors = <&tsens 2>; 1830 1831 trips { 1832 modemtx_alert0: trip-point0 { 1833 temperature = <90000>; 1834 hysteresis = <2000>; 1835 type = "hot"; 1836 }; 1837 }; 1838 }; 1839 1840 video-thermal { 1841 polling-delay-passive = <250>; 1842 polling-delay = <1000>; 1843 1844 thermal-sensors = <&tsens 3>; 1845 1846 trips { 1847 video_alert0: trip-point0 { 1848 temperature = <95000>; 1849 hysteresis = <2000>; 1850 type = "hot"; 1851 }; 1852 }; 1853 }; 1854 1855 wlan-thermal { 1856 polling-delay-passive = <250>; 1857 polling-delay = <1000>; 1858 1859 thermal-sensors = <&tsens 4>; 1860 1861 trips { 1862 wlan_alert0: trip-point0 { 1863 temperature = <105000>; 1864 hysteresis = <2000>; 1865 type = "hot"; 1866 }; 1867 }; 1868 }; 1869 1870 gpu-top-thermal { 1871 polling-delay-passive = <250>; 1872 polling-delay = <1000>; 1873 1874 thermal-sensors = <&tsens 9>; 1875 1876 trips { 1877 gpu1_alert0: trip-point0 { 1878 temperature = <90000>; 1879 hysteresis = <2000>; 1880 type = "hot"; 1881 }; 1882 }; 1883 }; 1884 1885 gpu-bottom-thermal { 1886 polling-delay-passive = <250>; 1887 polling-delay = <1000>; 1888 1889 thermal-sensors = <&tsens 10>; 1890 1891 trips { 1892 gpu2_alert0: trip-point0 { 1893 temperature = <90000>; 1894 hysteresis = <2000>; 1895 type = "hot"; 1896 }; 1897 }; 1898 }; 1899 }; 1900 1901 timer { 1902 compatible = "arm,armv7-timer"; 1903 interrupts = <GIC_PPI 2 0xf08>, 1904 <GIC_PPI 3 0xf08>, 1905 <GIC_PPI 4 0xf08>, 1906 <GIC_PPI 1 0xf08>; 1907 clock-frequency = <19200000>; 1908 }; 1909 1910 vreg_boost: vreg-boost { 1911 compatible = "regulator-fixed"; 1912 1913 regulator-name = "vreg-boost"; 1914 regulator-min-microvolt = <3150000>; 1915 regulator-max-microvolt = <3150000>; 1916 1917 regulator-always-on; 1918 regulator-boot-on; 1919 1920 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; 1921 enable-active-high; 1922 1923 pinctrl-names = "default"; 1924 pinctrl-0 = <&boost_bypass_n_pin>; 1925 }; 1926 1927 vreg_vph_pwr: vreg-vph-pwr { 1928 compatible = "regulator-fixed"; 1929 regulator-name = "vph-pwr"; 1930 1931 regulator-min-microvolt = <3600000>; 1932 regulator-max-microvolt = <3600000>; 1933 1934 regulator-always-on; 1935 }; 1936}; 1937