1 /*
2 * arch/ppc/kernel/ppc4xx_sgdma.c
3 *
4 * IBM PPC4xx DMA engine scatter/gather library
5 *
6 * Copyright 2002-2003 MontaVista Software Inc.
7 *
8 * Cleaned by Matt Porter <mporter@mvista.com>
9 *
10 * Original code by Armin Kuster <akuster@mvista.com>
11 * and Pete Popov <ppopov@mvista.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <linux/config.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/init.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29
30 #include <asm/system.h>
31 #include <asm/io.h>
32 #include <asm/ppc4xx_dma.h>
33
34 static __inline__ void
ppc4xx_set_sg_addr(int dmanr,phys_addr_t sg_addr)35 ppc4xx_set_sg_addr(int dmanr, phys_addr_t sg_addr)
36 {
37 switch (dmanr) {
38 case 0:
39 #ifdef PPC4xx_DMA_64BIT
40 mtdcr(DCRN_ASGH0, (u32)(sg_addr >> 32));
41 #endif
42 mtdcr(DCRN_ASG0, (u32)sg_addr);
43 break;
44 case 1:
45 #ifdef PPC4xx_DMA_64BIT
46 mtdcr(DCRN_ASGH1, (u32)(sg_addr >> 32));
47 #endif
48 mtdcr(DCRN_ASG1, (u32)sg_addr);
49 break;
50 case 2:
51 #ifdef PPC4xx_DMA_64BIT
52 mtdcr(DCRN_ASGH2, (u32)(sg_addr >> 32));
53 #endif
54 mtdcr(DCRN_ASG2, sg_addr);
55 break;
56 case 3:
57 #ifdef PPC4xx_DMA_64BIT
58 mtdcr(DCRN_ASGH3, (u32)(sg_addr >> 32));
59 #endif
60 mtdcr(DCRN_ASG3, (u32)sg_addr);
61 break;
62 }
63 }
64
65
66 /*
67 * Add a new sgl descriptor to the end of a scatter/gather list
68 * which was created by alloc_dma_handle().
69 *
70 * For a memory to memory transfer, both dma addresses must be
71 * valid. For a peripheral to memory transfer, one of the addresses
72 * must be set to NULL, depending on the direction of the transfer:
73 * memory to peripheral: set dst_addr to NULL,
74 * peripheral to memory: set src_addr to NULL.
75 */
76 static __inline__ int
ppc4xx_add_dma_sgl(sgl_handle_t handle,phys_addr_t src_addr,phys_addr_t dst_addr,unsigned int count)77 ppc4xx_add_dma_sgl(sgl_handle_t handle, phys_addr_t src_addr, phys_addr_t dst_addr,
78 unsigned int count)
79 {
80 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
81 ppc_dma_ch_t *p_dma_ch;
82
83 if (!handle) {
84 printk("ppc4xx_add_dma_sgl: null handle\n");
85 return DMA_STATUS_BAD_HANDLE;
86 }
87
88 if (psgl->dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
89 printk("ppc4xx_add_dma_sgl: bad channel: %d\n", psgl->dmanr);
90 return DMA_STATUS_BAD_CHANNEL;
91 }
92
93 p_dma_ch = &dma_channels[psgl->dmanr];
94
95 #ifdef DEBUG_4xxDMA
96 {
97 int error = 0;
98 unsigned int aligned =
99 (unsigned) src_addr | (unsigned) dst_addr | count;
100 switch (p_dma_ch->pwidth) {
101 case PW_8:
102 break;
103 case PW_16:
104 if (aligned & 0x1)
105 error = 1;
106 break;
107 case PW_32:
108 if (aligned & 0x3)
109 error = 1;
110 break;
111 case PW_64:
112 if (aligned & 0x7)
113 error = 1;
114 break;
115 default:
116 printk("ppc4xx_add_dma_sgl: invalid bus width: 0x%x\n",
117 p_dma_ch->pwidth);
118 return DMA_STATUS_GENERAL_ERROR;
119 }
120 if (error)
121 printk
122 ("Alignment warning: ppc4xx_add_dma_sgl src 0x%x dst 0x%x count 0x%x bus width var %d\n",
123 src_addr, dst_addr, count, p_dma_ch->pwidth);
124
125 }
126 #endif
127
128 if ((unsigned) (psgl->ptail + 1) >= ((unsigned) psgl + SGL_LIST_SIZE)) {
129 printk("sgl handle out of memory \n");
130 return DMA_STATUS_OUT_OF_MEMORY;
131 }
132
133 if (!psgl->ptail) {
134 psgl->phead = (ppc_sgl_t *)
135 ((unsigned) psgl + sizeof (sgl_list_info_t));
136 psgl->ptail = psgl->phead;
137 } else {
138 psgl->ptail->next = iopa((unsigned long)(psgl->ptail + 1));
139 psgl->ptail++;
140 }
141
142 psgl->ptail->control = psgl->control;
143 psgl->ptail->src_addr = src_addr;
144 psgl->ptail->dst_addr = dst_addr;
145 psgl->ptail->control_count = (count >> p_dma_ch->shift) |
146 psgl->sgl_control;
147 psgl->ptail->next = (uint32_t) NULL;
148
149 return DMA_STATUS_GOOD;
150 }
151
152 /*
153 * Enable (start) the DMA described by the sgl handle.
154 */
155 static __inline__ void
ppc4xx_enable_dma_sgl(sgl_handle_t handle)156 ppc4xx_enable_dma_sgl(sgl_handle_t handle)
157 {
158 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
159 ppc_dma_ch_t *p_dma_ch;
160 uint32_t sg_command;
161
162 if (!handle) {
163 printk("ppc4xx_enable_dma_sgl: null handle\n");
164 return;
165 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
166 printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n",
167 psgl->dmanr);
168 return;
169 } else if (!psgl->phead) {
170 printk("ppc4xx_enable_dma_sgl: sg list empty\n");
171 return;
172 }
173
174 p_dma_ch = &dma_channels[psgl->dmanr];
175 psgl->ptail->control_count &= ~SG_LINK; /* make this the last dscrptr */
176 sg_command = mfdcr(DCRN_ASGC);
177
178 ppc4xx_set_sg_addr(psgl->dmanr, iopa((unsigned long)psgl->phead));
179
180 switch (psgl->dmanr) {
181 case 0:
182 sg_command |= SSG0_ENABLE;
183 break;
184 case 1:
185 sg_command |= SSG1_ENABLE;
186 break;
187 case 2:
188 sg_command |= SSG2_ENABLE;
189 break;
190 case 3:
191 sg_command |= SSG3_ENABLE;
192 break;
193 default:
194 printk("ppc4xx_enable_dma_sgl: bad channel: %d\n", psgl->dmanr);
195 }
196
197 mtdcr(DCRN_ASGC, sg_command); /* start transfer */
198 }
199
200 /*
201 * Halt an active scatter/gather DMA operation.
202 */
203 static __inline__ void
ppc4xx_disable_dma_sgl(sgl_handle_t handle)204 ppc4xx_disable_dma_sgl(sgl_handle_t handle)
205 {
206 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
207 uint32_t sg_command;
208
209 if (!handle) {
210 printk("ppc4xx_enable_dma_sgl: null handle\n");
211 return;
212 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
213 printk("ppc4xx_enable_dma_sgl: bad channel in handle %d\n",
214 psgl->dmanr);
215 return;
216 }
217
218 sg_command = mfdcr(DCRN_ASGC);
219 switch (psgl->dmanr) {
220 case 0:
221 sg_command &= ~SSG0_ENABLE;
222 break;
223 case 1:
224 sg_command &= ~SSG1_ENABLE;
225 break;
226 case 2:
227 sg_command &= ~SSG2_ENABLE;
228 break;
229 case 3:
230 sg_command &= ~SSG3_ENABLE;
231 break;
232 default:
233 printk("ppc4xx_enable_dma_sgl: bad channel: %d\n", psgl->dmanr);
234 }
235
236 mtdcr(DCRN_ASGC, sg_command); /* stop transfer */
237 }
238
239 /*
240 * Returns number of bytes left to be transferred from the entire sgl list.
241 * *src_addr and *dst_addr get set to the source/destination address of
242 * the sgl descriptor where the DMA stopped.
243 *
244 * An sgl transfer must NOT be active when this function is called.
245 */
246 static __inline__ int
ppc4xx_get_dma_sgl_residue(sgl_handle_t handle,phys_addr_t * src_addr,phys_addr_t * dst_addr)247 ppc4xx_get_dma_sgl_residue(sgl_handle_t handle, phys_addr_t * src_addr,
248 phys_addr_t * dst_addr)
249 {
250 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
251 ppc_dma_ch_t *p_dma_ch;
252 ppc_sgl_t *pnext, *sgl_addr;
253 uint32_t count_left;
254
255 if (!handle) {
256 printk("ppc4xx_get_dma_sgl_residue: null handle\n");
257 return DMA_STATUS_BAD_HANDLE;
258 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
259 printk("ppc4xx_get_dma_sgl_residue: bad channel in handle %d\n",
260 psgl->dmanr);
261 return DMA_STATUS_BAD_CHANNEL;
262 }
263
264 switch (psgl->dmanr) {
265 case 0:
266 sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG0));
267 count_left = mfdcr(DCRN_DMACT0);
268 break;
269 case 1:
270 sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG1));
271 count_left = mfdcr(DCRN_DMACT1);
272 break;
273 case 2:
274 sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG2));
275 count_left = mfdcr(DCRN_DMACT2);
276 break;
277 case 3:
278 sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG3));
279 count_left = mfdcr(DCRN_DMACT3);
280 break;
281 default:
282 printk("ppc4xx_get_dma_sgl_residue: bad channel %d\n", psgl->dmanr);
283 goto error;
284 }
285
286 if (!sgl_addr) {
287 printk("ppc4xx_get_dma_sgl_residue: sgl addr register is null\n");
288 goto error;
289 }
290
291 pnext = psgl->phead;
292 while (pnext &&
293 ((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE) &&
294 (pnext != sgl_addr))
295 ) {
296 pnext++;
297 }
298
299 if (pnext == sgl_addr) { /* found the sgl descriptor */
300
301 *src_addr = pnext->src_addr;
302 *dst_addr = pnext->dst_addr;
303
304 /*
305 * Now search the remaining descriptors and add their count.
306 * We already have the remaining count from this descriptor in
307 * count_left.
308 */
309 pnext++;
310
311 while ((pnext != psgl->ptail) &&
312 ((unsigned) pnext < ((unsigned) psgl + SGL_LIST_SIZE))
313 ) {
314 count_left += pnext->control_count & SG_COUNT_MASK;
315 }
316
317 if (pnext != psgl->ptail) { /* should never happen */
318 printk
319 ("ppc4xx_get_dma_sgl_residue error (1) psgl->ptail 0x%x handle 0x%x\n",
320 (unsigned int) psgl->ptail, (unsigned int) handle);
321 goto error;
322 }
323
324 /* success */
325 p_dma_ch = &dma_channels[psgl->dmanr];
326 return (count_left << p_dma_ch->shift); /* count in bytes */
327
328 } else {
329 /* this shouldn't happen */
330 printk
331 ("get_dma_sgl_residue, unable to match current address 0x%x, handle 0x%x\n",
332 (unsigned int) sgl_addr, (unsigned int) handle);
333
334 }
335
336 error:
337 *src_addr = (phys_addr_t) NULL;
338 *dst_addr = (phys_addr_t) NULL;
339 return 0;
340 }
341
342 /*
343 * Returns the address(es) of the buffer(s) contained in the head element of
344 * the scatter/gather list. The element is removed from the scatter/gather
345 * list and the next element becomes the head.
346 *
347 * This function should only be called when the DMA is not active.
348 */
349 static __inline__ int
ppc4xx_delete_dma_sgl_element(sgl_handle_t handle,phys_addr_t * src_dma_addr,phys_addr_t * dst_dma_addr)350 ppc4xx_delete_dma_sgl_element(sgl_handle_t handle, phys_addr_t * src_dma_addr,
351 phys_addr_t * dst_dma_addr)
352 {
353 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
354
355 if (!handle) {
356 printk("ppc4xx_delete_sgl_element: null handle\n");
357 return DMA_STATUS_BAD_HANDLE;
358 } else if (psgl->dmanr > (MAX_PPC4xx_DMA_CHANNELS - 1)) {
359 printk("ppc4xx_delete_sgl_element: bad channel in handle %d\n",
360 psgl->dmanr);
361 return DMA_STATUS_BAD_CHANNEL;
362 }
363
364 if (!psgl->phead) {
365 printk("ppc4xx_delete_sgl_element: sgl list empty\n");
366 *src_dma_addr = (phys_addr_t) NULL;
367 *dst_dma_addr = (phys_addr_t) NULL;
368 return DMA_STATUS_SGL_LIST_EMPTY;
369 }
370
371 *src_dma_addr = (phys_addr_t) psgl->phead->src_addr;
372 *dst_dma_addr = (phys_addr_t) psgl->phead->dst_addr;
373
374 if (psgl->phead == psgl->ptail) {
375 /* last descriptor on the list */
376 psgl->phead = NULL;
377 psgl->ptail = NULL;
378 } else {
379 psgl->phead++;
380 }
381
382 return DMA_STATUS_GOOD;
383 }
384
385
386 /*
387 * Create a scatter/gather list handle. This is simply a structure which
388 * describes a scatter/gather list.
389 *
390 * A handle is returned in "handle" which the driver should save in order to
391 * be able to access this list later. A chunk of memory will be allocated
392 * to be used by the API for internal management purposes, including managing
393 * the sg list and allocating memory for the sgl descriptors. One page should
394 * be more than enough for that purpose. Perhaps it's a bit wasteful to use
395 * a whole page for a single sg list, but most likely there will be only one
396 * sg list per channel.
397 *
398 * Interrupt notes:
399 * Each sgl descriptor has a copy of the DMA control word which the DMA engine
400 * loads in the control register. The control word has a "global" interrupt
401 * enable bit for that channel. Interrupts are further qualified by a few bits
402 * in the sgl descriptor count register. In order to setup an sgl, we have to
403 * know ahead of time whether or not interrupts will be enabled at the completion
404 * of the transfers. Thus, enable_dma_interrupt()/disable_dma_interrupt() MUST
405 * be called before calling alloc_dma_handle(). If the interrupt mode will never
406 * change after powerup, then enable_dma_interrupt()/disable_dma_interrupt()
407 * do not have to be called -- interrupts will be enabled or disabled based
408 * on how the channel was configured after powerup by the hw_init_dma_channel()
409 * function. Each sgl descriptor will be setup to interrupt if an error occurs;
410 * however, only the last descriptor will be setup to interrupt. Thus, an
411 * interrupt will occur (if interrupts are enabled) only after the complete
412 * sgl transfer is done.
413 */
414 int
ppc4xx_alloc_dma_handle(sgl_handle_t * phandle,unsigned int mode,unsigned int dmanr)415 ppc4xx_alloc_dma_handle(sgl_handle_t * phandle, unsigned int mode, unsigned int dmanr)
416 {
417 sgl_list_info_t *psgl;
418 dma_addr_t dma_addr;
419 ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
420 uint32_t sg_command;
421 void *ret;
422
423 if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
424 printk("ppc4xx_alloc_dma_handle: invalid channel 0x%x\n", dmanr);
425 return DMA_STATUS_BAD_CHANNEL;
426 }
427
428 if (!phandle) {
429 printk("ppc4xx_alloc_dma_handle: null handle pointer\n");
430 return DMA_STATUS_NULL_POINTER;
431 }
432
433 /* Get a page of memory, which is zeroed out by consistent_alloc() */
434 ret = consistent_alloc(GFP_KERNEL, DMA_PPC4xx_SIZE, &dma_addr);
435 if (ret != NULL) {
436 memset(ret, 0, DMA_PPC4xx_SIZE);
437 psgl = (sgl_list_info_t *) ret;
438 }
439
440 if (psgl == NULL) {
441 *phandle = (sgl_handle_t) NULL;
442 return DMA_STATUS_OUT_OF_MEMORY;
443 }
444
445 psgl->dma_addr = dma_addr;
446 psgl->dmanr = dmanr;
447
448 /*
449 * Modify and save the control word. These words will be
450 * written to each sgl descriptor. The DMA engine then
451 * loads this control word into the control register
452 * every time it reads a new descriptor.
453 */
454 psgl->control = p_dma_ch->control;
455 /* Clear all mode bits */
456 psgl->control &= ~(DMA_TM_MASK | DMA_TD);
457 /* Save control word and mode */
458 psgl->control |= (mode | DMA_CE_ENABLE);
459
460 /* In MM mode, we must set ETD/TCE */
461 if (mode == DMA_MODE_MM)
462 psgl->control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
463
464 if (p_dma_ch->int_enable) {
465 /* Enable channel interrupt */
466 psgl->control |= DMA_CIE_ENABLE;
467 } else {
468 psgl->control &= ~DMA_CIE_ENABLE;
469 }
470
471 sg_command = mfdcr(DCRN_ASGC);
472 switch (dmanr) {
473 case 0:
474 sg_command |= SSG0_MASK_ENABLE;
475 break;
476 case 1:
477 sg_command |= SSG1_MASK_ENABLE;
478 break;
479 case 2:
480 sg_command |= SSG2_MASK_ENABLE;
481 break;
482 case 3:
483 sg_command |= SSG3_MASK_ENABLE;
484 break;
485 default:
486 printk("ppc4xx_alloc_dma_handle: bad channel: %d\n", dmanr);
487 ppc4xx_free_dma_handle((sgl_handle_t) psgl);
488 *phandle = (sgl_handle_t) NULL;
489 return DMA_STATUS_BAD_CHANNEL;
490 }
491
492 /* Enable SGL control access */
493 mtdcr(DCRN_ASGC, sg_command);
494 psgl->sgl_control = SG_ERI_ENABLE | SG_LINK;
495
496 if (p_dma_ch->int_enable) {
497 if (p_dma_ch->tce_enable)
498 psgl->sgl_control |= SG_TCI_ENABLE;
499 else
500 psgl->sgl_control |= SG_ETI_ENABLE;
501 }
502
503 *phandle = (sgl_handle_t) psgl;
504 return DMA_STATUS_GOOD;
505 }
506
507 /*
508 * Destroy a scatter/gather list handle that was created by alloc_dma_handle().
509 * The list must be empty (contain no elements).
510 */
511 void
ppc4xx_free_dma_handle(sgl_handle_t handle)512 ppc4xx_free_dma_handle(sgl_handle_t handle)
513 {
514 sgl_list_info_t *psgl = (sgl_list_info_t *) handle;
515
516 if (!handle) {
517 printk("ppc4xx_free_dma_handle: got NULL\n");
518 return;
519 } else if (psgl->phead) {
520 printk("ppc4xx_free_dma_handle: list not empty\n");
521 return;
522 } else if (!psgl->dma_addr) { /* should never happen */
523 printk("ppc4xx_free_dma_handle: no dma address\n");
524 return;
525 }
526
527 consistent_free((void *) psgl);
528 }
529
530 EXPORT_SYMBOL(ppc4xx_alloc_dma_handle);
531 EXPORT_SYMBOL(ppc4xx_free_dma_handle);
532 EXPORT_SYMBOL(ppc4xx_add_dma_sgl);
533 EXPORT_SYMBOL(ppc4xx_delete_dma_sgl_element);
534 EXPORT_SYMBOL(ppc4xx_enable_dma_sgl);
535 EXPORT_SYMBOL(ppc4xx_disable_dma_sgl);
536 EXPORT_SYMBOL(ppc4xx_get_dma_sgl_residue);
537