1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/mach-at91/pm_slow_clock.S
4 *
5 *  Copyright (C) 2006 Savin Zlobec
6 *
7 * AT91SAM9 support:
8 *  Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee>
9 */
10#include <linux/linkage.h>
11#include <linux/clk/at91_pmc.h>
12#include "pm.h"
13#include "pm_data-offsets.h"
14
15#define	SRAMC_SELF_FRESH_ACTIVE		0x01
16#define	SRAMC_SELF_FRESH_EXIT		0x00
17
18pmc	.req	r0
19tmp1	.req	r4
20tmp2	.req	r5
21tmp3	.req	r6
22
23/*
24 * Wait until master clock is ready (after switching master clock source)
25 *
26 * @r_mckid:	register holding master clock identifier
27 *
28 * Side effects: overwrites r7, r8
29 */
30	.macro wait_mckrdy r_mckid
31#ifdef CONFIG_SOC_SAMA7
32	cmp	\r_mckid, #0
33	beq	1f
34	mov	r7, #AT91_PMC_MCKXRDY
35	b	2f
36#endif
371:	mov	r7, #AT91_PMC_MCKRDY
382:	ldr	r8, [pmc, #AT91_PMC_SR]
39	and	r8, r7
40	cmp	r8, r7
41	bne	2b
42	.endm
43
44/*
45 * Wait until master oscillator has stabilized.
46 *
47 * Side effects: overwrites r7
48 */
49	.macro wait_moscrdy
501:	ldr	r7, [pmc, #AT91_PMC_SR]
51	tst	r7, #AT91_PMC_MOSCS
52	beq	1b
53	.endm
54
55/*
56 * Wait for main oscillator selection is done
57 *
58 * Side effects: overwrites r7
59 */
60	.macro wait_moscsels
611:	ldr	r7, [pmc, #AT91_PMC_SR]
62	tst	r7, #AT91_PMC_MOSCSELS
63	beq	1b
64	.endm
65
66/*
67 * Put the processor to enter the idle state
68 *
69 * Side effects: overwrites r7
70 */
71	.macro at91_cpu_idle
72
73#if defined(CONFIG_CPU_V7)
74	mov	r7, #AT91_PMC_PCK
75	str	r7, [pmc, #AT91_PMC_SCDR]
76
77	dsb
78
79	wfi		@ Wait For Interrupt
80#else
81	mcr	p15, 0, tmp1, c7, c0, 4
82#endif
83
84	.endm
85
86/**
87 * Set state for 2.5V low power regulator
88 * @ena: 0 - disable regulator
89 *	 1 - enable regulator
90 *
91 * Side effects: overwrites r7, r8, r9, r10
92 */
93	.macro at91_2_5V_reg_set_low_power ena
94#ifdef CONFIG_SOC_SAMA7
95	ldr	r7, .sfrbu
96	mov	r8, #\ena
97	ldr	r9, [r7, #AT91_SFRBU_25LDOCR]
98	orr	r9, r9, #AT91_SFRBU_25LDOCR_LP
99	cmp	r8, #1
100	beq	lp_done_\ena
101	bic	r9, r9, #AT91_SFRBU_25LDOCR_LP
102lp_done_\ena:
103	ldr	r10, =AT91_SFRBU_25LDOCR_LDOANAKEY
104	orr	r9, r9, r10
105	str	r9, [r7, #AT91_SFRBU_25LDOCR]
106#endif
107	.endm
108
109	.macro at91_backup_set_lpm reg
110#ifdef CONFIG_SOC_SAMA7
111	orr	\reg, \reg, #0x200000
112#endif
113	.endm
114
115	.text
116
117	.arm
118
119#ifdef CONFIG_SOC_SAMA7
120/**
121 * Enable self-refresh
122 *
123 * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7
124 */
125.macro at91_sramc_self_refresh_ena
126	ldr	r2, .sramc_base
127	ldr	r3, .sramc_phy_base
128	ldr	r7, .pm_mode
129
130	dsb
131
132	/* Disable all AXI ports. */
133	ldr	tmp1, [r2, #UDDRC_PCTRL_0]
134	bic	tmp1, tmp1, #0x1
135	str	tmp1, [r2, #UDDRC_PCTRL_0]
136
137	ldr	tmp1, [r2, #UDDRC_PCTRL_1]
138	bic	tmp1, tmp1, #0x1
139	str	tmp1, [r2, #UDDRC_PCTRL_1]
140
141	ldr	tmp1, [r2, #UDDRC_PCTRL_2]
142	bic	tmp1, tmp1, #0x1
143	str	tmp1, [r2, #UDDRC_PCTRL_2]
144
145	ldr	tmp1, [r2, #UDDRC_PCTRL_3]
146	bic	tmp1, tmp1, #0x1
147	str	tmp1, [r2, #UDDRC_PCTRL_3]
148
149	ldr	tmp1, [r2, #UDDRC_PCTRL_4]
150	bic	tmp1, tmp1, #0x1
151	str	tmp1, [r2, #UDDRC_PCTRL_4]
152
153sr_ena_1:
154	/* Wait for all ports to disable. */
155	ldr	tmp1, [r2, #UDDRC_PSTAT]
156	ldr	tmp2, =UDDRC_PSTAT_ALL_PORTS
157	tst	tmp1, tmp2
158	bne	sr_ena_1
159
160	/* Switch to self-refresh. */
161	ldr	tmp1, [r2, #UDDRC_PWRCTL]
162	orr	tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
163	str	tmp1, [r2, #UDDRC_PWRCTL]
164
165sr_ena_2:
166	/* Wait for self-refresh enter. */
167	ldr	tmp1, [r2, #UDDRC_STAT]
168	bic	tmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK
169	cmp	tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
170	bne	sr_ena_2
171
172	/* Disable DX DLLs for non-backup modes. */
173	cmp	r7, #AT91_PM_BACKUP
174	beq	sr_ena_3
175
176	/* Do not soft reset the AC DLL. */
177	ldr	tmp1, [r3, DDR3PHY_ACDLLCR]
178	bic	tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST
179	str	tmp1, [r3, DDR3PHY_ACDLLCR]
180
181	/* Disable DX DLLs. */
182	ldr	tmp1, [r3, #DDR3PHY_DX0DLLCR]
183	orr	tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
184	str	tmp1, [r3, #DDR3PHY_DX0DLLCR]
185
186	ldr	tmp1, [r3, #DDR3PHY_DX1DLLCR]
187	orr	tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
188	str	tmp1, [r3, #DDR3PHY_DX1DLLCR]
189
190sr_ena_3:
191	/* Power down DDR PHY data receivers. */
192	ldr	tmp1, [r3, #DDR3PHY_DXCCR]
193	orr	tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
194	str	tmp1, [r3, #DDR3PHY_DXCCR]
195
196	/* Power down ADDR/CMD IO. */
197	ldr	tmp1, [r3, #DDR3PHY_ACIOCR]
198	orr	tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
199	orr	tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
200	orr	tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
201	str	tmp1, [r3, #DDR3PHY_ACIOCR]
202
203	/* Power down ODT. */
204	ldr	tmp1, [r3, #DDR3PHY_DSGCR]
205	orr	tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
206	str	tmp1, [r3, #DDR3PHY_DSGCR]
207.endm
208
209/**
210 * Disable self-refresh
211 *
212 * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3
213 */
214.macro at91_sramc_self_refresh_dis
215	ldr	r2, .sramc_base
216	ldr	r3, .sramc_phy_base
217
218	/* Power up DDR PHY data receivers. */
219	ldr	tmp1, [r3, #DDR3PHY_DXCCR]
220	bic	tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
221	str	tmp1, [r3, #DDR3PHY_DXCCR]
222
223	/* Power up the output of CK and CS pins. */
224	ldr	tmp1, [r3, #DDR3PHY_ACIOCR]
225	bic	tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
226	bic	tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
227	bic	tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
228	str	tmp1, [r3, #DDR3PHY_ACIOCR]
229
230	/* Power up ODT. */
231	ldr	tmp1, [r3, #DDR3PHY_DSGCR]
232	bic	tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
233	str	tmp1, [r3, #DDR3PHY_DSGCR]
234
235	/* Enable DX DLLs. */
236	ldr	tmp1, [r3, #DDR3PHY_DX0DLLCR]
237	bic	tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
238	str	tmp1, [r3, #DDR3PHY_DX0DLLCR]
239
240	ldr	tmp1, [r3, #DDR3PHY_DX1DLLCR]
241	bic	tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
242	str	tmp1, [r3, #DDR3PHY_DX1DLLCR]
243
244	/* Enable quasi-dynamic programming. */
245	mov	tmp1, #0
246	str	tmp1, [r2, #UDDRC_SWCTRL]
247
248	/* De-assert SDRAM initialization. */
249	ldr	tmp1, [r2, #UDDRC_DFIMISC]
250	bic	tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
251	str	tmp1, [r2, #UDDRC_DFIMISC]
252
253	/* Quasi-dynamic programming done. */
254	mov	tmp1, #UDDRC_SWCTRL_SW_DONE
255	str	tmp1, [r2, #UDDRC_SWCTRL]
256
257sr_dis_1:
258	ldr	tmp1, [r2, #UDDRC_SWSTAT]
259	tst	tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
260	beq	sr_dis_1
261
262	/* DLL soft-reset + DLL lock wait + ITM reset */
263	mov	tmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \
264			DDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST)
265	str	tmp1, [r3, #DDR3PHY_PIR]
266
267sr_dis_4:
268	/* Wait for it. */
269	ldr	tmp1, [r3, #DDR3PHY_PGSR]
270	tst	tmp1, #DDR3PHY_PGSR_IDONE
271	beq	sr_dis_4
272
273	/* Enable quasi-dynamic programming. */
274	mov	tmp1, #0
275	str	tmp1, [r2, #UDDRC_SWCTRL]
276
277	/* Assert PHY init complete enable signal. */
278	ldr	tmp1, [r2, #UDDRC_DFIMISC]
279	orr	tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
280	str	tmp1, [r2, #UDDRC_DFIMISC]
281
282	/* Programming is done. Set sw_done. */
283	mov	tmp1, #UDDRC_SWCTRL_SW_DONE
284	str	tmp1, [r2, #UDDRC_SWCTRL]
285
286sr_dis_5:
287	/* Wait for it. */
288	ldr	tmp1, [r2, #UDDRC_SWSTAT]
289	tst	tmp1, #UDDRC_SWSTAT_SW_DONE_ACK
290	beq	sr_dis_5
291
292	/* Trigger self-refresh exit. */
293	ldr	tmp1, [r2, #UDDRC_PWRCTL]
294	bic	tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
295	str	tmp1, [r2, #UDDRC_PWRCTL]
296
297sr_dis_6:
298	/* Wait for self-refresh exit done. */
299	ldr	tmp1, [r2, #UDDRC_STAT]
300	bic	tmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK
301	cmp	tmp1, #UDDRC_STAT_OPMODE_NORMAL
302	bne	sr_dis_6
303
304	/* Enable all AXI ports. */
305	ldr	tmp1, [r2, #UDDRC_PCTRL_0]
306	orr	tmp1, tmp1, #0x1
307	str	tmp1, [r2, #UDDRC_PCTRL_0]
308
309	ldr	tmp1, [r2, #UDDRC_PCTRL_1]
310	orr	tmp1, tmp1, #0x1
311	str	tmp1, [r2, #UDDRC_PCTRL_1]
312
313	ldr	tmp1, [r2, #UDDRC_PCTRL_2]
314	orr	tmp1, tmp1, #0x1
315	str	tmp1, [r2, #UDDRC_PCTRL_2]
316
317	ldr	tmp1, [r2, #UDDRC_PCTRL_3]
318	orr	tmp1, tmp1, #0x1
319	str	tmp1, [r2, #UDDRC_PCTRL_3]
320
321	ldr	tmp1, [r2, #UDDRC_PCTRL_4]
322	orr	tmp1, tmp1, #0x1
323	str	tmp1, [r2, #UDDRC_PCTRL_4]
324
325	dsb
326.endm
327#else
328/**
329 * Enable self-refresh
330 *
331 * register usage:
332 * 	@r1: memory type
333 *	@r2: base address of the sram controller
334 *	@r3: temporary
335 */
336.macro at91_sramc_self_refresh_ena
337	ldr	r1, .memtype
338	ldr	r2, .sramc_base
339
340	cmp	r1, #AT91_MEMCTRL_MC
341	bne	sr_ena_ddrc_sf
342
343	/* Active SDRAM self-refresh mode */
344	mov	r3, #1
345	str	r3, [r2, #AT91_MC_SDRAMC_SRR]
346	b	sr_ena_exit
347
348sr_ena_ddrc_sf:
349	cmp	r1, #AT91_MEMCTRL_DDRSDR
350	bne	sr_ena_sdramc_sf
351
352	/*
353	 * DDR Memory controller
354	 */
355
356	/* LPDDR1 --> force DDR2 mode during self-refresh */
357	ldr	r3, [r2, #AT91_DDRSDRC_MDR]
358	str	r3, .saved_sam9_mdr
359	bic	r3, r3, #~AT91_DDRSDRC_MD
360	cmp	r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
361	ldreq	r3, [r2, #AT91_DDRSDRC_MDR]
362	biceq	r3, r3, #AT91_DDRSDRC_MD
363	orreq	r3, r3, #AT91_DDRSDRC_MD_DDR2
364	streq	r3, [r2, #AT91_DDRSDRC_MDR]
365
366	/* Active DDRC self-refresh mode */
367	ldr	r3, [r2, #AT91_DDRSDRC_LPR]
368	str	r3, .saved_sam9_lpr
369	bic	r3, r3, #AT91_DDRSDRC_LPCB
370	orr	r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
371	str	r3, [r2, #AT91_DDRSDRC_LPR]
372
373	/* If using the 2nd ddr controller */
374	ldr	r2, .sramc1_base
375	cmp	r2, #0
376	beq	sr_ena_no_2nd_ddrc
377
378	ldr	r3, [r2, #AT91_DDRSDRC_MDR]
379	str	r3, .saved_sam9_mdr1
380	bic	r3, r3, #~AT91_DDRSDRC_MD
381	cmp	r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
382	ldreq	r3, [r2, #AT91_DDRSDRC_MDR]
383	biceq	r3, r3, #AT91_DDRSDRC_MD
384	orreq	r3, r3, #AT91_DDRSDRC_MD_DDR2
385	streq	r3, [r2, #AT91_DDRSDRC_MDR]
386
387	/* Active DDRC self-refresh mode */
388	ldr	r3, [r2, #AT91_DDRSDRC_LPR]
389	str	r3, .saved_sam9_lpr1
390	bic	r3, r3, #AT91_DDRSDRC_LPCB
391	orr	r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
392	str	r3, [r2, #AT91_DDRSDRC_LPR]
393
394sr_ena_no_2nd_ddrc:
395	b	sr_ena_exit
396
397	/*
398	 * SDRAMC Memory controller
399	 */
400sr_ena_sdramc_sf:
401	/* Active SDRAMC self-refresh mode */
402	ldr	r3, [r2, #AT91_SDRAMC_LPR]
403	str	r3, .saved_sam9_lpr
404	bic	r3, r3, #AT91_SDRAMC_LPCB
405	orr	r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
406	str	r3, [r2, #AT91_SDRAMC_LPR]
407
408	ldr	r3, .saved_sam9_lpr
409	str	r3, [r2, #AT91_SDRAMC_LPR]
410
411sr_ena_exit:
412.endm
413
414/**
415 * Disable self-refresh
416 *
417 * register usage:
418 * 	@r1: memory type
419 *	@r2: base address of the sram controller
420 *	@r3: temporary
421 */
422.macro at91_sramc_self_refresh_dis
423	ldr	r1, .memtype
424	ldr	r2, .sramc_base
425
426	cmp	r1, #AT91_MEMCTRL_MC
427	bne	sr_dis_ddrc_exit_sf
428
429	/*
430	 * at91rm9200 Memory controller
431	 */
432
433	 /*
434	  * For exiting the self-refresh mode, do nothing,
435	  * automatically exit the self-refresh mode.
436	  */
437	b	sr_dis_exit
438
439sr_dis_ddrc_exit_sf:
440	cmp	r1, #AT91_MEMCTRL_DDRSDR
441	bne	sdramc_exit_sf
442
443	/* DDR Memory controller */
444
445	/* Restore MDR in case of LPDDR1 */
446	ldr	r3, .saved_sam9_mdr
447	str	r3, [r2, #AT91_DDRSDRC_MDR]
448	/* Restore LPR on AT91 with DDRAM */
449	ldr	r3, .saved_sam9_lpr
450	str	r3, [r2, #AT91_DDRSDRC_LPR]
451
452	/* If using the 2nd ddr controller */
453	ldr	r2, .sramc1_base
454	cmp	r2, #0
455	ldrne	r3, .saved_sam9_mdr1
456	strne	r3, [r2, #AT91_DDRSDRC_MDR]
457	ldrne	r3, .saved_sam9_lpr1
458	strne	r3, [r2, #AT91_DDRSDRC_LPR]
459
460	b	sr_dis_exit
461
462sdramc_exit_sf:
463	/* SDRAMC Memory controller */
464	ldr	r3, .saved_sam9_lpr
465	str	r3, [r2, #AT91_SDRAMC_LPR]
466
467sr_dis_exit:
468.endm
469#endif
470
471.macro at91_pm_ulp0_mode
472	ldr	pmc, .pmc_base
473	ldr	tmp2, .pm_mode
474	ldr	tmp3, .mckr_offset
475
476	/* Check if ULP0 fast variant has been requested. */
477	cmp	tmp2, #AT91_PM_ULP0_FAST
478	bne	0f
479
480	/* Set highest prescaler for power saving */
481	ldr	tmp1, [pmc, tmp3]
482	bic	tmp1, tmp1, #AT91_PMC_PRES
483	orr	tmp1, tmp1, #AT91_PMC_PRES_64
484	str	tmp1, [pmc, tmp3]
485
486	mov	tmp3, #0
487	wait_mckrdy tmp3
488	b	1f
489
4900:
491	/* Turn off the crystal oscillator */
492	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
493	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
494	orr	tmp1, tmp1, #AT91_PMC_KEY
495	str	tmp1, [pmc, #AT91_CKGR_MOR]
496
497	/* Save RC oscillator state */
498	ldr	tmp1, [pmc, #AT91_PMC_SR]
499	str	tmp1, .saved_osc_status
500	tst	tmp1, #AT91_PMC_MOSCRCS
501	bne	1f
502
503	/* Turn off RC oscillator */
504	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
505	bic	tmp1, tmp1, #AT91_PMC_MOSCRCEN
506	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
507	orr	tmp1, tmp1, #AT91_PMC_KEY
508	str	tmp1, [pmc, #AT91_CKGR_MOR]
509
510	/* Wait main RC disabled done */
5112:	ldr	tmp1, [pmc, #AT91_PMC_SR]
512	tst	tmp1, #AT91_PMC_MOSCRCS
513	bne	2b
514
515	/* Wait for interrupt */
5161:	at91_cpu_idle
517
518	/* Check if ULP0 fast variant has been requested. */
519	cmp	tmp2, #AT91_PM_ULP0_FAST
520	bne	5f
521
522	/* Set lowest prescaler for fast resume. */
523	ldr	tmp3, .mckr_offset
524	ldr	tmp1, [pmc, tmp3]
525	bic	tmp1, tmp1, #AT91_PMC_PRES
526	str	tmp1, [pmc, tmp3]
527
528	mov	tmp3, #0
529	wait_mckrdy tmp3
530	b	6f
531
5325:	/* Restore RC oscillator state */
533	ldr	tmp1, .saved_osc_status
534	tst	tmp1, #AT91_PMC_MOSCRCS
535	beq	4f
536
537	/* Turn on RC oscillator */
538	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
539	orr	tmp1, tmp1, #AT91_PMC_MOSCRCEN
540	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
541	orr	tmp1, tmp1, #AT91_PMC_KEY
542	str	tmp1, [pmc, #AT91_CKGR_MOR]
543
544	/* Wait main RC stabilization */
5453:	ldr	tmp1, [pmc, #AT91_PMC_SR]
546	tst	tmp1, #AT91_PMC_MOSCRCS
547	beq	3b
548
549	/* Turn on the crystal oscillator */
5504:	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
551	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
552	orr	tmp1, tmp1, #AT91_PMC_KEY
553	str	tmp1, [pmc, #AT91_CKGR_MOR]
554
555	wait_moscrdy
5566:
557.endm
558
559/**
560 * Note: This procedure only applies on the platform which uses
561 * the external crystal oscillator as a main clock source.
562 */
563.macro at91_pm_ulp1_mode
564	ldr	pmc, .pmc_base
565	ldr	tmp2, .mckr_offset
566	mov	tmp3, #0
567
568	/* Save RC oscillator state and check if it is enabled. */
569	ldr	tmp1, [pmc, #AT91_PMC_SR]
570	str	tmp1, .saved_osc_status
571	tst	tmp1, #AT91_PMC_MOSCRCS
572	bne	2f
573
574	/* Enable RC oscillator */
575	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
576	orr	tmp1, tmp1, #AT91_PMC_MOSCRCEN
577	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
578	orr	tmp1, tmp1, #AT91_PMC_KEY
579	str	tmp1, [pmc, #AT91_CKGR_MOR]
580
581	/* Wait main RC stabilization */
5821:	ldr	tmp1, [pmc, #AT91_PMC_SR]
583	tst	tmp1, #AT91_PMC_MOSCRCS
584	beq	1b
585
586	/* Switch the main clock source to 12-MHz RC oscillator */
5872:	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
588	bic	tmp1, tmp1, #AT91_PMC_MOSCSEL
589	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
590	orr	tmp1, tmp1, #AT91_PMC_KEY
591	str	tmp1, [pmc, #AT91_CKGR_MOR]
592
593	wait_moscsels
594
595	/* Disable the crystal oscillator */
596	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
597	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
598	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
599	orr	tmp1, tmp1, #AT91_PMC_KEY
600	str	tmp1, [pmc, #AT91_CKGR_MOR]
601
602	/* Switch the master clock source to main clock */
603	ldr	tmp1, [pmc, tmp2]
604	bic	tmp1, tmp1, #AT91_PMC_CSS
605	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
606	str	tmp1, [pmc, tmp2]
607
608	wait_mckrdy tmp3
609
610	/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
611	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
612	orr	tmp1, tmp1, #AT91_PMC_WAITMODE
613	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
614	orr	tmp1, tmp1, #AT91_PMC_KEY
615	str	tmp1, [pmc, #AT91_CKGR_MOR]
616
617	/* Quirk for SAM9X60's PMC */
618	nop
619	nop
620
621	wait_mckrdy tmp3
622
623	/* Enable the crystal oscillator */
624	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
625	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
626	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
627	orr	tmp1, tmp1, #AT91_PMC_KEY
628	str	tmp1, [pmc, #AT91_CKGR_MOR]
629
630	wait_moscrdy
631
632	/* Switch the master clock source to slow clock */
633	ldr	tmp1, [pmc, tmp2]
634	bic	tmp1, tmp1, #AT91_PMC_CSS
635	str	tmp1, [pmc, tmp2]
636
637	wait_mckrdy tmp3
638
639	/* Switch main clock source to crystal oscillator */
640	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
641	orr	tmp1, tmp1, #AT91_PMC_MOSCSEL
642	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
643	orr	tmp1, tmp1, #AT91_PMC_KEY
644	str	tmp1, [pmc, #AT91_CKGR_MOR]
645
646	wait_moscsels
647
648	/* Switch the master clock source to main clock */
649	ldr	tmp1, [pmc, tmp2]
650	bic	tmp1, tmp1, #AT91_PMC_CSS
651	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
652	str	tmp1, [pmc, tmp2]
653
654	wait_mckrdy tmp3
655
656	/* Restore RC oscillator state */
657	ldr	tmp1, .saved_osc_status
658	tst	tmp1, #AT91_PMC_MOSCRCS
659	bne	3f
660
661	/* Disable RC oscillator */
662	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
663	bic	tmp1, tmp1, #AT91_PMC_MOSCRCEN
664	bic	tmp1, tmp1, #AT91_PMC_KEY_MASK
665	orr	tmp1, tmp1, #AT91_PMC_KEY
666	str	tmp1, [pmc, #AT91_CKGR_MOR]
667
668	/* Wait RC oscillator disable done */
6694:	ldr	tmp1, [pmc, #AT91_PMC_SR]
670	tst	tmp1, #AT91_PMC_MOSCRCS
671	bne	4b
672
6733:
674.endm
675
676.macro at91_plla_disable
677	/* Save PLLA setting and disable it */
678	ldr	tmp1, .pmc_version
679	cmp	tmp1, #AT91_PMC_V1
680	beq	1f
681
682#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL
683	/* Save PLLA settings. */
684	ldr	tmp2, [pmc, #AT91_PMC_PLL_UPDT]
685	bic	tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
686	str	tmp2, [pmc, #AT91_PMC_PLL_UPDT]
687
688	/* save div. */
689	mov	tmp1, #0
690	ldr	tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
691	bic	tmp2, tmp2, #0xffffff00
692	orr	tmp1, tmp1, tmp2
693
694	/* save mul. */
695	ldr	tmp2, [pmc, #AT91_PMC_PLL_CTRL1]
696	bic	tmp2, tmp2, #0xffffff
697	orr	tmp1, tmp1, tmp2
698	str	tmp1, .saved_pllar
699
700	/* step 2. */
701	ldr	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
702	bic	tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
703	bic	tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
704	str	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
705
706	/* step 3. */
707	ldr	tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
708	bic	tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
709	orr	tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
710	str	tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
711
712	/* step 4. */
713	ldr	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
714	orr	tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
715	bic	tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
716	str	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
717
718	/* step 5. */
719	ldr	tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
720	bic	tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
721	str	tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
722
723	/* step 7. */
724	ldr	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
725	orr	tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
726	bic	tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
727	str	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
728
729	b	2f
730#endif
731
7321:	/* Save PLLA setting and disable it */
733	ldr	tmp1, [pmc, #AT91_CKGR_PLLAR]
734	str	tmp1, .saved_pllar
735
736	/* Disable PLLA. */
737	mov	tmp1, #AT91_PMC_PLLCOUNT
738	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
739	str	tmp1, [pmc, #AT91_CKGR_PLLAR]
7402:
741.endm
742
743.macro at91_plla_enable
744	ldr	tmp2, .saved_pllar
745	ldr	tmp3, .pmc_version
746	cmp	tmp3, #AT91_PMC_V1
747	beq	4f
748
749#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL
750	/* step 1. */
751	ldr	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
752	bic	tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
753	bic	tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
754	str	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
755
756	/* step 2. */
757	ldr	tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
758	str	tmp1, [pmc, #AT91_PMC_PLL_ACR]
759
760	/* step 3. */
761	ldr	tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
762	mov	tmp3, tmp2
763	bic	tmp3, tmp3, #0xffffff
764	orr	tmp1, tmp1, tmp3
765	str	tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
766
767	/* step 8. */
768	ldr	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
769	bic	tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
770	orr	tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
771	str	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
772
773	/* step 9. */
774	ldr	tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
775	orr	tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK
776	orr	tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
777	orr	tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
778	bic	tmp1, tmp1, #0xff
779	mov	tmp3, tmp2
780	bic	tmp3, tmp3, #0xffffff00
781	orr	tmp1, tmp1, tmp3
782	str	tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
783
784	/* step 10. */
785	ldr	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
786	orr	tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
787	bic	tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID
788	str	tmp1, [pmc, #AT91_PMC_PLL_UPDT]
789
790	/* step 11. */
7913:	ldr	tmp1, [pmc, #AT91_PMC_PLL_ISR0]
792	tst	tmp1, #0x1
793	beq	3b
794	b	2f
795#endif
796
797	/* Restore PLLA setting */
7984:	str	tmp2, [pmc, #AT91_CKGR_PLLAR]
799
800	/* Enable PLLA. */
801	tst	tmp2, #(AT91_PMC_MUL &  0xff0000)
802	bne	1f
803	tst	tmp2, #(AT91_PMC_MUL & ~0xff0000)
804	beq	2f
805
8061:	ldr	tmp1, [pmc, #AT91_PMC_SR]
807	tst	tmp1, #AT91_PMC_LOCKA
808	beq	1b
8092:
810.endm
811
812/**
813 * at91_mckx_ps_enable:	save MCK1..4 settings and switch it to main clock
814 *
815 * Side effects: overwrites tmp1, tmp2
816 */
817.macro at91_mckx_ps_enable
818#ifdef CONFIG_SOC_SAMA7
819	ldr	pmc, .pmc_base
820
821	/* There are 4 MCKs we need to handle: MCK1..4 */
822	mov	tmp1, #1
823e_loop:	cmp	tmp1, #5
824	beq	e_done
825
826	/* Write MCK ID to retrieve the settings. */
827	str	tmp1, [pmc, #AT91_PMC_MCR_V2]
828	ldr	tmp2, [pmc, #AT91_PMC_MCR_V2]
829
830e_save_mck1:
831	cmp	tmp1, #1
832	bne	e_save_mck2
833	str	tmp2, .saved_mck1
834	b	e_ps
835
836e_save_mck2:
837	cmp	tmp1, #2
838	bne	e_save_mck3
839	str	tmp2, .saved_mck2
840	b	e_ps
841
842e_save_mck3:
843	cmp	tmp1, #3
844	bne	e_save_mck4
845	str	tmp2, .saved_mck3
846	b	e_ps
847
848e_save_mck4:
849	str	tmp2, .saved_mck4
850
851e_ps:
852	/* Use CSS=MAINCK and DIV=1. */
853	bic	tmp2, tmp2, #AT91_PMC_MCR_V2_CSS
854	bic	tmp2, tmp2, #AT91_PMC_MCR_V2_DIV
855	orr	tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK
856	orr	tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1
857	str	tmp2, [pmc, #AT91_PMC_MCR_V2]
858
859	wait_mckrdy tmp1
860
861	add	tmp1, tmp1, #1
862	b	e_loop
863
864e_done:
865#endif
866.endm
867
868/**
869 * at91_mckx_ps_restore: restore MCK1..4 settings
870 *
871 * Side effects: overwrites tmp1, tmp2
872 */
873.macro at91_mckx_ps_restore
874#ifdef CONFIG_SOC_SAMA7
875	ldr	pmc, .pmc_base
876
877	/* There are 4 MCKs we need to handle: MCK1..4 */
878	mov	tmp1, #1
879r_loop:	cmp	tmp1, #5
880	beq	r_done
881
882r_save_mck1:
883	cmp	tmp1, #1
884	bne	r_save_mck2
885	ldr	tmp2, .saved_mck1
886	b	r_ps
887
888r_save_mck2:
889	cmp	tmp1, #2
890	bne	r_save_mck3
891	ldr	tmp2, .saved_mck2
892	b	r_ps
893
894r_save_mck3:
895	cmp	tmp1, #3
896	bne	r_save_mck4
897	ldr	tmp2, .saved_mck3
898	b	r_ps
899
900r_save_mck4:
901	ldr	tmp2, .saved_mck4
902
903r_ps:
904	/* Write MCK ID to retrieve the settings. */
905	str	tmp1, [pmc, #AT91_PMC_MCR_V2]
906	ldr	tmp3, [pmc, #AT91_PMC_MCR_V2]
907
908	/* We need to restore CSS and DIV. */
909	bic	tmp3, tmp3, #AT91_PMC_MCR_V2_CSS
910	bic	tmp3, tmp3, #AT91_PMC_MCR_V2_DIV
911	orr	tmp3, tmp3, tmp2
912	bic	tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK
913	orr	tmp3, tmp3, tmp1
914	orr	tmp3, tmp3, #AT91_PMC_MCR_V2_CMD
915	str	tmp2, [pmc, #AT91_PMC_MCR_V2]
916
917	wait_mckrdy tmp1
918
919	add	tmp1, tmp1, #1
920	b	r_loop
921r_done:
922#endif
923.endm
924
925.macro at91_ulp_mode
926	at91_mckx_ps_enable
927
928	ldr	pmc, .pmc_base
929	ldr	tmp2, .mckr_offset
930	ldr	tmp3, .pm_mode
931
932	/* Save Master clock setting */
933	ldr	tmp1, [pmc, tmp2]
934	str	tmp1, .saved_mckr
935
936	/*
937	 * Set master clock source to:
938	 * - MAINCK if using ULP0 fast variant
939	 * - slow clock, otherwise
940	 */
941	bic	tmp1, tmp1, #AT91_PMC_CSS
942	cmp	tmp3, #AT91_PM_ULP0_FAST
943	bne	save_mck
944	orr	tmp1, tmp1, #AT91_PMC_CSS_MAIN
945save_mck:
946	str	tmp1, [pmc, tmp2]
947
948	mov	tmp3, #0
949	wait_mckrdy tmp3
950
951	at91_plla_disable
952
953	/* Enable low power mode for 2.5V regulator. */
954	at91_2_5V_reg_set_low_power 1
955
956	ldr	tmp3, .pm_mode
957	cmp	tmp3, #AT91_PM_ULP1
958	beq	ulp1_mode
959
960	at91_pm_ulp0_mode
961	b	ulp_exit
962
963ulp1_mode:
964	at91_pm_ulp1_mode
965	b	ulp_exit
966
967ulp_exit:
968	/* Disable low power mode for 2.5V regulator. */
969	at91_2_5V_reg_set_low_power 0
970
971	ldr	pmc, .pmc_base
972
973	at91_plla_enable
974
975	/*
976	 * Restore master clock setting
977	 */
978	ldr	tmp1, .mckr_offset
979	ldr	tmp2, .saved_mckr
980	str	tmp2, [pmc, tmp1]
981
982	mov	tmp3, #0
983	wait_mckrdy tmp3
984
985	at91_mckx_ps_restore
986.endm
987
988.macro at91_backup_mode
989	/* Switch the master clock source to slow clock. */
990	ldr	pmc, .pmc_base
991	ldr	tmp2, .mckr_offset
992	ldr	tmp1, [pmc, tmp2]
993	bic	tmp1, tmp1, #AT91_PMC_CSS
994	str	tmp1, [pmc, tmp2]
995
996	mov	tmp3, #0
997	wait_mckrdy tmp3
998
999	/*BUMEN*/
1000	ldr	r0, .sfrbu
1001	mov	tmp1, #0x1
1002	str	tmp1, [r0, #0x10]
1003
1004	/* Wait for it. */
10051:	ldr	tmp1, [r0, #0x10]
1006	tst	tmp1, #0x1
1007	beq	1b
1008
1009	/* Shutdown */
1010	ldr	r0, .shdwc
1011	mov	tmp1, #0xA5000000
1012	add	tmp1, tmp1, #0x1
1013	at91_backup_set_lpm tmp1
1014	str	tmp1, [r0, #0]
1015.endm
1016
1017/*
1018 * void at91_suspend_sram_fn(struct at91_pm_data*)
1019 * @input param:
1020 * 	@r0: base address of struct at91_pm_data
1021 */
1022/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
1023	.align 3
1024ENTRY(at91_pm_suspend_in_sram)
1025	/* Save registers on stack */
1026	stmfd	sp!, {r4 - r12, lr}
1027
1028	/* Drain write buffer */
1029	mov	tmp1, #0
1030	mcr	p15, 0, tmp1, c7, c10, 4
1031
1032	/* Flush tlb. */
1033	mov	r4, #0
1034	mcr	p15, 0, r4, c8, c7, 0
1035
1036	ldr	tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
1037	str	tmp1, .mckr_offset
1038	ldr	tmp1, [r0, #PM_DATA_PMC_VERSION]
1039	str	tmp1, .pmc_version
1040	ldr	tmp1, [r0, #PM_DATA_MEMCTRL]
1041	str	tmp1, .memtype
1042	ldr	tmp1, [r0, #PM_DATA_MODE]
1043	str	tmp1, .pm_mode
1044
1045	/*
1046	 * ldrne below are here to preload their address in the TLB as access
1047	 * to RAM may be limited while in self-refresh.
1048	 */
1049	ldr	tmp1, [r0, #PM_DATA_PMC]
1050	str	tmp1, .pmc_base
1051	cmp	tmp1, #0
1052	ldrne	tmp2, [tmp1, #0]
1053
1054	ldr	tmp1, [r0, #PM_DATA_RAMC0]
1055	str	tmp1, .sramc_base
1056	cmp	tmp1, #0
1057	ldrne	tmp2, [tmp1, #0]
1058
1059	ldr	tmp1, [r0, #PM_DATA_RAMC1]
1060	str	tmp1, .sramc1_base
1061	cmp	tmp1, #0
1062	ldrne	tmp2, [tmp1, #0]
1063
1064#ifndef CONFIG_SOC_SAM_V4_V5
1065	/* ldrne below are here to preload their address in the TLB */
1066	ldr	tmp1, [r0, #PM_DATA_RAMC_PHY]
1067	str	tmp1, .sramc_phy_base
1068	cmp	tmp1, #0
1069	ldrne	tmp2, [tmp1, #0]
1070
1071	ldr	tmp1, [r0, #PM_DATA_SHDWC]
1072	str	tmp1, .shdwc
1073	cmp	tmp1, #0
1074	ldrne	tmp2, [tmp1, #0]
1075
1076	ldr	tmp1, [r0, #PM_DATA_SFRBU]
1077	str	tmp1, .sfrbu
1078	cmp	tmp1, #0
1079	ldrne	tmp2, [tmp1, #0x10]
1080#endif
1081
1082	/* Active the self-refresh mode */
1083	at91_sramc_self_refresh_ena
1084
1085	ldr	r0, .pm_mode
1086	cmp	r0, #AT91_PM_STANDBY
1087	beq	standby
1088	cmp	r0, #AT91_PM_BACKUP
1089	beq	backup_mode
1090
1091	at91_ulp_mode
1092	b	exit_suspend
1093
1094standby:
1095	/* Wait for interrupt */
1096	ldr	pmc, .pmc_base
1097	at91_cpu_idle
1098	b	exit_suspend
1099
1100backup_mode:
1101	at91_backup_mode
1102
1103exit_suspend:
1104	/* Exit the self-refresh mode */
1105	at91_sramc_self_refresh_dis
1106
1107	/* Restore registers, and return */
1108	ldmfd	sp!, {r4 - r12, pc}
1109ENDPROC(at91_pm_suspend_in_sram)
1110
1111.pmc_base:
1112	.word 0
1113.sramc_base:
1114	.word 0
1115.sramc1_base:
1116	.word 0
1117.sramc_phy_base:
1118	.word 0
1119.shdwc:
1120	.word 0
1121.sfrbu:
1122	.word 0
1123.memtype:
1124	.word 0
1125.pm_mode:
1126	.word 0
1127.mckr_offset:
1128	.word 0
1129.pmc_version:
1130	.word 0
1131.saved_mckr:
1132	.word 0
1133.saved_pllar:
1134	.word 0
1135.saved_sam9_lpr:
1136	.word 0
1137.saved_sam9_lpr1:
1138	.word 0
1139.saved_sam9_mdr:
1140	.word 0
1141.saved_sam9_mdr1:
1142	.word 0
1143.saved_osc_status:
1144	.word 0
1145#ifdef CONFIG_SOC_SAMA7
1146.saved_mck1:
1147	.word 0
1148.saved_mck2:
1149	.word 0
1150.saved_mck3:
1151	.word 0
1152.saved_mck4:
1153	.word 0
1154#endif
1155
1156ENTRY(at91_pm_suspend_in_sram_sz)
1157	.word .-at91_pm_suspend_in_sram
1158