1/*
2 * P1022 DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *       notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *       notice, this list of conditions and the following disclaimer in the
12 *       documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *       names of its contributors may be used to endorse or promote products
15 *       derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36	nor@0,0 {
37		#address-cells = <1>;
38		#size-cells = <1>;
39		compatible = "cfi-flash";
40		reg = <0x0 0x0 0x8000000>;
41		bank-width = <2>;
42		device-width = <1>;
43
44		partition@0 {
45			reg = <0x0 0x03000000>;
46			label = "ramdisk-nor";
47			read-only;
48		};
49
50		partition@3000000 {
51			reg = <0x03000000 0x00e00000>;
52			label = "diagnostic-nor";
53			read-only;
54		};
55
56		partition@3e00000 {
57			reg = <0x03e00000 0x00200000>;
58			label = "dink-nor";
59			read-only;
60		};
61
62		partition@4000000 {
63			reg = <0x04000000 0x00400000>;
64			label = "kernel-nor";
65			read-only;
66		};
67
68		partition@4400000 {
69			reg = <0x04400000 0x03b00000>;
70			label = "jffs2-nor";
71		};
72
73		partition@7f00000 {
74			reg = <0x07f00000 0x00080000>;
75			label = "dtb-nor";
76			read-only;
77		};
78
79		partition@7f80000 {
80			reg = <0x07f80000 0x00080000>;
81			label = "u-boot-nor";
82			read-only;
83		};
84	};
85
86	nand@2,0 {
87		#address-cells = <1>;
88		#size-cells = <1>;
89		compatible = "fsl,elbc-fcm-nand";
90		reg = <0x2 0x0 0x40000>;
91
92		partition@0 {
93			reg = <0x0 0x02000000>;
94			label = "u-boot-nand";
95			read-only;
96		};
97
98		partition@2000000 {
99			reg = <0x02000000 0x10000000>;
100			label = "jffs2-nand";
101		};
102
103		partition@12000000 {
104			reg = <0x12000000 0x10000000>;
105			label = "ramdisk-nand";
106			read-only;
107		};
108
109		partition@22000000 {
110			reg = <0x22000000 0x04000000>;
111			label = "kernel-nand";
112		};
113
114		partition@26000000 {
115			reg = <0x26000000 0x01000000>;
116			label = "dtb-nand";
117			read-only;
118		};
119
120		partition@27000000 {
121			reg = <0x27000000 0x19000000>;
122			label = "reserved-nand";
123		};
124	};
125
126	board-control@3,0 {
127		compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
128		reg = <3 0 0x30>;
129		interrupt-parent = <&mpic>;
130		/*
131		 * IRQ8 is generated if the "EVENT" switch is pressed
132		 * and PX_CTL[EVESEL] is set to 00.
133		 */
134		interrupts = <8 0 0 0>;
135	};
136};
137
138&board_soc {
139	i2c@3100 {
140		wm8776:codec@1a {
141			compatible = "wlf,wm8776";
142			reg = <0x1a>;
143			/*
144			 * clock-frequency will be set by U-Boot if
145			 * the clock is enabled.
146			 */
147		};
148	};
149
150	spi@7000 {
151		flash@0 {
152			#address-cells = <1>;
153			#size-cells = <1>;
154			compatible = "spansion,s25sl12801";
155			reg = <0>;
156			spi-max-frequency = <40000000>; /* input clock */
157
158			partition@0 {
159				label = "u-boot-spi";
160				reg = <0x00000000 0x00100000>;
161				read-only;
162			};
163			partition@100000 {
164				label = "kernel-spi";
165				reg = <0x00100000 0x00500000>;
166				read-only;
167			};
168			partition@600000 {
169				label = "dtb-spi";
170				reg = <0x00600000 0x00100000>;
171				read-only;
172			};
173			partition@700000 {
174				label = "file system-spi";
175				reg = <0x00700000 0x00900000>;
176			};
177		};
178	};
179
180	ssi@15000 {
181		fsl,mode = "i2s-slave";
182		codec-handle = <&wm8776>;
183		fsl,ssi-asynchronous;
184	};
185
186	usb@22000 {
187		phy_type = "ulpi";
188	};
189
190	usb@23000 {
191		status = "disabled";
192	};
193
194	mdio@24000 {
195		phy0: ethernet-phy@0 {
196			interrupts = <3 1 0 0>;
197			reg = <0x1>;
198		};
199		phy1: ethernet-phy@1 {
200			interrupts = <9 1 0 0>;
201			reg = <0x2>;
202		};
203		tbi-phy@2 {
204			device_type = "tbi-phy";
205			reg = <0x2>;
206		};
207	};
208
209	ethernet@b0000 {
210		phy-handle = <&phy0>;
211		phy-connection-type = "rgmii-id";
212	};
213
214	ethernet@b1000 {
215		phy-handle = <&phy1>;
216		phy-connection-type = "rgmii-id";
217	};
218};
219