1 /*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include "drmP.h"
26 #include "nouveau_drv.h"
27 #include "nouveau_ramht.h"
28
29 struct nv50_mpeg_engine {
30 struct nouveau_exec_engine base;
31 };
32
33 static inline u32
CTX_PTR(struct drm_device * dev,u32 offset)34 CTX_PTR(struct drm_device *dev, u32 offset)
35 {
36 struct drm_nouveau_private *dev_priv = dev->dev_private;
37
38 if (dev_priv->chipset == 0x50)
39 offset += 0x0260;
40 else
41 offset += 0x0060;
42
43 return offset;
44 }
45
46 static int
nv50_mpeg_context_new(struct nouveau_channel * chan,int engine)47 nv50_mpeg_context_new(struct nouveau_channel *chan, int engine)
48 {
49 struct drm_device *dev = chan->dev;
50 struct drm_nouveau_private *dev_priv = dev->dev_private;
51 struct nouveau_gpuobj *ramin = chan->ramin;
52 struct nouveau_gpuobj *ctx = NULL;
53 int ret;
54
55 NV_DEBUG(dev, "ch%d\n", chan->id);
56
57 ret = nouveau_gpuobj_new(dev, chan, 128 * 4, 0, NVOBJ_FLAG_ZERO_ALLOC |
58 NVOBJ_FLAG_ZERO_FREE, &ctx);
59 if (ret)
60 return ret;
61
62 nv_wo32(ramin, CTX_PTR(dev, 0x00), 0x80190002);
63 nv_wo32(ramin, CTX_PTR(dev, 0x04), ctx->vinst + ctx->size - 1);
64 nv_wo32(ramin, CTX_PTR(dev, 0x08), ctx->vinst);
65 nv_wo32(ramin, CTX_PTR(dev, 0x0c), 0);
66 nv_wo32(ramin, CTX_PTR(dev, 0x10), 0);
67 nv_wo32(ramin, CTX_PTR(dev, 0x14), 0x00010000);
68
69 nv_wo32(ctx, 0x70, 0x00801ec1);
70 nv_wo32(ctx, 0x7c, 0x0000037c);
71 dev_priv->engine.instmem.flush(dev);
72
73 chan->engctx[engine] = ctx;
74 return 0;
75 }
76
77 static void
nv50_mpeg_context_del(struct nouveau_channel * chan,int engine)78 nv50_mpeg_context_del(struct nouveau_channel *chan, int engine)
79 {
80 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
81 struct nouveau_gpuobj *ctx = chan->engctx[engine];
82 struct drm_device *dev = chan->dev;
83 unsigned long flags;
84 u32 inst, i;
85
86 if (!chan->ramin)
87 return;
88
89 inst = chan->ramin->vinst >> 12;
90 inst |= 0x80000000;
91
92 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
93 nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
94 if (nv_rd32(dev, 0x00b318) == inst)
95 nv_mask(dev, 0x00b318, 0x80000000, 0x00000000);
96 nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
97 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
98
99 for (i = 0x00; i <= 0x14; i += 4)
100 nv_wo32(chan->ramin, CTX_PTR(dev, i), 0x00000000);
101 nouveau_gpuobj_ref(NULL, &ctx);
102 chan->engctx[engine] = NULL;
103 }
104
105 static int
nv50_mpeg_object_new(struct nouveau_channel * chan,int engine,u32 handle,u16 class)106 nv50_mpeg_object_new(struct nouveau_channel *chan, int engine,
107 u32 handle, u16 class)
108 {
109 struct drm_device *dev = chan->dev;
110 struct drm_nouveau_private *dev_priv = dev->dev_private;
111 struct nouveau_gpuobj *obj = NULL;
112 int ret;
113
114 ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
115 if (ret)
116 return ret;
117 obj->engine = 2;
118 obj->class = class;
119
120 nv_wo32(obj, 0x00, class);
121 nv_wo32(obj, 0x04, 0x00000000);
122 nv_wo32(obj, 0x08, 0x00000000);
123 nv_wo32(obj, 0x0c, 0x00000000);
124 dev_priv->engine.instmem.flush(dev);
125
126 ret = nouveau_ramht_insert(chan, handle, obj);
127 nouveau_gpuobj_ref(NULL, &obj);
128 return ret;
129 }
130
131 static void
nv50_mpeg_tlb_flush(struct drm_device * dev,int engine)132 nv50_mpeg_tlb_flush(struct drm_device *dev, int engine)
133 {
134 nv50_vm_flush_engine(dev, 0x08);
135 }
136
137 static int
nv50_mpeg_init(struct drm_device * dev,int engine)138 nv50_mpeg_init(struct drm_device *dev, int engine)
139 {
140 nv_wr32(dev, 0x00b32c, 0x00000000);
141 nv_wr32(dev, 0x00b314, 0x00000100);
142 nv_wr32(dev, 0x00b0e0, 0x0000001a);
143
144 nv_wr32(dev, 0x00b220, 0x00000044);
145 nv_wr32(dev, 0x00b300, 0x00801ec1);
146 nv_wr32(dev, 0x00b390, 0x00000000);
147 nv_wr32(dev, 0x00b394, 0x00000000);
148 nv_wr32(dev, 0x00b398, 0x00000000);
149 nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
150
151 nv_wr32(dev, 0x00b100, 0xffffffff);
152 nv_wr32(dev, 0x00b140, 0xffffffff);
153
154 if (!nv_wait(dev, 0x00b200, 0x00000001, 0x00000000)) {
155 NV_ERROR(dev, "PMPEG init: 0x%08x\n", nv_rd32(dev, 0x00b200));
156 return -EBUSY;
157 }
158
159 return 0;
160 }
161
162 static int
nv50_mpeg_fini(struct drm_device * dev,int engine,bool suspend)163 nv50_mpeg_fini(struct drm_device *dev, int engine, bool suspend)
164 {
165 /*XXX: context save for s/r */
166 nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
167 nv_wr32(dev, 0x00b140, 0x00000000);
168 return 0;
169 }
170
171 static void
nv50_mpeg_isr(struct drm_device * dev)172 nv50_mpeg_isr(struct drm_device *dev)
173 {
174 u32 stat = nv_rd32(dev, 0x00b100);
175 u32 type = nv_rd32(dev, 0x00b230);
176 u32 mthd = nv_rd32(dev, 0x00b234);
177 u32 data = nv_rd32(dev, 0x00b238);
178 u32 show = stat;
179
180 if (stat & 0x01000000) {
181 /* happens on initial binding of the object */
182 if (type == 0x00000020 && mthd == 0x0000) {
183 nv_wr32(dev, 0x00b308, 0x00000100);
184 show &= ~0x01000000;
185 }
186 }
187
188 if (show && nouveau_ratelimit()) {
189 NV_INFO(dev, "PMPEG - 0x%08x 0x%08x 0x%08x 0x%08x\n",
190 stat, type, mthd, data);
191 }
192
193 nv_wr32(dev, 0x00b100, stat);
194 nv_wr32(dev, 0x00b230, 0x00000001);
195 nv50_fb_vm_trap(dev, 1);
196 }
197
198 static void
nv50_vpe_isr(struct drm_device * dev)199 nv50_vpe_isr(struct drm_device *dev)
200 {
201 if (nv_rd32(dev, 0x00b100))
202 nv50_mpeg_isr(dev);
203
204 if (nv_rd32(dev, 0x00b800)) {
205 u32 stat = nv_rd32(dev, 0x00b800);
206 NV_INFO(dev, "PMSRCH: 0x%08x\n", stat);
207 nv_wr32(dev, 0xb800, stat);
208 }
209 }
210
211 static void
nv50_mpeg_destroy(struct drm_device * dev,int engine)212 nv50_mpeg_destroy(struct drm_device *dev, int engine)
213 {
214 struct nv50_mpeg_engine *pmpeg = nv_engine(dev, engine);
215
216 nouveau_irq_unregister(dev, 0);
217
218 NVOBJ_ENGINE_DEL(dev, MPEG);
219 kfree(pmpeg);
220 }
221
222 int
nv50_mpeg_create(struct drm_device * dev)223 nv50_mpeg_create(struct drm_device *dev)
224 {
225 struct drm_nouveau_private *dev_priv = dev->dev_private;
226 struct nv50_mpeg_engine *pmpeg;
227
228 pmpeg = kzalloc(sizeof(*pmpeg), GFP_KERNEL);
229 if (!pmpeg)
230 return -ENOMEM;
231
232 pmpeg->base.destroy = nv50_mpeg_destroy;
233 pmpeg->base.init = nv50_mpeg_init;
234 pmpeg->base.fini = nv50_mpeg_fini;
235 pmpeg->base.context_new = nv50_mpeg_context_new;
236 pmpeg->base.context_del = nv50_mpeg_context_del;
237 pmpeg->base.object_new = nv50_mpeg_object_new;
238 pmpeg->base.tlb_flush = nv50_mpeg_tlb_flush;
239
240 if (dev_priv->chipset == 0x50) {
241 nouveau_irq_register(dev, 0, nv50_vpe_isr);
242 NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
243 NVOBJ_CLASS(dev, 0x3174, MPEG);
244 #if 0
245 NVOBJ_ENGINE_ADD(dev, ME, &pme->base);
246 NVOBJ_CLASS(dev, 0x4075, ME);
247 #endif
248 } else {
249 nouveau_irq_register(dev, 0, nv50_mpeg_isr);
250 NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
251 NVOBJ_CLASS(dev, 0x8274, MPEG);
252 }
253
254 return 0;
255
256 }
257