1 /* 2 * Copyright (c) 2010 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _NICPCI_H 18 #define _NICPCI_H 19 20 #if defined(BCMSDIO) || (defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)) 21 #define pcicore_find_pci_capability(a, b, c, d) (0) 22 #define pcie_readreg(a, b, c, d) (0) 23 #define pcie_writereg(a, b, c, d, e) (0) 24 25 #define pcie_clkreq(a, b, c) (0) 26 #define pcie_lcreg(a, b, c) (0) 27 28 #define pcicore_init(a, b, c) (0x0dadbeef) 29 #define pcicore_deinit(a) do { } while (0) 30 #define pcicore_attach(a, b, c) do { } while (0) 31 #define pcicore_hwup(a) do { } while (0) 32 #define pcicore_up(a, b) do { } while (0) 33 #define pcicore_sleep(a) do { } while (0) 34 #define pcicore_down(a, b) do { } while (0) 35 36 #define pcie_war_ovr_aspm_update(a, b) do { } while (0) 37 38 #define pcicore_pcieserdesreg(a, b, c, d, e) (0) 39 #define pcicore_pciereg(a, b, c, d, e) (0) 40 41 #define pcicore_pmecap_fast(a) (false) 42 #define pcicore_pmeen(a) do { } while (0) 43 #define pcicore_pmeclr(a) do { } while (0) 44 #define pcicore_pmestat(a) (false) 45 #else 46 struct sbpcieregs; 47 48 extern u8 pcicore_find_pci_capability(void *dev, u8 req_cap_id, 49 unsigned char *buf, u32 *buflen); 50 extern uint pcie_readreg(struct sbpcieregs *pcieregs, 51 uint addrtype, uint offset); 52 extern uint pcie_writereg(struct sbpcieregs *pcieregs, 53 uint addrtype, uint offset, uint val); 54 55 extern u8 pcie_clkreq(void *pch, u32 mask, u32 val); 56 extern u32 pcie_lcreg(void *pch, u32 mask, u32 val); 57 58 extern void *pcicore_init(si_t *sih, void *pdev, void *regs); 59 extern void pcicore_deinit(void *pch); 60 extern void pcicore_attach(void *pch, char *pvars, int state); 61 extern void pcicore_hwup(void *pch); 62 extern void pcicore_up(void *pch, int state); 63 extern void pcicore_sleep(void *pch); 64 extern void pcicore_down(void *pch, int state); 65 66 extern void pcie_war_ovr_aspm_update(void *pch, u8 aspm); 67 extern u32 pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset, 68 u32 mask, u32 val); 69 70 extern u32 pcicore_pciereg(void *pch, u32 offset, u32 mask, 71 u32 val, uint type); 72 73 extern bool pcicore_pmecap_fast(void *pch); 74 extern void pcicore_pmeen(void *pch); 75 extern void pcicore_pmeclr(void *pch); 76 extern bool pcicore_pmestat(void *pch); 77 #endif /* defined(BCMSDIO)||(defined(BCMBUSTYPE) && (BCMBUSTYPE==SI_BUS)) */ 78 79 #endif /* _NICPCI_H */ 80