1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Mediated virtual PCI serial host device driver
4 *
5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
6 * Author: Neo Jia <cjia@nvidia.com>
7 * Kirti Wankhede <kwankhede@nvidia.com>
8 *
9 * Sample driver that creates mdev device that simulates serial port over PCI
10 * card.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/fs.h>
17 #include <linux/poll.h>
18 #include <linux/slab.h>
19 #include <linux/cdev.h>
20 #include <linux/sched.h>
21 #include <linux/wait.h>
22 #include <linux/vfio.h>
23 #include <linux/iommu.h>
24 #include <linux/sysfs.h>
25 #include <linux/ctype.h>
26 #include <linux/file.h>
27 #include <linux/mdev.h>
28 #include <linux/pci.h>
29 #include <linux/serial.h>
30 #include <uapi/linux/serial_reg.h>
31 #include <linux/eventfd.h>
32 /*
33 * #defines
34 */
35
36 #define VERSION_STRING "0.1"
37 #define DRIVER_AUTHOR "NVIDIA Corporation"
38
39 #define MTTY_CLASS_NAME "mtty"
40
41 #define MTTY_NAME "mtty"
42
43 #define MTTY_STRING_LEN 16
44
45 #define MTTY_CONFIG_SPACE_SIZE 0xff
46 #define MTTY_IO_BAR_SIZE 0x8
47 #define MTTY_MMIO_BAR_SIZE 0x100000
48
49 #define STORE_LE16(addr, val) (*(u16 *)addr = val)
50 #define STORE_LE32(addr, val) (*(u32 *)addr = val)
51
52 #define MAX_FIFO_SIZE 16
53
54 #define CIRCULAR_BUF_INC_IDX(idx) (idx = (idx + 1) & (MAX_FIFO_SIZE - 1))
55
56 #define MTTY_VFIO_PCI_OFFSET_SHIFT 40
57
58 #define MTTY_VFIO_PCI_OFFSET_TO_INDEX(off) (off >> MTTY_VFIO_PCI_OFFSET_SHIFT)
59 #define MTTY_VFIO_PCI_INDEX_TO_OFFSET(index) \
60 ((u64)(index) << MTTY_VFIO_PCI_OFFSET_SHIFT)
61 #define MTTY_VFIO_PCI_OFFSET_MASK \
62 (((u64)(1) << MTTY_VFIO_PCI_OFFSET_SHIFT) - 1)
63 #define MAX_MTTYS 24
64
65 /*
66 * Global Structures
67 */
68
69 static struct mtty_dev {
70 dev_t vd_devt;
71 struct class *vd_class;
72 struct cdev vd_cdev;
73 struct idr vd_idr;
74 struct device dev;
75 struct mdev_parent parent;
76 } mtty_dev;
77
78 struct mdev_region_info {
79 u64 start;
80 u64 phys_start;
81 u32 size;
82 u64 vfio_offset;
83 };
84
85 #if defined(DEBUG_REGS)
86 static const char *wr_reg[] = {
87 "TX",
88 "IER",
89 "FCR",
90 "LCR",
91 "MCR",
92 "LSR",
93 "MSR",
94 "SCR"
95 };
96
97 static const char *rd_reg[] = {
98 "RX",
99 "IER",
100 "IIR",
101 "LCR",
102 "MCR",
103 "LSR",
104 "MSR",
105 "SCR"
106 };
107 #endif
108
109 /* loop back buffer */
110 struct rxtx {
111 u8 fifo[MAX_FIFO_SIZE];
112 u8 head, tail;
113 u8 count;
114 };
115
116 struct serial_port {
117 u8 uart_reg[8]; /* 8 registers */
118 struct rxtx rxtx; /* loop back buffer */
119 bool dlab;
120 bool overrun;
121 u16 divisor;
122 u8 fcr; /* FIFO control register */
123 u8 max_fifo_size;
124 u8 intr_trigger_level; /* interrupt trigger level */
125 };
126
127 /* State of each mdev device */
128 struct mdev_state {
129 struct vfio_device vdev;
130 int irq_fd;
131 struct eventfd_ctx *intx_evtfd;
132 struct eventfd_ctx *msi_evtfd;
133 int irq_index;
134 u8 *vconfig;
135 struct mutex ops_lock;
136 struct mdev_device *mdev;
137 struct mdev_region_info region_info[VFIO_PCI_NUM_REGIONS];
138 u32 bar_mask[VFIO_PCI_NUM_REGIONS];
139 struct list_head next;
140 struct serial_port s[2];
141 struct mutex rxtx_lock;
142 struct vfio_device_info dev_info;
143 int nr_ports;
144 };
145
146 static struct mtty_type {
147 struct mdev_type type;
148 int nr_ports;
149 } mtty_types[2] = {
150 { .nr_ports = 1, .type.sysfs_name = "1",
151 .type.pretty_name = "Single port serial" },
152 { .nr_ports = 2, .type.sysfs_name = "2",
153 .type.pretty_name = "Dual port serial" },
154 };
155
156 static struct mdev_type *mtty_mdev_types[] = {
157 &mtty_types[0].type,
158 &mtty_types[1].type,
159 };
160
161 static atomic_t mdev_avail_ports = ATOMIC_INIT(MAX_MTTYS);
162
163 static const struct file_operations vd_fops = {
164 .owner = THIS_MODULE,
165 };
166
167 static const struct vfio_device_ops mtty_dev_ops;
168
169 /* function prototypes */
170
171 static int mtty_trigger_interrupt(struct mdev_state *mdev_state);
172
173 /* Helper functions */
174
dump_buffer(u8 * buf,uint32_t count)175 static void dump_buffer(u8 *buf, uint32_t count)
176 {
177 #if defined(DEBUG)
178 int i;
179
180 pr_info("Buffer:\n");
181 for (i = 0; i < count; i++) {
182 pr_info("%2x ", *(buf + i));
183 if ((i + 1) % 16 == 0)
184 pr_info("\n");
185 }
186 #endif
187 }
188
mtty_create_config_space(struct mdev_state * mdev_state)189 static void mtty_create_config_space(struct mdev_state *mdev_state)
190 {
191 /* PCI dev ID */
192 STORE_LE32((u32 *) &mdev_state->vconfig[0x0], 0x32534348);
193
194 /* Control: I/O+, Mem-, BusMaster- */
195 STORE_LE16((u16 *) &mdev_state->vconfig[0x4], 0x0001);
196
197 /* Status: capabilities list absent */
198 STORE_LE16((u16 *) &mdev_state->vconfig[0x6], 0x0200);
199
200 /* Rev ID */
201 mdev_state->vconfig[0x8] = 0x10;
202
203 /* programming interface class : 16550-compatible serial controller */
204 mdev_state->vconfig[0x9] = 0x02;
205
206 /* Sub class : 00 */
207 mdev_state->vconfig[0xa] = 0x00;
208
209 /* Base class : Simple Communication controllers */
210 mdev_state->vconfig[0xb] = 0x07;
211
212 /* base address registers */
213 /* BAR0: IO space */
214 STORE_LE32((u32 *) &mdev_state->vconfig[0x10], 0x000001);
215 mdev_state->bar_mask[0] = ~(MTTY_IO_BAR_SIZE) + 1;
216
217 if (mdev_state->nr_ports == 2) {
218 /* BAR1: IO space */
219 STORE_LE32((u32 *) &mdev_state->vconfig[0x14], 0x000001);
220 mdev_state->bar_mask[1] = ~(MTTY_IO_BAR_SIZE) + 1;
221 }
222
223 /* Subsystem ID */
224 STORE_LE32((u32 *) &mdev_state->vconfig[0x2c], 0x32534348);
225
226 mdev_state->vconfig[0x34] = 0x00; /* Cap Ptr */
227 mdev_state->vconfig[0x3d] = 0x01; /* interrupt pin (INTA#) */
228
229 /* Vendor specific data */
230 mdev_state->vconfig[0x40] = 0x23;
231 mdev_state->vconfig[0x43] = 0x80;
232 mdev_state->vconfig[0x44] = 0x23;
233 mdev_state->vconfig[0x48] = 0x23;
234 mdev_state->vconfig[0x4c] = 0x23;
235
236 mdev_state->vconfig[0x60] = 0x50;
237 mdev_state->vconfig[0x61] = 0x43;
238 mdev_state->vconfig[0x62] = 0x49;
239 mdev_state->vconfig[0x63] = 0x20;
240 mdev_state->vconfig[0x64] = 0x53;
241 mdev_state->vconfig[0x65] = 0x65;
242 mdev_state->vconfig[0x66] = 0x72;
243 mdev_state->vconfig[0x67] = 0x69;
244 mdev_state->vconfig[0x68] = 0x61;
245 mdev_state->vconfig[0x69] = 0x6c;
246 mdev_state->vconfig[0x6a] = 0x2f;
247 mdev_state->vconfig[0x6b] = 0x55;
248 mdev_state->vconfig[0x6c] = 0x41;
249 mdev_state->vconfig[0x6d] = 0x52;
250 mdev_state->vconfig[0x6e] = 0x54;
251 }
252
handle_pci_cfg_write(struct mdev_state * mdev_state,u16 offset,u8 * buf,u32 count)253 static void handle_pci_cfg_write(struct mdev_state *mdev_state, u16 offset,
254 u8 *buf, u32 count)
255 {
256 u32 cfg_addr, bar_mask, bar_index = 0;
257
258 switch (offset) {
259 case 0x04: /* device control */
260 case 0x06: /* device status */
261 /* do nothing */
262 break;
263 case 0x3c: /* interrupt line */
264 mdev_state->vconfig[0x3c] = buf[0];
265 break;
266 case 0x3d:
267 /*
268 * Interrupt Pin is hardwired to INTA.
269 * This field is write protected by hardware
270 */
271 break;
272 case 0x10: /* BAR0 */
273 case 0x14: /* BAR1 */
274 if (offset == 0x10)
275 bar_index = 0;
276 else if (offset == 0x14)
277 bar_index = 1;
278
279 if ((mdev_state->nr_ports == 1) && (bar_index == 1)) {
280 STORE_LE32(&mdev_state->vconfig[offset], 0);
281 break;
282 }
283
284 cfg_addr = *(u32 *)buf;
285 pr_info("BAR%d addr 0x%x\n", bar_index, cfg_addr);
286
287 if (cfg_addr == 0xffffffff) {
288 bar_mask = mdev_state->bar_mask[bar_index];
289 cfg_addr = (cfg_addr & bar_mask);
290 }
291
292 cfg_addr |= (mdev_state->vconfig[offset] & 0x3ul);
293 STORE_LE32(&mdev_state->vconfig[offset], cfg_addr);
294 break;
295 case 0x18: /* BAR2 */
296 case 0x1c: /* BAR3 */
297 case 0x20: /* BAR4 */
298 STORE_LE32(&mdev_state->vconfig[offset], 0);
299 break;
300 default:
301 pr_info("PCI config write @0x%x of %d bytes not handled\n",
302 offset, count);
303 break;
304 }
305 }
306
handle_bar_write(unsigned int index,struct mdev_state * mdev_state,u16 offset,u8 * buf,u32 count)307 static void handle_bar_write(unsigned int index, struct mdev_state *mdev_state,
308 u16 offset, u8 *buf, u32 count)
309 {
310 u8 data = *buf;
311
312 /* Handle data written by guest */
313 switch (offset) {
314 case UART_TX:
315 /* if DLAB set, data is LSB of divisor */
316 if (mdev_state->s[index].dlab) {
317 mdev_state->s[index].divisor |= data;
318 break;
319 }
320
321 mutex_lock(&mdev_state->rxtx_lock);
322
323 /* save in TX buffer */
324 if (mdev_state->s[index].rxtx.count <
325 mdev_state->s[index].max_fifo_size) {
326 mdev_state->s[index].rxtx.fifo[
327 mdev_state->s[index].rxtx.head] = data;
328 mdev_state->s[index].rxtx.count++;
329 CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.head);
330 mdev_state->s[index].overrun = false;
331
332 /*
333 * Trigger interrupt if receive data interrupt is
334 * enabled and fifo reached trigger level
335 */
336 if ((mdev_state->s[index].uart_reg[UART_IER] &
337 UART_IER_RDI) &&
338 (mdev_state->s[index].rxtx.count ==
339 mdev_state->s[index].intr_trigger_level)) {
340 /* trigger interrupt */
341 #if defined(DEBUG_INTR)
342 pr_err("Serial port %d: Fifo level trigger\n",
343 index);
344 #endif
345 mtty_trigger_interrupt(mdev_state);
346 }
347 } else {
348 #if defined(DEBUG_INTR)
349 pr_err("Serial port %d: Buffer Overflow\n", index);
350 #endif
351 mdev_state->s[index].overrun = true;
352
353 /*
354 * Trigger interrupt if receiver line status interrupt
355 * is enabled
356 */
357 if (mdev_state->s[index].uart_reg[UART_IER] &
358 UART_IER_RLSI)
359 mtty_trigger_interrupt(mdev_state);
360 }
361 mutex_unlock(&mdev_state->rxtx_lock);
362 break;
363
364 case UART_IER:
365 /* if DLAB set, data is MSB of divisor */
366 if (mdev_state->s[index].dlab)
367 mdev_state->s[index].divisor |= (u16)data << 8;
368 else {
369 mdev_state->s[index].uart_reg[offset] = data;
370 mutex_lock(&mdev_state->rxtx_lock);
371 if ((data & UART_IER_THRI) &&
372 (mdev_state->s[index].rxtx.head ==
373 mdev_state->s[index].rxtx.tail)) {
374 #if defined(DEBUG_INTR)
375 pr_err("Serial port %d: IER_THRI write\n",
376 index);
377 #endif
378 mtty_trigger_interrupt(mdev_state);
379 }
380
381 mutex_unlock(&mdev_state->rxtx_lock);
382 }
383
384 break;
385
386 case UART_FCR:
387 mdev_state->s[index].fcr = data;
388
389 mutex_lock(&mdev_state->rxtx_lock);
390 if (data & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT)) {
391 /* clear loop back FIFO */
392 mdev_state->s[index].rxtx.count = 0;
393 mdev_state->s[index].rxtx.head = 0;
394 mdev_state->s[index].rxtx.tail = 0;
395 }
396 mutex_unlock(&mdev_state->rxtx_lock);
397
398 switch (data & UART_FCR_TRIGGER_MASK) {
399 case UART_FCR_TRIGGER_1:
400 mdev_state->s[index].intr_trigger_level = 1;
401 break;
402
403 case UART_FCR_TRIGGER_4:
404 mdev_state->s[index].intr_trigger_level = 4;
405 break;
406
407 case UART_FCR_TRIGGER_8:
408 mdev_state->s[index].intr_trigger_level = 8;
409 break;
410
411 case UART_FCR_TRIGGER_14:
412 mdev_state->s[index].intr_trigger_level = 14;
413 break;
414 }
415
416 /*
417 * Set trigger level to 1 otherwise or implement timer with
418 * timeout of 4 characters and on expiring that timer set
419 * Recevice data timeout in IIR register
420 */
421 mdev_state->s[index].intr_trigger_level = 1;
422 if (data & UART_FCR_ENABLE_FIFO)
423 mdev_state->s[index].max_fifo_size = MAX_FIFO_SIZE;
424 else {
425 mdev_state->s[index].max_fifo_size = 1;
426 mdev_state->s[index].intr_trigger_level = 1;
427 }
428
429 break;
430
431 case UART_LCR:
432 if (data & UART_LCR_DLAB) {
433 mdev_state->s[index].dlab = true;
434 mdev_state->s[index].divisor = 0;
435 } else
436 mdev_state->s[index].dlab = false;
437
438 mdev_state->s[index].uart_reg[offset] = data;
439 break;
440
441 case UART_MCR:
442 mdev_state->s[index].uart_reg[offset] = data;
443
444 if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
445 (data & UART_MCR_OUT2)) {
446 #if defined(DEBUG_INTR)
447 pr_err("Serial port %d: MCR_OUT2 write\n", index);
448 #endif
449 mtty_trigger_interrupt(mdev_state);
450 }
451
452 if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
453 (data & (UART_MCR_RTS | UART_MCR_DTR))) {
454 #if defined(DEBUG_INTR)
455 pr_err("Serial port %d: MCR RTS/DTR write\n", index);
456 #endif
457 mtty_trigger_interrupt(mdev_state);
458 }
459 break;
460
461 case UART_LSR:
462 case UART_MSR:
463 /* do nothing */
464 break;
465
466 case UART_SCR:
467 mdev_state->s[index].uart_reg[offset] = data;
468 break;
469
470 default:
471 break;
472 }
473 }
474
handle_bar_read(unsigned int index,struct mdev_state * mdev_state,u16 offset,u8 * buf,u32 count)475 static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state,
476 u16 offset, u8 *buf, u32 count)
477 {
478 /* Handle read requests by guest */
479 switch (offset) {
480 case UART_RX:
481 /* if DLAB set, data is LSB of divisor */
482 if (mdev_state->s[index].dlab) {
483 *buf = (u8)mdev_state->s[index].divisor;
484 break;
485 }
486
487 mutex_lock(&mdev_state->rxtx_lock);
488 /* return data in tx buffer */
489 if (mdev_state->s[index].rxtx.head !=
490 mdev_state->s[index].rxtx.tail) {
491 *buf = mdev_state->s[index].rxtx.fifo[
492 mdev_state->s[index].rxtx.tail];
493 mdev_state->s[index].rxtx.count--;
494 CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.tail);
495 }
496
497 if (mdev_state->s[index].rxtx.head ==
498 mdev_state->s[index].rxtx.tail) {
499 /*
500 * Trigger interrupt if tx buffer empty interrupt is
501 * enabled and fifo is empty
502 */
503 #if defined(DEBUG_INTR)
504 pr_err("Serial port %d: Buffer Empty\n", index);
505 #endif
506 if (mdev_state->s[index].uart_reg[UART_IER] &
507 UART_IER_THRI)
508 mtty_trigger_interrupt(mdev_state);
509 }
510 mutex_unlock(&mdev_state->rxtx_lock);
511
512 break;
513
514 case UART_IER:
515 if (mdev_state->s[index].dlab) {
516 *buf = (u8)(mdev_state->s[index].divisor >> 8);
517 break;
518 }
519 *buf = mdev_state->s[index].uart_reg[offset] & 0x0f;
520 break;
521
522 case UART_IIR:
523 {
524 u8 ier = mdev_state->s[index].uart_reg[UART_IER];
525 *buf = 0;
526
527 mutex_lock(&mdev_state->rxtx_lock);
528 /* Interrupt priority 1: Parity, overrun, framing or break */
529 if ((ier & UART_IER_RLSI) && mdev_state->s[index].overrun)
530 *buf |= UART_IIR_RLSI;
531
532 /* Interrupt priority 2: Fifo trigger level reached */
533 if ((ier & UART_IER_RDI) &&
534 (mdev_state->s[index].rxtx.count >=
535 mdev_state->s[index].intr_trigger_level))
536 *buf |= UART_IIR_RDI;
537
538 /* Interrupt priotiry 3: transmitter holding register empty */
539 if ((ier & UART_IER_THRI) &&
540 (mdev_state->s[index].rxtx.head ==
541 mdev_state->s[index].rxtx.tail))
542 *buf |= UART_IIR_THRI;
543
544 /* Interrupt priotiry 4: Modem status: CTS, DSR, RI or DCD */
545 if ((ier & UART_IER_MSI) &&
546 (mdev_state->s[index].uart_reg[UART_MCR] &
547 (UART_MCR_RTS | UART_MCR_DTR)))
548 *buf |= UART_IIR_MSI;
549
550 /* bit0: 0=> interrupt pending, 1=> no interrupt is pending */
551 if (*buf == 0)
552 *buf = UART_IIR_NO_INT;
553
554 /* set bit 6 & 7 to be 16550 compatible */
555 *buf |= 0xC0;
556 mutex_unlock(&mdev_state->rxtx_lock);
557 }
558 break;
559
560 case UART_LCR:
561 case UART_MCR:
562 *buf = mdev_state->s[index].uart_reg[offset];
563 break;
564
565 case UART_LSR:
566 {
567 u8 lsr = 0;
568
569 mutex_lock(&mdev_state->rxtx_lock);
570 /* atleast one char in FIFO */
571 if (mdev_state->s[index].rxtx.head !=
572 mdev_state->s[index].rxtx.tail)
573 lsr |= UART_LSR_DR;
574
575 /* if FIFO overrun */
576 if (mdev_state->s[index].overrun)
577 lsr |= UART_LSR_OE;
578
579 /* transmit FIFO empty and tramsitter empty */
580 if (mdev_state->s[index].rxtx.head ==
581 mdev_state->s[index].rxtx.tail)
582 lsr |= UART_LSR_TEMT | UART_LSR_THRE;
583
584 mutex_unlock(&mdev_state->rxtx_lock);
585 *buf = lsr;
586 break;
587 }
588 case UART_MSR:
589 *buf = UART_MSR_DSR | UART_MSR_DDSR | UART_MSR_DCD;
590
591 mutex_lock(&mdev_state->rxtx_lock);
592 /* if AFE is 1 and FIFO have space, set CTS bit */
593 if (mdev_state->s[index].uart_reg[UART_MCR] &
594 UART_MCR_AFE) {
595 if (mdev_state->s[index].rxtx.count <
596 mdev_state->s[index].max_fifo_size)
597 *buf |= UART_MSR_CTS | UART_MSR_DCTS;
598 } else
599 *buf |= UART_MSR_CTS | UART_MSR_DCTS;
600 mutex_unlock(&mdev_state->rxtx_lock);
601
602 break;
603
604 case UART_SCR:
605 *buf = mdev_state->s[index].uart_reg[offset];
606 break;
607
608 default:
609 break;
610 }
611 }
612
mdev_read_base(struct mdev_state * mdev_state)613 static void mdev_read_base(struct mdev_state *mdev_state)
614 {
615 int index, pos;
616 u32 start_lo, start_hi;
617 u32 mem_type;
618
619 pos = PCI_BASE_ADDRESS_0;
620
621 for (index = 0; index <= VFIO_PCI_BAR5_REGION_INDEX; index++) {
622
623 if (!mdev_state->region_info[index].size)
624 continue;
625
626 start_lo = (*(u32 *)(mdev_state->vconfig + pos)) &
627 PCI_BASE_ADDRESS_MEM_MASK;
628 mem_type = (*(u32 *)(mdev_state->vconfig + pos)) &
629 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
630
631 switch (mem_type) {
632 case PCI_BASE_ADDRESS_MEM_TYPE_64:
633 start_hi = (*(u32 *)(mdev_state->vconfig + pos + 4));
634 pos += 4;
635 break;
636 case PCI_BASE_ADDRESS_MEM_TYPE_32:
637 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
638 /* 1M mem BAR treated as 32-bit BAR */
639 default:
640 /* mem unknown type treated as 32-bit BAR */
641 start_hi = 0;
642 break;
643 }
644 pos += 4;
645 mdev_state->region_info[index].start = ((u64)start_hi << 32) |
646 start_lo;
647 }
648 }
649
mdev_access(struct mdev_state * mdev_state,u8 * buf,size_t count,loff_t pos,bool is_write)650 static ssize_t mdev_access(struct mdev_state *mdev_state, u8 *buf, size_t count,
651 loff_t pos, bool is_write)
652 {
653 unsigned int index;
654 loff_t offset;
655 int ret = 0;
656
657 if (!buf)
658 return -EINVAL;
659
660 mutex_lock(&mdev_state->ops_lock);
661
662 index = MTTY_VFIO_PCI_OFFSET_TO_INDEX(pos);
663 offset = pos & MTTY_VFIO_PCI_OFFSET_MASK;
664 switch (index) {
665 case VFIO_PCI_CONFIG_REGION_INDEX:
666
667 #if defined(DEBUG)
668 pr_info("%s: PCI config space %s at offset 0x%llx\n",
669 __func__, is_write ? "write" : "read", offset);
670 #endif
671 if (is_write) {
672 dump_buffer(buf, count);
673 handle_pci_cfg_write(mdev_state, offset, buf, count);
674 } else {
675 memcpy(buf, (mdev_state->vconfig + offset), count);
676 dump_buffer(buf, count);
677 }
678
679 break;
680
681 case VFIO_PCI_BAR0_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX:
682 if (!mdev_state->region_info[index].start)
683 mdev_read_base(mdev_state);
684
685 if (is_write) {
686 dump_buffer(buf, count);
687
688 #if defined(DEBUG_REGS)
689 pr_info("%s: BAR%d WR @0x%llx %s val:0x%02x dlab:%d\n",
690 __func__, index, offset, wr_reg[offset],
691 *buf, mdev_state->s[index].dlab);
692 #endif
693 handle_bar_write(index, mdev_state, offset, buf, count);
694 } else {
695 handle_bar_read(index, mdev_state, offset, buf, count);
696 dump_buffer(buf, count);
697
698 #if defined(DEBUG_REGS)
699 pr_info("%s: BAR%d RD @0x%llx %s val:0x%02x dlab:%d\n",
700 __func__, index, offset, rd_reg[offset],
701 *buf, mdev_state->s[index].dlab);
702 #endif
703 }
704 break;
705
706 default:
707 ret = -1;
708 goto accessfailed;
709 }
710
711 ret = count;
712
713
714 accessfailed:
715 mutex_unlock(&mdev_state->ops_lock);
716
717 return ret;
718 }
719
mtty_init_dev(struct vfio_device * vdev)720 static int mtty_init_dev(struct vfio_device *vdev)
721 {
722 struct mdev_state *mdev_state =
723 container_of(vdev, struct mdev_state, vdev);
724 struct mdev_device *mdev = to_mdev_device(vdev->dev);
725 struct mtty_type *type =
726 container_of(mdev->type, struct mtty_type, type);
727 int avail_ports = atomic_read(&mdev_avail_ports);
728 int ret;
729
730 do {
731 if (avail_ports < type->nr_ports)
732 return -ENOSPC;
733 } while (!atomic_try_cmpxchg(&mdev_avail_ports,
734 &avail_ports,
735 avail_ports - type->nr_ports));
736
737 mdev_state->nr_ports = type->nr_ports;
738 mdev_state->irq_index = -1;
739 mdev_state->s[0].max_fifo_size = MAX_FIFO_SIZE;
740 mdev_state->s[1].max_fifo_size = MAX_FIFO_SIZE;
741 mutex_init(&mdev_state->rxtx_lock);
742
743 mdev_state->vconfig = kzalloc(MTTY_CONFIG_SPACE_SIZE, GFP_KERNEL);
744 if (!mdev_state->vconfig) {
745 ret = -ENOMEM;
746 goto err_nr_ports;
747 }
748
749 mutex_init(&mdev_state->ops_lock);
750 mdev_state->mdev = mdev;
751 mtty_create_config_space(mdev_state);
752 return 0;
753
754 err_nr_ports:
755 atomic_add(type->nr_ports, &mdev_avail_ports);
756 return ret;
757 }
758
mtty_probe(struct mdev_device * mdev)759 static int mtty_probe(struct mdev_device *mdev)
760 {
761 struct mdev_state *mdev_state;
762 int ret;
763
764 mdev_state = vfio_alloc_device(mdev_state, vdev, &mdev->dev,
765 &mtty_dev_ops);
766 if (IS_ERR(mdev_state))
767 return PTR_ERR(mdev_state);
768
769 ret = vfio_register_emulated_iommu_dev(&mdev_state->vdev);
770 if (ret)
771 goto err_put_vdev;
772 dev_set_drvdata(&mdev->dev, mdev_state);
773 return 0;
774
775 err_put_vdev:
776 vfio_put_device(&mdev_state->vdev);
777 return ret;
778 }
779
mtty_release_dev(struct vfio_device * vdev)780 static void mtty_release_dev(struct vfio_device *vdev)
781 {
782 struct mdev_state *mdev_state =
783 container_of(vdev, struct mdev_state, vdev);
784
785 atomic_add(mdev_state->nr_ports, &mdev_avail_ports);
786 kfree(mdev_state->vconfig);
787 vfio_free_device(vdev);
788 }
789
mtty_remove(struct mdev_device * mdev)790 static void mtty_remove(struct mdev_device *mdev)
791 {
792 struct mdev_state *mdev_state = dev_get_drvdata(&mdev->dev);
793
794 vfio_unregister_group_dev(&mdev_state->vdev);
795 vfio_put_device(&mdev_state->vdev);
796 }
797
mtty_reset(struct mdev_state * mdev_state)798 static int mtty_reset(struct mdev_state *mdev_state)
799 {
800 pr_info("%s: called\n", __func__);
801
802 return 0;
803 }
804
mtty_read(struct vfio_device * vdev,char __user * buf,size_t count,loff_t * ppos)805 static ssize_t mtty_read(struct vfio_device *vdev, char __user *buf,
806 size_t count, loff_t *ppos)
807 {
808 struct mdev_state *mdev_state =
809 container_of(vdev, struct mdev_state, vdev);
810 unsigned int done = 0;
811 int ret;
812
813 while (count) {
814 size_t filled;
815
816 if (count >= 4 && !(*ppos % 4)) {
817 u32 val;
818
819 ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
820 *ppos, false);
821 if (ret <= 0)
822 goto read_err;
823
824 if (copy_to_user(buf, &val, sizeof(val)))
825 goto read_err;
826
827 filled = 4;
828 } else if (count >= 2 && !(*ppos % 2)) {
829 u16 val;
830
831 ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
832 *ppos, false);
833 if (ret <= 0)
834 goto read_err;
835
836 if (copy_to_user(buf, &val, sizeof(val)))
837 goto read_err;
838
839 filled = 2;
840 } else {
841 u8 val;
842
843 ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
844 *ppos, false);
845 if (ret <= 0)
846 goto read_err;
847
848 if (copy_to_user(buf, &val, sizeof(val)))
849 goto read_err;
850
851 filled = 1;
852 }
853
854 count -= filled;
855 done += filled;
856 *ppos += filled;
857 buf += filled;
858 }
859
860 return done;
861
862 read_err:
863 return -EFAULT;
864 }
865
mtty_write(struct vfio_device * vdev,const char __user * buf,size_t count,loff_t * ppos)866 static ssize_t mtty_write(struct vfio_device *vdev, const char __user *buf,
867 size_t count, loff_t *ppos)
868 {
869 struct mdev_state *mdev_state =
870 container_of(vdev, struct mdev_state, vdev);
871 unsigned int done = 0;
872 int ret;
873
874 while (count) {
875 size_t filled;
876
877 if (count >= 4 && !(*ppos % 4)) {
878 u32 val;
879
880 if (copy_from_user(&val, buf, sizeof(val)))
881 goto write_err;
882
883 ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
884 *ppos, true);
885 if (ret <= 0)
886 goto write_err;
887
888 filled = 4;
889 } else if (count >= 2 && !(*ppos % 2)) {
890 u16 val;
891
892 if (copy_from_user(&val, buf, sizeof(val)))
893 goto write_err;
894
895 ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
896 *ppos, true);
897 if (ret <= 0)
898 goto write_err;
899
900 filled = 2;
901 } else {
902 u8 val;
903
904 if (copy_from_user(&val, buf, sizeof(val)))
905 goto write_err;
906
907 ret = mdev_access(mdev_state, (u8 *)&val, sizeof(val),
908 *ppos, true);
909 if (ret <= 0)
910 goto write_err;
911
912 filled = 1;
913 }
914 count -= filled;
915 done += filled;
916 *ppos += filled;
917 buf += filled;
918 }
919
920 return done;
921 write_err:
922 return -EFAULT;
923 }
924
mtty_set_irqs(struct mdev_state * mdev_state,uint32_t flags,unsigned int index,unsigned int start,unsigned int count,void * data)925 static int mtty_set_irqs(struct mdev_state *mdev_state, uint32_t flags,
926 unsigned int index, unsigned int start,
927 unsigned int count, void *data)
928 {
929 int ret = 0;
930
931 mutex_lock(&mdev_state->ops_lock);
932 switch (index) {
933 case VFIO_PCI_INTX_IRQ_INDEX:
934 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
935 case VFIO_IRQ_SET_ACTION_MASK:
936 case VFIO_IRQ_SET_ACTION_UNMASK:
937 break;
938 case VFIO_IRQ_SET_ACTION_TRIGGER:
939 {
940 if (flags & VFIO_IRQ_SET_DATA_NONE) {
941 pr_info("%s: disable INTx\n", __func__);
942 if (mdev_state->intx_evtfd)
943 eventfd_ctx_put(mdev_state->intx_evtfd);
944 break;
945 }
946
947 if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
948 int fd = *(int *)data;
949
950 if (fd > 0) {
951 struct eventfd_ctx *evt;
952
953 evt = eventfd_ctx_fdget(fd);
954 if (IS_ERR(evt)) {
955 ret = PTR_ERR(evt);
956 break;
957 }
958 mdev_state->intx_evtfd = evt;
959 mdev_state->irq_fd = fd;
960 mdev_state->irq_index = index;
961 break;
962 }
963 }
964 break;
965 }
966 }
967 break;
968 case VFIO_PCI_MSI_IRQ_INDEX:
969 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
970 case VFIO_IRQ_SET_ACTION_MASK:
971 case VFIO_IRQ_SET_ACTION_UNMASK:
972 break;
973 case VFIO_IRQ_SET_ACTION_TRIGGER:
974 if (flags & VFIO_IRQ_SET_DATA_NONE) {
975 if (mdev_state->msi_evtfd)
976 eventfd_ctx_put(mdev_state->msi_evtfd);
977 pr_info("%s: disable MSI\n", __func__);
978 mdev_state->irq_index = VFIO_PCI_INTX_IRQ_INDEX;
979 break;
980 }
981 if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
982 int fd = *(int *)data;
983 struct eventfd_ctx *evt;
984
985 if (fd <= 0)
986 break;
987
988 if (mdev_state->msi_evtfd)
989 break;
990
991 evt = eventfd_ctx_fdget(fd);
992 if (IS_ERR(evt)) {
993 ret = PTR_ERR(evt);
994 break;
995 }
996 mdev_state->msi_evtfd = evt;
997 mdev_state->irq_fd = fd;
998 mdev_state->irq_index = index;
999 }
1000 break;
1001 }
1002 break;
1003 case VFIO_PCI_MSIX_IRQ_INDEX:
1004 pr_info("%s: MSIX_IRQ\n", __func__);
1005 break;
1006 case VFIO_PCI_ERR_IRQ_INDEX:
1007 pr_info("%s: ERR_IRQ\n", __func__);
1008 break;
1009 case VFIO_PCI_REQ_IRQ_INDEX:
1010 pr_info("%s: REQ_IRQ\n", __func__);
1011 break;
1012 }
1013
1014 mutex_unlock(&mdev_state->ops_lock);
1015 return ret;
1016 }
1017
mtty_trigger_interrupt(struct mdev_state * mdev_state)1018 static int mtty_trigger_interrupt(struct mdev_state *mdev_state)
1019 {
1020 int ret = -1;
1021
1022 if ((mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX) &&
1023 (!mdev_state->msi_evtfd))
1024 return -EINVAL;
1025 else if ((mdev_state->irq_index == VFIO_PCI_INTX_IRQ_INDEX) &&
1026 (!mdev_state->intx_evtfd)) {
1027 pr_info("%s: Intr eventfd not found\n", __func__);
1028 return -EINVAL;
1029 }
1030
1031 if (mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX)
1032 ret = eventfd_signal(mdev_state->msi_evtfd, 1);
1033 else
1034 ret = eventfd_signal(mdev_state->intx_evtfd, 1);
1035
1036 #if defined(DEBUG_INTR)
1037 pr_info("Intx triggered\n");
1038 #endif
1039 if (ret != 1)
1040 pr_err("%s: eventfd signal failed (%d)\n", __func__, ret);
1041
1042 return ret;
1043 }
1044
mtty_get_region_info(struct mdev_state * mdev_state,struct vfio_region_info * region_info,u16 * cap_type_id,void ** cap_type)1045 static int mtty_get_region_info(struct mdev_state *mdev_state,
1046 struct vfio_region_info *region_info,
1047 u16 *cap_type_id, void **cap_type)
1048 {
1049 unsigned int size = 0;
1050 u32 bar_index;
1051
1052 bar_index = region_info->index;
1053 if (bar_index >= VFIO_PCI_NUM_REGIONS)
1054 return -EINVAL;
1055
1056 mutex_lock(&mdev_state->ops_lock);
1057
1058 switch (bar_index) {
1059 case VFIO_PCI_CONFIG_REGION_INDEX:
1060 size = MTTY_CONFIG_SPACE_SIZE;
1061 break;
1062 case VFIO_PCI_BAR0_REGION_INDEX:
1063 size = MTTY_IO_BAR_SIZE;
1064 break;
1065 case VFIO_PCI_BAR1_REGION_INDEX:
1066 if (mdev_state->nr_ports == 2)
1067 size = MTTY_IO_BAR_SIZE;
1068 break;
1069 default:
1070 size = 0;
1071 break;
1072 }
1073
1074 mdev_state->region_info[bar_index].size = size;
1075 mdev_state->region_info[bar_index].vfio_offset =
1076 MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
1077
1078 region_info->size = size;
1079 region_info->offset = MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
1080 region_info->flags = VFIO_REGION_INFO_FLAG_READ |
1081 VFIO_REGION_INFO_FLAG_WRITE;
1082 mutex_unlock(&mdev_state->ops_lock);
1083 return 0;
1084 }
1085
mtty_get_irq_info(struct vfio_irq_info * irq_info)1086 static int mtty_get_irq_info(struct vfio_irq_info *irq_info)
1087 {
1088 switch (irq_info->index) {
1089 case VFIO_PCI_INTX_IRQ_INDEX:
1090 case VFIO_PCI_MSI_IRQ_INDEX:
1091 case VFIO_PCI_REQ_IRQ_INDEX:
1092 break;
1093
1094 default:
1095 return -EINVAL;
1096 }
1097
1098 irq_info->flags = VFIO_IRQ_INFO_EVENTFD;
1099 irq_info->count = 1;
1100
1101 if (irq_info->index == VFIO_PCI_INTX_IRQ_INDEX)
1102 irq_info->flags |= (VFIO_IRQ_INFO_MASKABLE |
1103 VFIO_IRQ_INFO_AUTOMASKED);
1104 else
1105 irq_info->flags |= VFIO_IRQ_INFO_NORESIZE;
1106
1107 return 0;
1108 }
1109
mtty_get_device_info(struct vfio_device_info * dev_info)1110 static int mtty_get_device_info(struct vfio_device_info *dev_info)
1111 {
1112 dev_info->flags = VFIO_DEVICE_FLAGS_PCI;
1113 dev_info->num_regions = VFIO_PCI_NUM_REGIONS;
1114 dev_info->num_irqs = VFIO_PCI_NUM_IRQS;
1115
1116 return 0;
1117 }
1118
mtty_ioctl(struct vfio_device * vdev,unsigned int cmd,unsigned long arg)1119 static long mtty_ioctl(struct vfio_device *vdev, unsigned int cmd,
1120 unsigned long arg)
1121 {
1122 struct mdev_state *mdev_state =
1123 container_of(vdev, struct mdev_state, vdev);
1124 int ret = 0;
1125 unsigned long minsz;
1126
1127 switch (cmd) {
1128 case VFIO_DEVICE_GET_INFO:
1129 {
1130 struct vfio_device_info info;
1131
1132 minsz = offsetofend(struct vfio_device_info, num_irqs);
1133
1134 if (copy_from_user(&info, (void __user *)arg, minsz))
1135 return -EFAULT;
1136
1137 if (info.argsz < minsz)
1138 return -EINVAL;
1139
1140 ret = mtty_get_device_info(&info);
1141 if (ret)
1142 return ret;
1143
1144 memcpy(&mdev_state->dev_info, &info, sizeof(info));
1145
1146 if (copy_to_user((void __user *)arg, &info, minsz))
1147 return -EFAULT;
1148
1149 return 0;
1150 }
1151 case VFIO_DEVICE_GET_REGION_INFO:
1152 {
1153 struct vfio_region_info info;
1154 u16 cap_type_id = 0;
1155 void *cap_type = NULL;
1156
1157 minsz = offsetofend(struct vfio_region_info, offset);
1158
1159 if (copy_from_user(&info, (void __user *)arg, minsz))
1160 return -EFAULT;
1161
1162 if (info.argsz < minsz)
1163 return -EINVAL;
1164
1165 ret = mtty_get_region_info(mdev_state, &info, &cap_type_id,
1166 &cap_type);
1167 if (ret)
1168 return ret;
1169
1170 if (copy_to_user((void __user *)arg, &info, minsz))
1171 return -EFAULT;
1172
1173 return 0;
1174 }
1175
1176 case VFIO_DEVICE_GET_IRQ_INFO:
1177 {
1178 struct vfio_irq_info info;
1179
1180 minsz = offsetofend(struct vfio_irq_info, count);
1181
1182 if (copy_from_user(&info, (void __user *)arg, minsz))
1183 return -EFAULT;
1184
1185 if ((info.argsz < minsz) ||
1186 (info.index >= mdev_state->dev_info.num_irqs))
1187 return -EINVAL;
1188
1189 ret = mtty_get_irq_info(&info);
1190 if (ret)
1191 return ret;
1192
1193 if (copy_to_user((void __user *)arg, &info, minsz))
1194 return -EFAULT;
1195
1196 return 0;
1197 }
1198 case VFIO_DEVICE_SET_IRQS:
1199 {
1200 struct vfio_irq_set hdr;
1201 u8 *data = NULL, *ptr = NULL;
1202 size_t data_size = 0;
1203
1204 minsz = offsetofend(struct vfio_irq_set, count);
1205
1206 if (copy_from_user(&hdr, (void __user *)arg, minsz))
1207 return -EFAULT;
1208
1209 ret = vfio_set_irqs_validate_and_prepare(&hdr,
1210 mdev_state->dev_info.num_irqs,
1211 VFIO_PCI_NUM_IRQS,
1212 &data_size);
1213 if (ret)
1214 return ret;
1215
1216 if (data_size) {
1217 ptr = data = memdup_user((void __user *)(arg + minsz),
1218 data_size);
1219 if (IS_ERR(data))
1220 return PTR_ERR(data);
1221 }
1222
1223 ret = mtty_set_irqs(mdev_state, hdr.flags, hdr.index, hdr.start,
1224 hdr.count, data);
1225
1226 kfree(ptr);
1227 return ret;
1228 }
1229 case VFIO_DEVICE_RESET:
1230 return mtty_reset(mdev_state);
1231 }
1232 return -ENOTTY;
1233 }
1234
1235 static ssize_t
sample_mdev_dev_show(struct device * dev,struct device_attribute * attr,char * buf)1236 sample_mdev_dev_show(struct device *dev, struct device_attribute *attr,
1237 char *buf)
1238 {
1239 return sprintf(buf, "This is MDEV %s\n", dev_name(dev));
1240 }
1241
1242 static DEVICE_ATTR_RO(sample_mdev_dev);
1243
1244 static struct attribute *mdev_dev_attrs[] = {
1245 &dev_attr_sample_mdev_dev.attr,
1246 NULL,
1247 };
1248
1249 static const struct attribute_group mdev_dev_group = {
1250 .name = "vendor",
1251 .attrs = mdev_dev_attrs,
1252 };
1253
1254 static const struct attribute_group *mdev_dev_groups[] = {
1255 &mdev_dev_group,
1256 NULL,
1257 };
1258
mtty_get_available(struct mdev_type * mtype)1259 static unsigned int mtty_get_available(struct mdev_type *mtype)
1260 {
1261 struct mtty_type *type = container_of(mtype, struct mtty_type, type);
1262
1263 return atomic_read(&mdev_avail_ports) / type->nr_ports;
1264 }
1265
1266 static const struct vfio_device_ops mtty_dev_ops = {
1267 .name = "vfio-mtty",
1268 .init = mtty_init_dev,
1269 .release = mtty_release_dev,
1270 .read = mtty_read,
1271 .write = mtty_write,
1272 .ioctl = mtty_ioctl,
1273 };
1274
1275 static struct mdev_driver mtty_driver = {
1276 .device_api = VFIO_DEVICE_API_PCI_STRING,
1277 .driver = {
1278 .name = "mtty",
1279 .owner = THIS_MODULE,
1280 .mod_name = KBUILD_MODNAME,
1281 .dev_groups = mdev_dev_groups,
1282 },
1283 .probe = mtty_probe,
1284 .remove = mtty_remove,
1285 .get_available = mtty_get_available,
1286 };
1287
mtty_device_release(struct device * dev)1288 static void mtty_device_release(struct device *dev)
1289 {
1290 dev_dbg(dev, "mtty: released\n");
1291 }
1292
mtty_dev_init(void)1293 static int __init mtty_dev_init(void)
1294 {
1295 int ret = 0;
1296
1297 pr_info("mtty_dev: %s\n", __func__);
1298
1299 memset(&mtty_dev, 0, sizeof(mtty_dev));
1300
1301 idr_init(&mtty_dev.vd_idr);
1302
1303 ret = alloc_chrdev_region(&mtty_dev.vd_devt, 0, MINORMASK + 1,
1304 MTTY_NAME);
1305
1306 if (ret < 0) {
1307 pr_err("Error: failed to register mtty_dev, err:%d\n", ret);
1308 return ret;
1309 }
1310
1311 cdev_init(&mtty_dev.vd_cdev, &vd_fops);
1312 cdev_add(&mtty_dev.vd_cdev, mtty_dev.vd_devt, MINORMASK + 1);
1313
1314 pr_info("major_number:%d\n", MAJOR(mtty_dev.vd_devt));
1315
1316 ret = mdev_register_driver(&mtty_driver);
1317 if (ret)
1318 goto err_cdev;
1319
1320 mtty_dev.vd_class = class_create(THIS_MODULE, MTTY_CLASS_NAME);
1321
1322 if (IS_ERR(mtty_dev.vd_class)) {
1323 pr_err("Error: failed to register mtty_dev class\n");
1324 ret = PTR_ERR(mtty_dev.vd_class);
1325 goto err_driver;
1326 }
1327
1328 mtty_dev.dev.class = mtty_dev.vd_class;
1329 mtty_dev.dev.release = mtty_device_release;
1330 dev_set_name(&mtty_dev.dev, "%s", MTTY_NAME);
1331
1332 ret = device_register(&mtty_dev.dev);
1333 if (ret)
1334 goto err_class;
1335
1336 ret = mdev_register_parent(&mtty_dev.parent, &mtty_dev.dev,
1337 &mtty_driver, mtty_mdev_types,
1338 ARRAY_SIZE(mtty_mdev_types));
1339 if (ret)
1340 goto err_device;
1341 return 0;
1342
1343 err_device:
1344 device_unregister(&mtty_dev.dev);
1345 err_class:
1346 class_destroy(mtty_dev.vd_class);
1347 err_driver:
1348 mdev_unregister_driver(&mtty_driver);
1349 err_cdev:
1350 cdev_del(&mtty_dev.vd_cdev);
1351 unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK + 1);
1352 return ret;
1353 }
1354
mtty_dev_exit(void)1355 static void __exit mtty_dev_exit(void)
1356 {
1357 mtty_dev.dev.bus = NULL;
1358 mdev_unregister_parent(&mtty_dev.parent);
1359
1360 device_unregister(&mtty_dev.dev);
1361 idr_destroy(&mtty_dev.vd_idr);
1362 mdev_unregister_driver(&mtty_driver);
1363 cdev_del(&mtty_dev.vd_cdev);
1364 unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK + 1);
1365 class_destroy(mtty_dev.vd_class);
1366 mtty_dev.vd_class = NULL;
1367 pr_info("mtty_dev: Unloaded!\n");
1368 }
1369
1370 module_init(mtty_dev_init)
1371 module_exit(mtty_dev_exit)
1372
1373 MODULE_LICENSE("GPL v2");
1374 MODULE_INFO(supported, "Test driver that simulate serial port over PCI");
1375 MODULE_VERSION(VERSION_STRING);
1376 MODULE_AUTHOR(DRIVER_AUTHOR);
1377