1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8996.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8996.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,apr.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 clocks { 24 xo_board: xo-board { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <19200000>; 28 clock-output-names = "xo_board"; 29 }; 30 31 sleep_clk: sleep-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <32764>; 35 clock-output-names = "sleep_clk"; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 cpu-idle-states = <&CPU_SLEEP_0>; 49 capacity-dmips-mhz = <1024>; 50 clocks = <&kryocc 0>; 51 operating-points-v2 = <&cluster0_opp>; 52 #cooling-cells = <2>; 53 next-level-cache = <&L2_0>; 54 L2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 }; 58 }; 59 60 CPU1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "qcom,kryo"; 63 reg = <0x0 0x1>; 64 enable-method = "psci"; 65 cpu-idle-states = <&CPU_SLEEP_0>; 66 capacity-dmips-mhz = <1024>; 67 clocks = <&kryocc 0>; 68 operating-points-v2 = <&cluster0_opp>; 69 #cooling-cells = <2>; 70 next-level-cache = <&L2_0>; 71 }; 72 73 CPU2: cpu@100 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo"; 76 reg = <0x0 0x100>; 77 enable-method = "psci"; 78 cpu-idle-states = <&CPU_SLEEP_0>; 79 capacity-dmips-mhz = <1024>; 80 clocks = <&kryocc 1>; 81 operating-points-v2 = <&cluster1_opp>; 82 #cooling-cells = <2>; 83 next-level-cache = <&L2_1>; 84 L2_1: l2-cache { 85 compatible = "cache"; 86 cache-level = <2>; 87 }; 88 }; 89 90 CPU3: cpu@101 { 91 device_type = "cpu"; 92 compatible = "qcom,kryo"; 93 reg = <0x0 0x101>; 94 enable-method = "psci"; 95 cpu-idle-states = <&CPU_SLEEP_0>; 96 capacity-dmips-mhz = <1024>; 97 clocks = <&kryocc 1>; 98 operating-points-v2 = <&cluster1_opp>; 99 #cooling-cells = <2>; 100 next-level-cache = <&L2_1>; 101 }; 102 103 cpu-map { 104 cluster0 { 105 core0 { 106 cpu = <&CPU0>; 107 }; 108 109 core1 { 110 cpu = <&CPU1>; 111 }; 112 }; 113 114 cluster1 { 115 core0 { 116 cpu = <&CPU2>; 117 }; 118 119 core1 { 120 cpu = <&CPU3>; 121 }; 122 }; 123 }; 124 125 idle-states { 126 entry-method = "psci"; 127 128 CPU_SLEEP_0: cpu-sleep-0 { 129 compatible = "arm,idle-state"; 130 idle-state-name = "standalone-power-collapse"; 131 arm,psci-suspend-param = <0x00000004>; 132 entry-latency-us = <130>; 133 exit-latency-us = <80>; 134 min-residency-us = <300>; 135 }; 136 }; 137 }; 138 139 cluster0_opp: opp-table-cluster0 { 140 compatible = "operating-points-v2-kryo-cpu"; 141 nvmem-cells = <&speedbin_efuse>; 142 opp-shared; 143 144 /* Nominal fmax for now */ 145 opp-307200000 { 146 opp-hz = /bits/ 64 <307200000>; 147 opp-supported-hw = <0x7>; 148 clock-latency-ns = <200000>; 149 }; 150 opp-422400000 { 151 opp-hz = /bits/ 64 <422400000>; 152 opp-supported-hw = <0x7>; 153 clock-latency-ns = <200000>; 154 }; 155 opp-480000000 { 156 opp-hz = /bits/ 64 <480000000>; 157 opp-supported-hw = <0x7>; 158 clock-latency-ns = <200000>; 159 }; 160 opp-556800000 { 161 opp-hz = /bits/ 64 <556800000>; 162 opp-supported-hw = <0x7>; 163 clock-latency-ns = <200000>; 164 }; 165 opp-652800000 { 166 opp-hz = /bits/ 64 <652800000>; 167 opp-supported-hw = <0x7>; 168 clock-latency-ns = <200000>; 169 }; 170 opp-729600000 { 171 opp-hz = /bits/ 64 <729600000>; 172 opp-supported-hw = <0x7>; 173 clock-latency-ns = <200000>; 174 }; 175 opp-844800000 { 176 opp-hz = /bits/ 64 <844800000>; 177 opp-supported-hw = <0x7>; 178 clock-latency-ns = <200000>; 179 }; 180 opp-960000000 { 181 opp-hz = /bits/ 64 <960000000>; 182 opp-supported-hw = <0x7>; 183 clock-latency-ns = <200000>; 184 }; 185 opp-1036800000 { 186 opp-hz = /bits/ 64 <1036800000>; 187 opp-supported-hw = <0x7>; 188 clock-latency-ns = <200000>; 189 }; 190 opp-1113600000 { 191 opp-hz = /bits/ 64 <1113600000>; 192 opp-supported-hw = <0x7>; 193 clock-latency-ns = <200000>; 194 }; 195 opp-1190400000 { 196 opp-hz = /bits/ 64 <1190400000>; 197 opp-supported-hw = <0x7>; 198 clock-latency-ns = <200000>; 199 }; 200 opp-1228800000 { 201 opp-hz = /bits/ 64 <1228800000>; 202 opp-supported-hw = <0x7>; 203 clock-latency-ns = <200000>; 204 }; 205 opp-1324800000 { 206 opp-hz = /bits/ 64 <1324800000>; 207 opp-supported-hw = <0x5>; 208 clock-latency-ns = <200000>; 209 }; 210 opp-1363200000 { 211 opp-hz = /bits/ 64 <1363200000>; 212 opp-supported-hw = <0x2>; 213 clock-latency-ns = <200000>; 214 }; 215 opp-1401600000 { 216 opp-hz = /bits/ 64 <1401600000>; 217 opp-supported-hw = <0x5>; 218 clock-latency-ns = <200000>; 219 }; 220 opp-1478400000 { 221 opp-hz = /bits/ 64 <1478400000>; 222 opp-supported-hw = <0x1>; 223 clock-latency-ns = <200000>; 224 }; 225 opp-1497600000 { 226 opp-hz = /bits/ 64 <1497600000>; 227 opp-supported-hw = <0x04>; 228 clock-latency-ns = <200000>; 229 }; 230 opp-1593600000 { 231 opp-hz = /bits/ 64 <1593600000>; 232 opp-supported-hw = <0x1>; 233 clock-latency-ns = <200000>; 234 }; 235 }; 236 237 cluster1_opp: opp-table-cluster1 { 238 compatible = "operating-points-v2-kryo-cpu"; 239 nvmem-cells = <&speedbin_efuse>; 240 opp-shared; 241 242 /* Nominal fmax for now */ 243 opp-307200000 { 244 opp-hz = /bits/ 64 <307200000>; 245 opp-supported-hw = <0x7>; 246 clock-latency-ns = <200000>; 247 }; 248 opp-403200000 { 249 opp-hz = /bits/ 64 <403200000>; 250 opp-supported-hw = <0x7>; 251 clock-latency-ns = <200000>; 252 }; 253 opp-480000000 { 254 opp-hz = /bits/ 64 <480000000>; 255 opp-supported-hw = <0x7>; 256 clock-latency-ns = <200000>; 257 }; 258 opp-556800000 { 259 opp-hz = /bits/ 64 <556800000>; 260 opp-supported-hw = <0x7>; 261 clock-latency-ns = <200000>; 262 }; 263 opp-652800000 { 264 opp-hz = /bits/ 64 <652800000>; 265 opp-supported-hw = <0x7>; 266 clock-latency-ns = <200000>; 267 }; 268 opp-729600000 { 269 opp-hz = /bits/ 64 <729600000>; 270 opp-supported-hw = <0x7>; 271 clock-latency-ns = <200000>; 272 }; 273 opp-806400000 { 274 opp-hz = /bits/ 64 <806400000>; 275 opp-supported-hw = <0x7>; 276 clock-latency-ns = <200000>; 277 }; 278 opp-883200000 { 279 opp-hz = /bits/ 64 <883200000>; 280 opp-supported-hw = <0x7>; 281 clock-latency-ns = <200000>; 282 }; 283 opp-940800000 { 284 opp-hz = /bits/ 64 <940800000>; 285 opp-supported-hw = <0x7>; 286 clock-latency-ns = <200000>; 287 }; 288 opp-1036800000 { 289 opp-hz = /bits/ 64 <1036800000>; 290 opp-supported-hw = <0x7>; 291 clock-latency-ns = <200000>; 292 }; 293 opp-1113600000 { 294 opp-hz = /bits/ 64 <1113600000>; 295 opp-supported-hw = <0x7>; 296 clock-latency-ns = <200000>; 297 }; 298 opp-1190400000 { 299 opp-hz = /bits/ 64 <1190400000>; 300 opp-supported-hw = <0x7>; 301 clock-latency-ns = <200000>; 302 }; 303 opp-1248000000 { 304 opp-hz = /bits/ 64 <1248000000>; 305 opp-supported-hw = <0x7>; 306 clock-latency-ns = <200000>; 307 }; 308 opp-1324800000 { 309 opp-hz = /bits/ 64 <1324800000>; 310 opp-supported-hw = <0x7>; 311 clock-latency-ns = <200000>; 312 }; 313 opp-1401600000 { 314 opp-hz = /bits/ 64 <1401600000>; 315 opp-supported-hw = <0x7>; 316 clock-latency-ns = <200000>; 317 }; 318 opp-1478400000 { 319 opp-hz = /bits/ 64 <1478400000>; 320 opp-supported-hw = <0x7>; 321 clock-latency-ns = <200000>; 322 }; 323 opp-1555200000 { 324 opp-hz = /bits/ 64 <1555200000>; 325 opp-supported-hw = <0x7>; 326 clock-latency-ns = <200000>; 327 }; 328 opp-1632000000 { 329 opp-hz = /bits/ 64 <1632000000>; 330 opp-supported-hw = <0x7>; 331 clock-latency-ns = <200000>; 332 }; 333 opp-1708800000 { 334 opp-hz = /bits/ 64 <1708800000>; 335 opp-supported-hw = <0x7>; 336 clock-latency-ns = <200000>; 337 }; 338 opp-1785600000 { 339 opp-hz = /bits/ 64 <1785600000>; 340 opp-supported-hw = <0x7>; 341 clock-latency-ns = <200000>; 342 }; 343 opp-1804800000 { 344 opp-hz = /bits/ 64 <1804800000>; 345 opp-supported-hw = <0x6>; 346 clock-latency-ns = <200000>; 347 }; 348 opp-1824000000 { 349 opp-hz = /bits/ 64 <1824000000>; 350 opp-supported-hw = <0x1>; 351 clock-latency-ns = <200000>; 352 }; 353 opp-1900800000 { 354 opp-hz = /bits/ 64 <1900800000>; 355 opp-supported-hw = <0x4>; 356 clock-latency-ns = <200000>; 357 }; 358 opp-1920000000 { 359 opp-hz = /bits/ 64 <1920000000>; 360 opp-supported-hw = <0x1>; 361 clock-latency-ns = <200000>; 362 }; 363 opp-1996800000 { 364 opp-hz = /bits/ 64 <1996800000>; 365 opp-supported-hw = <0x1>; 366 clock-latency-ns = <200000>; 367 }; 368 opp-2073600000 { 369 opp-hz = /bits/ 64 <2073600000>; 370 opp-supported-hw = <0x1>; 371 clock-latency-ns = <200000>; 372 }; 373 opp-2150400000 { 374 opp-hz = /bits/ 64 <2150400000>; 375 opp-supported-hw = <0x1>; 376 clock-latency-ns = <200000>; 377 }; 378 }; 379 380 firmware { 381 scm { 382 compatible = "qcom,scm-msm8996", "qcom,scm"; 383 qcom,dload-mode = <&tcsr_2 0x13000>; 384 }; 385 }; 386 387 memory@80000000 { 388 device_type = "memory"; 389 /* We expect the bootloader to fill in the reg */ 390 reg = <0x0 0x80000000 0x0 0x0>; 391 }; 392 393 psci { 394 compatible = "arm,psci-1.0"; 395 method = "smc"; 396 }; 397 398 reserved-memory { 399 #address-cells = <2>; 400 #size-cells = <2>; 401 ranges; 402 403 hyp_mem: memory@85800000 { 404 reg = <0x0 0x85800000 0x0 0x600000>; 405 no-map; 406 }; 407 408 xbl_mem: memory@85e00000 { 409 reg = <0x0 0x85e00000 0x0 0x200000>; 410 no-map; 411 }; 412 413 smem_mem: smem-mem@86000000 { 414 reg = <0x0 0x86000000 0x0 0x200000>; 415 no-map; 416 }; 417 418 tz_mem: memory@86200000 { 419 reg = <0x0 0x86200000 0x0 0x2600000>; 420 no-map; 421 }; 422 423 rmtfs_mem: rmtfs { 424 compatible = "qcom,rmtfs-mem"; 425 426 size = <0x0 0x200000>; 427 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 428 no-map; 429 430 qcom,client-id = <1>; 431 qcom,vmid = <15>; 432 }; 433 434 mpss_mem: mpss@88800000 { 435 reg = <0x0 0x88800000 0x0 0x6200000>; 436 no-map; 437 }; 438 439 adsp_mem: adsp@8ea00000 { 440 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 441 no-map; 442 }; 443 444 slpi_mem: slpi@90500000 { 445 reg = <0x0 0x90500000 0x0 0xa00000>; 446 no-map; 447 }; 448 449 gpu_mem: gpu@90f00000 { 450 compatible = "shared-dma-pool"; 451 reg = <0x0 0x90f00000 0x0 0x100000>; 452 no-map; 453 }; 454 455 venus_mem: venus@91000000 { 456 reg = <0x0 0x91000000 0x0 0x500000>; 457 no-map; 458 }; 459 460 mba_mem: mba@91500000 { 461 reg = <0x0 0x91500000 0x0 0x200000>; 462 no-map; 463 }; 464 }; 465 466 rpm-glink { 467 compatible = "qcom,glink-rpm"; 468 469 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 470 471 qcom,rpm-msg-ram = <&rpm_msg_ram>; 472 473 mboxes = <&apcs_glb 0>; 474 475 rpm_requests: rpm-requests { 476 compatible = "qcom,rpm-msm8996"; 477 qcom,glink-channels = "rpm_requests"; 478 479 rpmcc: qcom,rpmcc { 480 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 481 #clock-cells = <1>; 482 clocks = <&xo_board>; 483 clock-names = "xo"; 484 }; 485 486 rpmpd: power-controller { 487 compatible = "qcom,msm8996-rpmpd"; 488 #power-domain-cells = <1>; 489 operating-points-v2 = <&rpmpd_opp_table>; 490 491 rpmpd_opp_table: opp-table { 492 compatible = "operating-points-v2"; 493 494 rpmpd_opp1: opp1 { 495 opp-level = <1>; 496 }; 497 498 rpmpd_opp2: opp2 { 499 opp-level = <2>; 500 }; 501 502 rpmpd_opp3: opp3 { 503 opp-level = <3>; 504 }; 505 506 rpmpd_opp4: opp4 { 507 opp-level = <4>; 508 }; 509 510 rpmpd_opp5: opp5 { 511 opp-level = <5>; 512 }; 513 514 rpmpd_opp6: opp6 { 515 opp-level = <6>; 516 }; 517 }; 518 }; 519 }; 520 }; 521 522 smem { 523 compatible = "qcom,smem"; 524 memory-region = <&smem_mem>; 525 hwlocks = <&tcsr_mutex 3>; 526 }; 527 528 smp2p-adsp { 529 compatible = "qcom,smp2p"; 530 qcom,smem = <443>, <429>; 531 532 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 533 534 mboxes = <&apcs_glb 10>; 535 536 qcom,local-pid = <0>; 537 qcom,remote-pid = <2>; 538 539 adsp_smp2p_out: master-kernel { 540 qcom,entry-name = "master-kernel"; 541 #qcom,smem-state-cells = <1>; 542 }; 543 544 adsp_smp2p_in: slave-kernel { 545 qcom,entry-name = "slave-kernel"; 546 547 interrupt-controller; 548 #interrupt-cells = <2>; 549 }; 550 }; 551 552 smp2p-mpss { 553 compatible = "qcom,smp2p"; 554 qcom,smem = <435>, <428>; 555 556 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 557 558 mboxes = <&apcs_glb 14>; 559 560 qcom,local-pid = <0>; 561 qcom,remote-pid = <1>; 562 563 mpss_smp2p_out: master-kernel { 564 qcom,entry-name = "master-kernel"; 565 #qcom,smem-state-cells = <1>; 566 }; 567 568 mpss_smp2p_in: slave-kernel { 569 qcom,entry-name = "slave-kernel"; 570 571 interrupt-controller; 572 #interrupt-cells = <2>; 573 }; 574 }; 575 576 smp2p-slpi { 577 compatible = "qcom,smp2p"; 578 qcom,smem = <481>, <430>; 579 580 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 581 582 mboxes = <&apcs_glb 26>; 583 584 qcom,local-pid = <0>; 585 qcom,remote-pid = <3>; 586 587 slpi_smp2p_out: master-kernel { 588 qcom,entry-name = "master-kernel"; 589 #qcom,smem-state-cells = <1>; 590 }; 591 592 slpi_smp2p_in: slave-kernel { 593 qcom,entry-name = "slave-kernel"; 594 595 interrupt-controller; 596 #interrupt-cells = <2>; 597 }; 598 }; 599 600 soc: soc { 601 #address-cells = <1>; 602 #size-cells = <1>; 603 ranges = <0 0 0 0xffffffff>; 604 compatible = "simple-bus"; 605 606 pcie_phy: phy-wrapper@34000 { 607 compatible = "qcom,msm8996-qmp-pcie-phy"; 608 reg = <0x00034000 0x488>; 609 #address-cells = <1>; 610 #size-cells = <1>; 611 ranges = <0x0 0x00034000 0x4000>; 612 613 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 614 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 615 <&gcc GCC_PCIE_CLKREF_CLK>; 616 clock-names = "aux", "cfg_ahb", "ref"; 617 618 resets = <&gcc GCC_PCIE_PHY_BCR>, 619 <&gcc GCC_PCIE_PHY_COM_BCR>, 620 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 621 reset-names = "phy", "common", "cfg"; 622 623 status = "disabled"; 624 625 pciephy_0: phy@1000 { 626 reg = <0x1000 0x130>, 627 <0x1200 0x200>, 628 <0x1400 0x1dc>; 629 630 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 631 clock-names = "pipe0"; 632 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 633 reset-names = "lane0"; 634 635 #clock-cells = <0>; 636 clock-output-names = "pcie_0_pipe_clk_src"; 637 638 #phy-cells = <0>; 639 }; 640 641 pciephy_1: phy@2000 { 642 reg = <0x2000 0x130>, 643 <0x2200 0x200>, 644 <0x2400 0x1dc>; 645 646 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 647 clock-names = "pipe1"; 648 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 649 reset-names = "lane1"; 650 651 #clock-cells = <0>; 652 clock-output-names = "pcie_1_pipe_clk_src"; 653 654 #phy-cells = <0>; 655 }; 656 657 pciephy_2: phy@3000 { 658 reg = <0x3000 0x130>, 659 <0x3200 0x200>, 660 <0x3400 0x1dc>; 661 662 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 663 clock-names = "pipe2"; 664 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 665 reset-names = "lane2"; 666 667 #clock-cells = <0>; 668 clock-output-names = "pcie_2_pipe_clk_src"; 669 670 #phy-cells = <0>; 671 }; 672 }; 673 674 rpm_msg_ram: sram@68000 { 675 compatible = "qcom,rpm-msg-ram"; 676 reg = <0x00068000 0x6000>; 677 }; 678 679 qfprom@74000 { 680 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 681 reg = <0x00074000 0x8ff>; 682 #address-cells = <1>; 683 #size-cells = <1>; 684 685 qusb2p_hstx_trim: hstx_trim@24e { 686 reg = <0x24e 0x2>; 687 bits = <5 4>; 688 }; 689 690 qusb2s_hstx_trim: hstx_trim@24f { 691 reg = <0x24f 0x1>; 692 bits = <1 4>; 693 }; 694 695 speedbin_efuse: speedbin@133 { 696 reg = <0x133 0x1>; 697 bits = <5 3>; 698 }; 699 }; 700 701 rng: rng@83000 { 702 compatible = "qcom,prng-ee"; 703 reg = <0x00083000 0x1000>; 704 clocks = <&gcc GCC_PRNG_AHB_CLK>; 705 clock-names = "core"; 706 }; 707 708 gcc: clock-controller@300000 { 709 compatible = "qcom,gcc-msm8996"; 710 #clock-cells = <1>; 711 #reset-cells = <1>; 712 #power-domain-cells = <1>; 713 reg = <0x00300000 0x90000>; 714 715 clocks = <&rpmcc RPM_SMD_BB_CLK1>, 716 <&rpmcc RPM_SMD_LN_BB_CLK>, 717 <&sleep_clk>, 718 <&pciephy_0>, 719 <&pciephy_1>, 720 <&pciephy_2>, 721 <&ssusb_phy_0>, 722 <0>, <0>, <0>; 723 clock-names = "cxo", 724 "cxo2", 725 "sleep_clk", 726 "pcie_0_pipe_clk_src", 727 "pcie_1_pipe_clk_src", 728 "pcie_2_pipe_clk_src", 729 "usb3_phy_pipe_clk_src", 730 "ufs_rx_symbol_0_clk_src", 731 "ufs_rx_symbol_1_clk_src", 732 "ufs_tx_symbol_0_clk_src"; 733 }; 734 735 bimc: interconnect@408000 { 736 compatible = "qcom,msm8996-bimc"; 737 reg = <0x00408000 0x5a000>; 738 #interconnect-cells = <1>; 739 clock-names = "bus", "bus_a"; 740 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 741 <&rpmcc RPM_SMD_BIMC_A_CLK>; 742 }; 743 744 tsens0: thermal-sensor@4a9000 { 745 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 746 reg = <0x004a9000 0x1000>, /* TM */ 747 <0x004a8000 0x1000>; /* SROT */ 748 #qcom,sensors = <13>; 749 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 751 interrupt-names = "uplow", "critical"; 752 #thermal-sensor-cells = <1>; 753 }; 754 755 tsens1: thermal-sensor@4ad000 { 756 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 757 reg = <0x004ad000 0x1000>, /* TM */ 758 <0x004ac000 0x1000>; /* SROT */ 759 #qcom,sensors = <8>; 760 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 762 interrupt-names = "uplow", "critical"; 763 #thermal-sensor-cells = <1>; 764 }; 765 766 cryptobam: dma-controller@644000 { 767 compatible = "qcom,bam-v1.7.0"; 768 reg = <0x00644000 0x24000>; 769 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&gcc GCC_CE1_CLK>; 771 clock-names = "bam_clk"; 772 #dma-cells = <1>; 773 qcom,ee = <0>; 774 qcom,controlled-remotely; 775 }; 776 777 crypto: crypto@67a000 { 778 compatible = "qcom,crypto-v5.4"; 779 reg = <0x0067a000 0x6000>; 780 clocks = <&gcc GCC_CE1_AHB_CLK>, 781 <&gcc GCC_CE1_AXI_CLK>, 782 <&gcc GCC_CE1_CLK>; 783 clock-names = "iface", "bus", "core"; 784 dmas = <&cryptobam 6>, <&cryptobam 7>; 785 dma-names = "rx", "tx"; 786 }; 787 788 cnoc: interconnect@500000 { 789 compatible = "qcom,msm8996-cnoc"; 790 reg = <0x00500000 0x1000>; 791 #interconnect-cells = <1>; 792 clock-names = "bus", "bus_a"; 793 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 794 <&rpmcc RPM_SMD_CNOC_A_CLK>; 795 }; 796 797 snoc: interconnect@524000 { 798 compatible = "qcom,msm8996-snoc"; 799 reg = <0x00524000 0x1c000>; 800 #interconnect-cells = <1>; 801 clock-names = "bus", "bus_a"; 802 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 803 <&rpmcc RPM_SMD_SNOC_A_CLK>; 804 }; 805 806 a0noc: interconnect@543000 { 807 compatible = "qcom,msm8996-a0noc"; 808 reg = <0x00543000 0x6000>; 809 #interconnect-cells = <1>; 810 clock-names = "aggre0_snoc_axi", 811 "aggre0_cnoc_ahb", 812 "aggre0_noc_mpu_cfg"; 813 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 814 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 815 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 816 power-domains = <&gcc AGGRE0_NOC_GDSC>; 817 }; 818 819 a1noc: interconnect@562000 { 820 compatible = "qcom,msm8996-a1noc"; 821 reg = <0x00562000 0x5000>; 822 #interconnect-cells = <1>; 823 clock-names = "bus", "bus_a"; 824 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 825 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 826 }; 827 828 a2noc: interconnect@583000 { 829 compatible = "qcom,msm8996-a2noc"; 830 reg = <0x00583000 0x7000>; 831 #interconnect-cells = <1>; 832 clock-names = "bus", "bus_a"; 833 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 834 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; 835 }; 836 837 mnoc: interconnect@5a4000 { 838 compatible = "qcom,msm8996-mnoc"; 839 reg = <0x005a4000 0x1c000>; 840 #interconnect-cells = <1>; 841 clock-names = "bus", "bus_a", "iface"; 842 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 843 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 844 <&mmcc AHB_CLK_SRC>; 845 }; 846 847 pnoc: interconnect@5c0000 { 848 compatible = "qcom,msm8996-pnoc"; 849 reg = <0x005c0000 0x3000>; 850 #interconnect-cells = <1>; 851 clock-names = "bus", "bus_a"; 852 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 853 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 854 }; 855 856 tcsr_mutex: hwlock@740000 { 857 compatible = "qcom,tcsr-mutex"; 858 reg = <0x00740000 0x20000>; 859 #hwlock-cells = <1>; 860 }; 861 862 tcsr_1: syscon@760000 { 863 compatible = "qcom,tcsr-msm8996", "syscon"; 864 reg = <0x00760000 0x20000>; 865 }; 866 867 tcsr_2: syscon@7a0000 { 868 compatible = "qcom,tcsr-msm8996", "syscon"; 869 reg = <0x007a0000 0x18000>; 870 }; 871 872 mmcc: clock-controller@8c0000 { 873 compatible = "qcom,mmcc-msm8996"; 874 #clock-cells = <1>; 875 #reset-cells = <1>; 876 #power-domain-cells = <1>; 877 reg = <0x008c0000 0x40000>; 878 clocks = <&xo_board>, 879 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 880 <&gcc GPLL0>, 881 <&dsi0_phy 1>, 882 <&dsi0_phy 0>, 883 <0>, 884 <0>, 885 <0>; 886 clock-names = "xo", 887 "gcc_mmss_noc_cfg_ahb_clk", 888 "gpll0", 889 "dsi0pll", 890 "dsi0pllbyte", 891 "dsi1pll", 892 "dsi1pllbyte", 893 "hdmipll"; 894 assigned-clocks = <&mmcc MMPLL9_PLL>, 895 <&mmcc MMPLL1_PLL>, 896 <&mmcc MMPLL3_PLL>, 897 <&mmcc MMPLL4_PLL>, 898 <&mmcc MMPLL5_PLL>; 899 assigned-clock-rates = <624000000>, 900 <810000000>, 901 <980000000>, 902 <960000000>, 903 <825000000>; 904 }; 905 906 mdss: mdss@900000 { 907 compatible = "qcom,mdss"; 908 909 reg = <0x00900000 0x1000>, 910 <0x009b0000 0x1040>, 911 <0x009b8000 0x1040>; 912 reg-names = "mdss_phys", 913 "vbif_phys", 914 "vbif_nrt_phys"; 915 916 power-domains = <&mmcc MDSS_GDSC>; 917 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 918 919 interrupt-controller; 920 #interrupt-cells = <1>; 921 922 clocks = <&mmcc MDSS_AHB_CLK>, 923 <&mmcc MDSS_MDP_CLK>; 924 clock-names = "iface", "core"; 925 926 #address-cells = <1>; 927 #size-cells = <1>; 928 ranges; 929 930 status = "disabled"; 931 932 mdp: mdp@901000 { 933 compatible = "qcom,mdp5"; 934 reg = <0x00901000 0x90000>; 935 reg-names = "mdp_phys"; 936 937 interrupt-parent = <&mdss>; 938 interrupts = <0>; 939 940 clocks = <&mmcc MDSS_AHB_CLK>, 941 <&mmcc MDSS_AXI_CLK>, 942 <&mmcc MDSS_MDP_CLK>, 943 <&mmcc SMMU_MDP_AXI_CLK>, 944 <&mmcc MDSS_VSYNC_CLK>; 945 clock-names = "iface", 946 "bus", 947 "core", 948 "iommu", 949 "vsync"; 950 951 iommus = <&mdp_smmu 0>; 952 953 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 954 <&mmcc MDSS_VSYNC_CLK>; 955 assigned-clock-rates = <300000000>, 956 <19200000>; 957 958 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 959 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 960 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 961 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 962 963 ports { 964 #address-cells = <1>; 965 #size-cells = <0>; 966 967 port@0 { 968 reg = <0>; 969 mdp5_intf3_out: endpoint { 970 remote-endpoint = <&hdmi_in>; 971 }; 972 }; 973 974 port@1 { 975 reg = <1>; 976 mdp5_intf1_out: endpoint { 977 remote-endpoint = <&dsi0_in>; 978 }; 979 }; 980 981 port@2 { 982 reg = <2>; 983 mdp5_intf2_out: endpoint { 984 remote-endpoint = <&dsi1_in>; 985 }; 986 }; 987 }; 988 }; 989 990 dsi0: dsi@994000 { 991 compatible = "qcom,mdss-dsi-ctrl"; 992 reg = <0x00994000 0x400>; 993 reg-names = "dsi_ctrl"; 994 995 interrupt-parent = <&mdss>; 996 interrupts = <4>; 997 998 clocks = <&mmcc MDSS_MDP_CLK>, 999 <&mmcc MDSS_BYTE0_CLK>, 1000 <&mmcc MDSS_AHB_CLK>, 1001 <&mmcc MDSS_AXI_CLK>, 1002 <&mmcc MMSS_MISC_AHB_CLK>, 1003 <&mmcc MDSS_PCLK0_CLK>, 1004 <&mmcc MDSS_ESC0_CLK>; 1005 clock-names = "mdp_core", 1006 "byte", 1007 "iface", 1008 "bus", 1009 "core_mmss", 1010 "pixel", 1011 "core"; 1012 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1013 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 1014 1015 phys = <&dsi0_phy>; 1016 phy-names = "dsi"; 1017 status = "disabled"; 1018 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 1022 ports { 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 1026 port@0 { 1027 reg = <0>; 1028 dsi0_in: endpoint { 1029 remote-endpoint = <&mdp5_intf1_out>; 1030 }; 1031 }; 1032 1033 port@1 { 1034 reg = <1>; 1035 dsi0_out: endpoint { 1036 }; 1037 }; 1038 }; 1039 }; 1040 1041 dsi0_phy: dsi-phy@994400 { 1042 compatible = "qcom,dsi-phy-14nm"; 1043 reg = <0x00994400 0x100>, 1044 <0x00994500 0x300>, 1045 <0x00994800 0x188>; 1046 reg-names = "dsi_phy", 1047 "dsi_phy_lane", 1048 "dsi_pll"; 1049 1050 #clock-cells = <1>; 1051 #phy-cells = <0>; 1052 1053 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 1054 clock-names = "iface", "ref"; 1055 status = "disabled"; 1056 }; 1057 1058 dsi1: dsi@996000 { 1059 compatible = "qcom,mdss-dsi-ctrl"; 1060 reg = <0x00996000 0x400>; 1061 reg-names = "dsi_ctrl"; 1062 1063 interrupt-parent = <&mdss>; 1064 interrupts = <4>; 1065 1066 clocks = <&mmcc MDSS_MDP_CLK>, 1067 <&mmcc MDSS_BYTE1_CLK>, 1068 <&mmcc MDSS_AHB_CLK>, 1069 <&mmcc MDSS_AXI_CLK>, 1070 <&mmcc MMSS_MISC_AHB_CLK>, 1071 <&mmcc MDSS_PCLK1_CLK>, 1072 <&mmcc MDSS_ESC1_CLK>; 1073 clock-names = "mdp_core", 1074 "byte", 1075 "iface", 1076 "bus", 1077 "core_mmss", 1078 "pixel", 1079 "core"; 1080 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1081 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 1082 1083 phys = <&dsi1_phy>; 1084 phy-names = "dsi"; 1085 status = "disabled"; 1086 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 1090 ports { 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 1094 port@0 { 1095 reg = <0>; 1096 dsi1_in: endpoint { 1097 remote-endpoint = <&mdp5_intf2_out>; 1098 }; 1099 }; 1100 1101 port@1 { 1102 reg = <1>; 1103 dsi1_out: endpoint { 1104 }; 1105 }; 1106 }; 1107 }; 1108 1109 dsi1_phy: dsi-phy@996400 { 1110 compatible = "qcom,dsi-phy-14nm"; 1111 reg = <0x00996400 0x100>, 1112 <0x00996500 0x300>, 1113 <0x00996800 0x188>; 1114 reg-names = "dsi_phy", 1115 "dsi_phy_lane", 1116 "dsi_pll"; 1117 1118 #clock-cells = <1>; 1119 #phy-cells = <0>; 1120 1121 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; 1122 clock-names = "iface", "ref"; 1123 status = "disabled"; 1124 }; 1125 1126 hdmi: hdmi-tx@9a0000 { 1127 compatible = "qcom,hdmi-tx-8996"; 1128 reg = <0x009a0000 0x50c>, 1129 <0x00070000 0x6158>, 1130 <0x009e0000 0xfff>; 1131 reg-names = "core_physical", 1132 "qfprom_physical", 1133 "hdcp_physical"; 1134 1135 interrupt-parent = <&mdss>; 1136 interrupts = <8>; 1137 1138 clocks = <&mmcc MDSS_MDP_CLK>, 1139 <&mmcc MDSS_AHB_CLK>, 1140 <&mmcc MDSS_HDMI_CLK>, 1141 <&mmcc MDSS_HDMI_AHB_CLK>, 1142 <&mmcc MDSS_EXTPCLK_CLK>; 1143 clock-names = 1144 "mdp_core", 1145 "iface", 1146 "core", 1147 "alt_iface", 1148 "extp"; 1149 1150 phys = <&hdmi_phy>; 1151 #sound-dai-cells = <1>; 1152 1153 status = "disabled"; 1154 1155 ports { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 1159 port@0 { 1160 reg = <0>; 1161 hdmi_in: endpoint { 1162 remote-endpoint = <&mdp5_intf3_out>; 1163 }; 1164 }; 1165 }; 1166 }; 1167 1168 hdmi_phy: hdmi-phy@9a0600 { 1169 #phy-cells = <0>; 1170 compatible = "qcom,hdmi-phy-8996"; 1171 reg = <0x009a0600 0x1c4>, 1172 <0x009a0a00 0x124>, 1173 <0x009a0c00 0x124>, 1174 <0x009a0e00 0x124>, 1175 <0x009a1000 0x124>, 1176 <0x009a1200 0x0c8>; 1177 reg-names = "hdmi_pll", 1178 "hdmi_tx_l0", 1179 "hdmi_tx_l1", 1180 "hdmi_tx_l2", 1181 "hdmi_tx_l3", 1182 "hdmi_phy"; 1183 1184 clocks = <&mmcc MDSS_AHB_CLK>, 1185 <&gcc GCC_HDMI_CLKREF_CLK>, 1186 <&xo_board>; 1187 clock-names = "iface", 1188 "ref", 1189 "xo"; 1190 1191 #clock-cells = <0>; 1192 1193 status = "disabled"; 1194 }; 1195 }; 1196 1197 gpu: gpu@b00000 { 1198 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1199 1200 reg = <0x00b00000 0x3f000>; 1201 reg-names = "kgsl_3d0_reg_memory"; 1202 1203 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1204 1205 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1206 <&mmcc GPU_AHB_CLK>, 1207 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1208 <&gcc GCC_BIMC_GFX_CLK>, 1209 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1210 1211 clock-names = "core", 1212 "iface", 1213 "rbbmtimer", 1214 "mem", 1215 "mem_iface"; 1216 1217 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1218 interconnect-names = "gfx-mem"; 1219 1220 power-domains = <&mmcc GPU_GX_GDSC>; 1221 iommus = <&adreno_smmu 0>; 1222 1223 nvmem-cells = <&speedbin_efuse>; 1224 nvmem-cell-names = "speed_bin"; 1225 1226 operating-points-v2 = <&gpu_opp_table>; 1227 1228 status = "disabled"; 1229 1230 #cooling-cells = <2>; 1231 1232 gpu_opp_table: opp-table { 1233 compatible = "operating-points-v2"; 1234 1235 /* 1236 * 624Mhz is only available on speed bins 0 and 3. 1237 * 560Mhz is only available on speed bins 0, 2 and 3. 1238 * All the rest are available on all bins of the hardware. 1239 */ 1240 opp-624000000 { 1241 opp-hz = /bits/ 64 <624000000>; 1242 opp-supported-hw = <0x09>; 1243 }; 1244 opp-560000000 { 1245 opp-hz = /bits/ 64 <560000000>; 1246 opp-supported-hw = <0x0d>; 1247 }; 1248 opp-510000000 { 1249 opp-hz = /bits/ 64 <510000000>; 1250 opp-supported-hw = <0xFF>; 1251 }; 1252 opp-401800000 { 1253 opp-hz = /bits/ 64 <401800000>; 1254 opp-supported-hw = <0xFF>; 1255 }; 1256 opp-315000000 { 1257 opp-hz = /bits/ 64 <315000000>; 1258 opp-supported-hw = <0xFF>; 1259 }; 1260 opp-214000000 { 1261 opp-hz = /bits/ 64 <214000000>; 1262 opp-supported-hw = <0xFF>; 1263 }; 1264 opp-133000000 { 1265 opp-hz = /bits/ 64 <133000000>; 1266 opp-supported-hw = <0xFF>; 1267 }; 1268 }; 1269 1270 zap-shader { 1271 memory-region = <&gpu_mem>; 1272 }; 1273 }; 1274 1275 tlmm: pinctrl@1010000 { 1276 compatible = "qcom,msm8996-pinctrl"; 1277 reg = <0x01010000 0x300000>; 1278 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1279 gpio-controller; 1280 gpio-ranges = <&tlmm 0 0 150>; 1281 #gpio-cells = <2>; 1282 interrupt-controller; 1283 #interrupt-cells = <2>; 1284 1285 blsp1_spi1_default: blsp1-spi1-default { 1286 spi { 1287 pins = "gpio0", "gpio1", "gpio3"; 1288 function = "blsp_spi1"; 1289 drive-strength = <12>; 1290 bias-disable; 1291 }; 1292 1293 cs { 1294 pins = "gpio2"; 1295 function = "gpio"; 1296 drive-strength = <16>; 1297 bias-disable; 1298 output-high; 1299 }; 1300 }; 1301 1302 blsp1_spi1_sleep: blsp1-spi1-sleep { 1303 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1304 function = "gpio"; 1305 drive-strength = <2>; 1306 bias-pull-down; 1307 }; 1308 1309 blsp2_uart2_2pins_default: blsp2-uart1-2pins { 1310 pins = "gpio4", "gpio5"; 1311 function = "blsp_uart8"; 1312 drive-strength = <16>; 1313 bias-disable; 1314 }; 1315 1316 blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep { 1317 pins = "gpio4", "gpio5"; 1318 function = "gpio"; 1319 drive-strength = <2>; 1320 bias-disable; 1321 }; 1322 1323 blsp2_i2c2_default: blsp2-i2c2 { 1324 pins = "gpio6", "gpio7"; 1325 function = "blsp_i2c8"; 1326 drive-strength = <16>; 1327 bias-disable; 1328 }; 1329 1330 blsp2_i2c2_sleep: blsp2-i2c2-sleep { 1331 pins = "gpio6", "gpio7"; 1332 function = "gpio"; 1333 drive-strength = <2>; 1334 bias-disable; 1335 }; 1336 1337 cci0_default: cci0-default { 1338 pins = "gpio17", "gpio18"; 1339 function = "cci_i2c"; 1340 drive-strength = <16>; 1341 bias-disable; 1342 }; 1343 1344 camera0_state_on: 1345 camera_rear_default: camera-rear-default { 1346 camera0_mclk: mclk0 { 1347 pins = "gpio13"; 1348 function = "cam_mclk"; 1349 drive-strength = <16>; 1350 bias-disable; 1351 }; 1352 1353 camera0_rst: rst { 1354 pins = "gpio25"; 1355 function = "gpio"; 1356 drive-strength = <16>; 1357 bias-disable; 1358 }; 1359 1360 camera0_pwdn: pwdn { 1361 pins = "gpio26"; 1362 function = "gpio"; 1363 drive-strength = <16>; 1364 bias-disable; 1365 }; 1366 }; 1367 1368 cci1_default: cci1-default { 1369 pins = "gpio19", "gpio20"; 1370 function = "cci_i2c"; 1371 drive-strength = <16>; 1372 bias-disable; 1373 }; 1374 1375 camera1_state_on: 1376 camera_board_default: camera-board-default { 1377 mclk1 { 1378 pins = "gpio14"; 1379 function = "cam_mclk"; 1380 drive-strength = <16>; 1381 bias-disable; 1382 }; 1383 1384 pwdn { 1385 pins = "gpio98"; 1386 function = "gpio"; 1387 drive-strength = <16>; 1388 bias-disable; 1389 }; 1390 1391 rst { 1392 pins = "gpio104"; 1393 function = "gpio"; 1394 drive-strength = <16>; 1395 bias-disable; 1396 }; 1397 }; 1398 1399 camera2_state_on: 1400 camera_front_default: camera-front-default { 1401 camera2_mclk: mclk2 { 1402 pins = "gpio15"; 1403 function = "cam_mclk"; 1404 drive-strength = <16>; 1405 bias-disable; 1406 }; 1407 1408 camera2_rst: rst { 1409 pins = "gpio23"; 1410 function = "gpio"; 1411 drive-strength = <16>; 1412 bias-disable; 1413 }; 1414 1415 pwdn { 1416 pins = "gpio133"; 1417 function = "gpio"; 1418 drive-strength = <16>; 1419 bias-disable; 1420 }; 1421 }; 1422 1423 pcie0_state_on: pcie0-state-on { 1424 perst { 1425 pins = "gpio35"; 1426 function = "gpio"; 1427 drive-strength = <2>; 1428 bias-pull-down; 1429 }; 1430 1431 clkreq { 1432 pins = "gpio36"; 1433 function = "pci_e0"; 1434 drive-strength = <2>; 1435 bias-pull-up; 1436 }; 1437 1438 wake { 1439 pins = "gpio37"; 1440 function = "gpio"; 1441 drive-strength = <2>; 1442 bias-pull-up; 1443 }; 1444 }; 1445 1446 pcie0_state_off: pcie0-state-off { 1447 perst { 1448 pins = "gpio35"; 1449 function = "gpio"; 1450 drive-strength = <2>; 1451 bias-pull-down; 1452 }; 1453 1454 clkreq { 1455 pins = "gpio36"; 1456 function = "gpio"; 1457 drive-strength = <2>; 1458 bias-disable; 1459 }; 1460 1461 wake { 1462 pins = "gpio37"; 1463 function = "gpio"; 1464 drive-strength = <2>; 1465 bias-disable; 1466 }; 1467 }; 1468 1469 blsp1_uart2_default: blsp1-uart2-default { 1470 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1471 function = "blsp_uart2"; 1472 drive-strength = <16>; 1473 bias-disable; 1474 }; 1475 1476 blsp1_uart2_sleep: blsp1-uart2-sleep { 1477 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1478 function = "gpio"; 1479 drive-strength = <2>; 1480 bias-disable; 1481 }; 1482 1483 blsp1_i2c3_default: blsp1-i2c2-default { 1484 pins = "gpio47", "gpio48"; 1485 function = "blsp_i2c3"; 1486 drive-strength = <16>; 1487 bias-disable; 1488 }; 1489 1490 blsp1_i2c3_sleep: blsp1-i2c2-sleep { 1491 pins = "gpio47", "gpio48"; 1492 function = "gpio"; 1493 drive-strength = <2>; 1494 bias-disable; 1495 }; 1496 1497 blsp2_uart3_4pins_default: blsp2-uart2-4pins { 1498 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1499 function = "blsp_uart9"; 1500 drive-strength = <16>; 1501 bias-disable; 1502 }; 1503 1504 blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep { 1505 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1506 function = "blsp_uart9"; 1507 drive-strength = <2>; 1508 bias-disable; 1509 }; 1510 1511 blsp2_i2c3_default: blsp2-i2c3 { 1512 pins = "gpio51", "gpio52"; 1513 function = "blsp_i2c9"; 1514 drive-strength = <16>; 1515 bias-disable; 1516 }; 1517 1518 blsp2_i2c3_sleep: blsp2-i2c3-sleep { 1519 pins = "gpio51", "gpio52"; 1520 function = "gpio"; 1521 drive-strength = <2>; 1522 bias-disable; 1523 }; 1524 1525 wcd_intr_default: wcd-intr-default{ 1526 pins = "gpio54"; 1527 function = "gpio"; 1528 drive-strength = <2>; 1529 bias-pull-down; 1530 input-enable; 1531 }; 1532 1533 blsp2_i2c1_default: blsp2-i2c1 { 1534 pins = "gpio55", "gpio56"; 1535 function = "blsp_i2c7"; 1536 drive-strength = <16>; 1537 bias-disable; 1538 }; 1539 1540 blsp2_i2c1_sleep: blsp2-i2c0-sleep { 1541 pins = "gpio55", "gpio56"; 1542 function = "gpio"; 1543 drive-strength = <2>; 1544 bias-disable; 1545 }; 1546 1547 blsp2_i2c5_default: blsp2-i2c5 { 1548 pins = "gpio60", "gpio61"; 1549 function = "blsp_i2c11"; 1550 drive-strength = <2>; 1551 bias-disable; 1552 }; 1553 1554 /* Sleep state for BLSP2_I2C5 is missing.. */ 1555 1556 cdc_reset_active: cdc-reset-active { 1557 pins = "gpio64"; 1558 function = "gpio"; 1559 drive-strength = <16>; 1560 bias-pull-down; 1561 output-high; 1562 }; 1563 1564 cdc_reset_sleep: cdc-reset-sleep { 1565 pins = "gpio64"; 1566 function = "gpio"; 1567 drive-strength = <16>; 1568 bias-disable; 1569 output-low; 1570 }; 1571 1572 blsp2_spi6_default: blsp2-spi5-default { 1573 spi { 1574 pins = "gpio85", "gpio86", "gpio88"; 1575 function = "blsp_spi12"; 1576 drive-strength = <12>; 1577 bias-disable; 1578 }; 1579 1580 cs { 1581 pins = "gpio87"; 1582 function = "gpio"; 1583 drive-strength = <16>; 1584 bias-disable; 1585 output-high; 1586 }; 1587 }; 1588 1589 blsp2_spi6_sleep: blsp2-spi5-sleep { 1590 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1591 function = "gpio"; 1592 drive-strength = <2>; 1593 bias-pull-down; 1594 }; 1595 1596 blsp2_i2c6_default: blsp2-i2c6 { 1597 pins = "gpio87", "gpio88"; 1598 function = "blsp_i2c12"; 1599 drive-strength = <16>; 1600 bias-disable; 1601 }; 1602 1603 blsp2_i2c6_sleep: blsp2-i2c6-sleep { 1604 pins = "gpio87", "gpio88"; 1605 function = "gpio"; 1606 drive-strength = <2>; 1607 bias-disable; 1608 }; 1609 1610 pcie1_state_on: pcie1-state-on { 1611 perst { 1612 pins = "gpio130"; 1613 function = "gpio"; 1614 drive-strength = <2>; 1615 bias-pull-down; 1616 }; 1617 1618 clkreq { 1619 pins = "gpio131"; 1620 function = "pci_e1"; 1621 drive-strength = <2>; 1622 bias-pull-up; 1623 }; 1624 1625 wake { 1626 pins = "gpio132"; 1627 function = "gpio"; 1628 drive-strength = <2>; 1629 bias-pull-down; 1630 }; 1631 }; 1632 1633 pcie1_state_off: pcie1-state-off { 1634 /* Perst is missing? */ 1635 clkreq { 1636 pins = "gpio131"; 1637 function = "gpio"; 1638 drive-strength = <2>; 1639 bias-disable; 1640 }; 1641 1642 wake { 1643 pins = "gpio132"; 1644 function = "gpio"; 1645 drive-strength = <2>; 1646 bias-disable; 1647 }; 1648 }; 1649 1650 pcie2_state_on: pcie2-state-on { 1651 perst { 1652 pins = "gpio114"; 1653 function = "gpio"; 1654 drive-strength = <2>; 1655 bias-pull-down; 1656 }; 1657 1658 clkreq { 1659 pins = "gpio115"; 1660 function = "pci_e2"; 1661 drive-strength = <2>; 1662 bias-pull-up; 1663 }; 1664 1665 wake { 1666 pins = "gpio116"; 1667 function = "gpio"; 1668 drive-strength = <2>; 1669 bias-pull-down; 1670 }; 1671 }; 1672 1673 pcie2_state_off: pcie2-state-off { 1674 /* Perst is missing? */ 1675 clkreq { 1676 pins = "gpio115"; 1677 function = "gpio"; 1678 drive-strength = <2>; 1679 bias-disable; 1680 }; 1681 1682 wake { 1683 pins = "gpio116"; 1684 function = "gpio"; 1685 drive-strength = <2>; 1686 bias-disable; 1687 }; 1688 }; 1689 1690 sdc1_state_on: sdc1-state-on { 1691 clk { 1692 pins = "sdc1_clk"; 1693 bias-disable; 1694 drive-strength = <16>; 1695 }; 1696 1697 cmd { 1698 pins = "sdc1_cmd"; 1699 bias-pull-up; 1700 drive-strength = <10>; 1701 }; 1702 1703 data { 1704 pins = "sdc1_data"; 1705 bias-pull-up; 1706 drive-strength = <10>; 1707 }; 1708 1709 rclk { 1710 pins = "sdc1_rclk"; 1711 bias-pull-down; 1712 }; 1713 }; 1714 1715 sdc1_state_off: sdc1-state-off { 1716 clk { 1717 pins = "sdc1_clk"; 1718 bias-disable; 1719 drive-strength = <2>; 1720 }; 1721 1722 cmd { 1723 pins = "sdc1_cmd"; 1724 bias-pull-up; 1725 drive-strength = <2>; 1726 }; 1727 1728 data { 1729 pins = "sdc1_data"; 1730 bias-pull-up; 1731 drive-strength = <2>; 1732 }; 1733 1734 rclk { 1735 pins = "sdc1_rclk"; 1736 bias-pull-down; 1737 }; 1738 }; 1739 1740 sdc2_state_on: sdc2-clk-on { 1741 clk { 1742 pins = "sdc2_clk"; 1743 bias-disable; 1744 drive-strength = <16>; 1745 }; 1746 1747 cmd { 1748 pins = "sdc2_cmd"; 1749 bias-pull-up; 1750 drive-strength = <10>; 1751 }; 1752 1753 data { 1754 pins = "sdc2_data"; 1755 bias-pull-up; 1756 drive-strength = <10>; 1757 }; 1758 }; 1759 1760 sdc2_state_off: sdc2-clk-off { 1761 clk { 1762 pins = "sdc2_clk"; 1763 bias-disable; 1764 drive-strength = <2>; 1765 }; 1766 1767 cmd { 1768 pins = "sdc2_cmd"; 1769 bias-pull-up; 1770 drive-strength = <2>; 1771 }; 1772 1773 data { 1774 pins = "sdc2_data"; 1775 bias-pull-up; 1776 drive-strength = <2>; 1777 }; 1778 }; 1779 }; 1780 1781 sram@290000 { 1782 compatible = "qcom,rpm-stats"; 1783 reg = <0x00290000 0x10000>; 1784 }; 1785 1786 spmi_bus: spmi@400f000 { 1787 compatible = "qcom,spmi-pmic-arb"; 1788 reg = <0x0400f000 0x1000>, 1789 <0x04400000 0x800000>, 1790 <0x04c00000 0x800000>, 1791 <0x05800000 0x200000>, 1792 <0x0400a000 0x002100>; 1793 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1794 interrupt-names = "periph_irq"; 1795 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1796 qcom,ee = <0>; 1797 qcom,channel = <0>; 1798 #address-cells = <2>; 1799 #size-cells = <0>; 1800 interrupt-controller; 1801 #interrupt-cells = <4>; 1802 }; 1803 1804 agnoc@0 { 1805 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1806 compatible = "simple-pm-bus"; 1807 #address-cells = <1>; 1808 #size-cells = <1>; 1809 ranges; 1810 1811 pcie0: pcie@600000 { 1812 compatible = "qcom,pcie-msm8996"; 1813 status = "disabled"; 1814 power-domains = <&gcc PCIE0_GDSC>; 1815 bus-range = <0x00 0xff>; 1816 num-lanes = <1>; 1817 1818 reg = <0x00600000 0x2000>, 1819 <0x0c000000 0xf1d>, 1820 <0x0c000f20 0xa8>, 1821 <0x0c100000 0x100000>; 1822 reg-names = "parf", "dbi", "elbi","config"; 1823 1824 phys = <&pciephy_0>; 1825 phy-names = "pciephy"; 1826 1827 #address-cells = <3>; 1828 #size-cells = <2>; 1829 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 1830 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1831 1832 device_type = "pci"; 1833 1834 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1835 interrupt-names = "msi"; 1836 #interrupt-cells = <1>; 1837 interrupt-map-mask = <0 0 0 0x7>; 1838 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1839 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1840 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1841 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1842 1843 pinctrl-names = "default", "sleep"; 1844 pinctrl-0 = <&pcie0_state_on>; 1845 pinctrl-1 = <&pcie0_state_off>; 1846 1847 linux,pci-domain = <0>; 1848 1849 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1850 <&gcc GCC_PCIE_0_AUX_CLK>, 1851 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1852 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1853 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1854 1855 clock-names = "pipe", 1856 "aux", 1857 "cfg", 1858 "bus_master", 1859 "bus_slave"; 1860 1861 }; 1862 1863 pcie1: pcie@608000 { 1864 compatible = "qcom,pcie-msm8996"; 1865 power-domains = <&gcc PCIE1_GDSC>; 1866 bus-range = <0x00 0xff>; 1867 num-lanes = <1>; 1868 1869 status = "disabled"; 1870 1871 reg = <0x00608000 0x2000>, 1872 <0x0d000000 0xf1d>, 1873 <0x0d000f20 0xa8>, 1874 <0x0d100000 0x100000>; 1875 1876 reg-names = "parf", "dbi", "elbi","config"; 1877 1878 phys = <&pciephy_1>; 1879 phy-names = "pciephy"; 1880 1881 #address-cells = <3>; 1882 #size-cells = <2>; 1883 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 1884 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1885 1886 device_type = "pci"; 1887 1888 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1889 interrupt-names = "msi"; 1890 #interrupt-cells = <1>; 1891 interrupt-map-mask = <0 0 0 0x7>; 1892 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1893 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1894 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1895 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1896 1897 pinctrl-names = "default", "sleep"; 1898 pinctrl-0 = <&pcie1_state_on>; 1899 pinctrl-1 = <&pcie1_state_off>; 1900 1901 linux,pci-domain = <1>; 1902 1903 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1904 <&gcc GCC_PCIE_1_AUX_CLK>, 1905 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1906 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1907 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1908 1909 clock-names = "pipe", 1910 "aux", 1911 "cfg", 1912 "bus_master", 1913 "bus_slave"; 1914 }; 1915 1916 pcie2: pcie@610000 { 1917 compatible = "qcom,pcie-msm8996"; 1918 power-domains = <&gcc PCIE2_GDSC>; 1919 bus-range = <0x00 0xff>; 1920 num-lanes = <1>; 1921 status = "disabled"; 1922 reg = <0x00610000 0x2000>, 1923 <0x0e000000 0xf1d>, 1924 <0x0e000f20 0xa8>, 1925 <0x0e100000 0x100000>; 1926 1927 reg-names = "parf", "dbi", "elbi","config"; 1928 1929 phys = <&pciephy_2>; 1930 phy-names = "pciephy"; 1931 1932 #address-cells = <3>; 1933 #size-cells = <2>; 1934 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 1935 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 1936 1937 device_type = "pci"; 1938 1939 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1940 interrupt-names = "msi"; 1941 #interrupt-cells = <1>; 1942 interrupt-map-mask = <0 0 0 0x7>; 1943 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1944 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1945 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1946 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1947 1948 pinctrl-names = "default", "sleep"; 1949 pinctrl-0 = <&pcie2_state_on>; 1950 pinctrl-1 = <&pcie2_state_off>; 1951 1952 linux,pci-domain = <2>; 1953 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1954 <&gcc GCC_PCIE_2_AUX_CLK>, 1955 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1956 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1957 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 1958 1959 clock-names = "pipe", 1960 "aux", 1961 "cfg", 1962 "bus_master", 1963 "bus_slave"; 1964 }; 1965 }; 1966 1967 ufshc: ufshc@624000 { 1968 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 1969 "jedec,ufs-2.0"; 1970 reg = <0x00624000 0x2500>; 1971 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1972 1973 phys = <&ufsphy_lane>; 1974 phy-names = "ufsphy"; 1975 1976 power-domains = <&gcc UFS_GDSC>; 1977 1978 clock-names = 1979 "core_clk_src", 1980 "core_clk", 1981 "bus_clk", 1982 "bus_aggr_clk", 1983 "iface_clk", 1984 "core_clk_unipro_src", 1985 "core_clk_unipro", 1986 "core_clk_ice", 1987 "ref_clk", 1988 "tx_lane0_sync_clk", 1989 "rx_lane0_sync_clk"; 1990 clocks = 1991 <&gcc UFS_AXI_CLK_SRC>, 1992 <&gcc GCC_UFS_AXI_CLK>, 1993 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 1994 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 1995 <&gcc GCC_UFS_AHB_CLK>, 1996 <&gcc UFS_ICE_CORE_CLK_SRC>, 1997 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1998 <&gcc GCC_UFS_ICE_CORE_CLK>, 1999 <&rpmcc RPM_SMD_LN_BB_CLK>, 2000 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2001 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2002 freq-table-hz = 2003 <100000000 200000000>, 2004 <0 0>, 2005 <0 0>, 2006 <0 0>, 2007 <0 0>, 2008 <150000000 300000000>, 2009 <0 0>, 2010 <0 0>, 2011 <0 0>, 2012 <0 0>, 2013 <0 0>; 2014 2015 lanes-per-direction = <1>; 2016 #reset-cells = <1>; 2017 status = "disabled"; 2018 2019 ufs_variant { 2020 compatible = "qcom,ufs_variant"; 2021 }; 2022 }; 2023 2024 ufsphy: phy@627000 { 2025 compatible = "qcom,msm8996-qmp-ufs-phy"; 2026 reg = <0x00627000 0x1c4>; 2027 #address-cells = <1>; 2028 #size-cells = <1>; 2029 ranges; 2030 2031 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2032 clock-names = "ref"; 2033 2034 resets = <&ufshc 0>; 2035 reset-names = "ufsphy"; 2036 status = "disabled"; 2037 2038 ufsphy_lane: phy@627400 { 2039 reg = <0x627400 0x12c>, 2040 <0x627600 0x200>, 2041 <0x627c00 0x1b4>; 2042 #phy-cells = <0>; 2043 }; 2044 }; 2045 2046 camss: camss@a00000 { 2047 compatible = "qcom,msm8996-camss"; 2048 reg = <0x00a34000 0x1000>, 2049 <0x00a00030 0x4>, 2050 <0x00a35000 0x1000>, 2051 <0x00a00038 0x4>, 2052 <0x00a36000 0x1000>, 2053 <0x00a00040 0x4>, 2054 <0x00a30000 0x100>, 2055 <0x00a30400 0x100>, 2056 <0x00a30800 0x100>, 2057 <0x00a30c00 0x100>, 2058 <0x00a31000 0x500>, 2059 <0x00a00020 0x10>, 2060 <0x00a10000 0x1000>, 2061 <0x00a14000 0x1000>; 2062 reg-names = "csiphy0", 2063 "csiphy0_clk_mux", 2064 "csiphy1", 2065 "csiphy1_clk_mux", 2066 "csiphy2", 2067 "csiphy2_clk_mux", 2068 "csid0", 2069 "csid1", 2070 "csid2", 2071 "csid3", 2072 "ispif", 2073 "csi_clk_mux", 2074 "vfe0", 2075 "vfe1"; 2076 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2077 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2078 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2079 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2080 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2081 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2082 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2083 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2084 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2085 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2086 interrupt-names = "csiphy0", 2087 "csiphy1", 2088 "csiphy2", 2089 "csid0", 2090 "csid1", 2091 "csid2", 2092 "csid3", 2093 "ispif", 2094 "vfe0", 2095 "vfe1"; 2096 power-domains = <&mmcc VFE0_GDSC>, 2097 <&mmcc VFE1_GDSC>; 2098 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2099 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2100 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2101 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2102 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2103 <&mmcc CAMSS_CSI0_AHB_CLK>, 2104 <&mmcc CAMSS_CSI0_CLK>, 2105 <&mmcc CAMSS_CSI0PHY_CLK>, 2106 <&mmcc CAMSS_CSI0PIX_CLK>, 2107 <&mmcc CAMSS_CSI0RDI_CLK>, 2108 <&mmcc CAMSS_CSI1_AHB_CLK>, 2109 <&mmcc CAMSS_CSI1_CLK>, 2110 <&mmcc CAMSS_CSI1PHY_CLK>, 2111 <&mmcc CAMSS_CSI1PIX_CLK>, 2112 <&mmcc CAMSS_CSI1RDI_CLK>, 2113 <&mmcc CAMSS_CSI2_AHB_CLK>, 2114 <&mmcc CAMSS_CSI2_CLK>, 2115 <&mmcc CAMSS_CSI2PHY_CLK>, 2116 <&mmcc CAMSS_CSI2PIX_CLK>, 2117 <&mmcc CAMSS_CSI2RDI_CLK>, 2118 <&mmcc CAMSS_CSI3_AHB_CLK>, 2119 <&mmcc CAMSS_CSI3_CLK>, 2120 <&mmcc CAMSS_CSI3PHY_CLK>, 2121 <&mmcc CAMSS_CSI3PIX_CLK>, 2122 <&mmcc CAMSS_CSI3RDI_CLK>, 2123 <&mmcc CAMSS_AHB_CLK>, 2124 <&mmcc CAMSS_VFE0_CLK>, 2125 <&mmcc CAMSS_CSI_VFE0_CLK>, 2126 <&mmcc CAMSS_VFE0_AHB_CLK>, 2127 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2128 <&mmcc CAMSS_VFE1_CLK>, 2129 <&mmcc CAMSS_CSI_VFE1_CLK>, 2130 <&mmcc CAMSS_VFE1_AHB_CLK>, 2131 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2132 <&mmcc CAMSS_VFE_AHB_CLK>, 2133 <&mmcc CAMSS_VFE_AXI_CLK>; 2134 clock-names = "top_ahb", 2135 "ispif_ahb", 2136 "csiphy0_timer", 2137 "csiphy1_timer", 2138 "csiphy2_timer", 2139 "csi0_ahb", 2140 "csi0", 2141 "csi0_phy", 2142 "csi0_pix", 2143 "csi0_rdi", 2144 "csi1_ahb", 2145 "csi1", 2146 "csi1_phy", 2147 "csi1_pix", 2148 "csi1_rdi", 2149 "csi2_ahb", 2150 "csi2", 2151 "csi2_phy", 2152 "csi2_pix", 2153 "csi2_rdi", 2154 "csi3_ahb", 2155 "csi3", 2156 "csi3_phy", 2157 "csi3_pix", 2158 "csi3_rdi", 2159 "ahb", 2160 "vfe0", 2161 "csi_vfe0", 2162 "vfe0_ahb", 2163 "vfe0_stream", 2164 "vfe1", 2165 "csi_vfe1", 2166 "vfe1_ahb", 2167 "vfe1_stream", 2168 "vfe_ahb", 2169 "vfe_axi"; 2170 iommus = <&vfe_smmu 0>, 2171 <&vfe_smmu 1>, 2172 <&vfe_smmu 2>, 2173 <&vfe_smmu 3>; 2174 status = "disabled"; 2175 ports { 2176 #address-cells = <1>; 2177 #size-cells = <0>; 2178 }; 2179 }; 2180 2181 cci: cci@a0c000 { 2182 compatible = "qcom,msm8996-cci"; 2183 #address-cells = <1>; 2184 #size-cells = <0>; 2185 reg = <0xa0c000 0x1000>; 2186 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2187 power-domains = <&mmcc CAMSS_GDSC>; 2188 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2189 <&mmcc CAMSS_CCI_AHB_CLK>, 2190 <&mmcc CAMSS_CCI_CLK>, 2191 <&mmcc CAMSS_AHB_CLK>; 2192 clock-names = "camss_top_ahb", 2193 "cci_ahb", 2194 "cci", 2195 "camss_ahb"; 2196 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2197 <&mmcc CAMSS_CCI_CLK>; 2198 assigned-clock-rates = <80000000>, <37500000>; 2199 pinctrl-names = "default"; 2200 pinctrl-0 = <&cci0_default &cci1_default>; 2201 status = "disabled"; 2202 2203 cci_i2c0: i2c-bus@0 { 2204 reg = <0>; 2205 clock-frequency = <400000>; 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 }; 2209 2210 cci_i2c1: i2c-bus@1 { 2211 reg = <1>; 2212 clock-frequency = <400000>; 2213 #address-cells = <1>; 2214 #size-cells = <0>; 2215 }; 2216 }; 2217 2218 adreno_smmu: iommu@b40000 { 2219 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2220 reg = <0x00b40000 0x10000>; 2221 2222 #global-interrupts = <1>; 2223 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2226 #iommu-cells = <1>; 2227 2228 clocks = <&mmcc GPU_AHB_CLK>, 2229 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 2230 clock-names = "iface", "bus"; 2231 2232 power-domains = <&mmcc GPU_GDSC>; 2233 }; 2234 2235 venus: video-codec@c00000 { 2236 compatible = "qcom,msm8996-venus"; 2237 reg = <0x00c00000 0xff000>; 2238 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2239 power-domains = <&mmcc VENUS_GDSC>; 2240 clocks = <&mmcc VIDEO_CORE_CLK>, 2241 <&mmcc VIDEO_AHB_CLK>, 2242 <&mmcc VIDEO_AXI_CLK>, 2243 <&mmcc VIDEO_MAXI_CLK>; 2244 clock-names = "core", "iface", "bus", "mbus"; 2245 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2246 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2247 interconnect-names = "video-mem", "cpu-cfg"; 2248 iommus = <&venus_smmu 0x00>, 2249 <&venus_smmu 0x01>, 2250 <&venus_smmu 0x0a>, 2251 <&venus_smmu 0x07>, 2252 <&venus_smmu 0x0e>, 2253 <&venus_smmu 0x0f>, 2254 <&venus_smmu 0x08>, 2255 <&venus_smmu 0x09>, 2256 <&venus_smmu 0x0b>, 2257 <&venus_smmu 0x0c>, 2258 <&venus_smmu 0x0d>, 2259 <&venus_smmu 0x10>, 2260 <&venus_smmu 0x11>, 2261 <&venus_smmu 0x21>, 2262 <&venus_smmu 0x28>, 2263 <&venus_smmu 0x29>, 2264 <&venus_smmu 0x2b>, 2265 <&venus_smmu 0x2c>, 2266 <&venus_smmu 0x2d>, 2267 <&venus_smmu 0x31>; 2268 memory-region = <&venus_mem>; 2269 status = "disabled"; 2270 2271 video-decoder { 2272 compatible = "venus-decoder"; 2273 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2274 clock-names = "core"; 2275 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2276 }; 2277 2278 video-encoder { 2279 compatible = "venus-encoder"; 2280 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2281 clock-names = "core"; 2282 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2283 }; 2284 }; 2285 2286 mdp_smmu: iommu@d00000 { 2287 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2288 reg = <0x00d00000 0x10000>; 2289 2290 #global-interrupts = <1>; 2291 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2294 #iommu-cells = <1>; 2295 clocks = <&mmcc SMMU_MDP_AHB_CLK>, 2296 <&mmcc SMMU_MDP_AXI_CLK>; 2297 clock-names = "iface", "bus"; 2298 2299 power-domains = <&mmcc MDSS_GDSC>; 2300 }; 2301 2302 venus_smmu: iommu@d40000 { 2303 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2304 reg = <0x00d40000 0x20000>; 2305 #global-interrupts = <1>; 2306 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2307 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2308 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2309 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2310 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2311 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2312 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2313 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2314 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2315 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, 2316 <&mmcc SMMU_VIDEO_AXI_CLK>; 2317 clock-names = "iface", "bus"; 2318 #iommu-cells = <1>; 2319 status = "okay"; 2320 }; 2321 2322 vfe_smmu: iommu@da0000 { 2323 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2324 reg = <0x00da0000 0x10000>; 2325 2326 #global-interrupts = <1>; 2327 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2328 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2329 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2330 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2331 clocks = <&mmcc SMMU_VFE_AHB_CLK>, 2332 <&mmcc SMMU_VFE_AXI_CLK>; 2333 clock-names = "iface", 2334 "bus"; 2335 #iommu-cells = <1>; 2336 }; 2337 2338 lpass_q6_smmu: iommu@1600000 { 2339 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2340 reg = <0x01600000 0x20000>; 2341 #iommu-cells = <1>; 2342 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2343 2344 #global-interrupts = <1>; 2345 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2346 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2347 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2348 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2349 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2351 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2352 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2353 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2356 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2358 2359 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, 2360 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 2361 clock-names = "iface", "bus"; 2362 }; 2363 2364 slpi_pil: remoteproc@1c00000 { 2365 compatible = "qcom,msm8996-slpi-pil"; 2366 reg = <0x01c00000 0x4000>; 2367 2368 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2369 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2370 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2371 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2372 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2373 interrupt-names = "wdog", 2374 "fatal", 2375 "ready", 2376 "handover", 2377 "stop-ack"; 2378 2379 clocks = <&xo_board>, 2380 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2381 clock-names = "xo", "aggre2"; 2382 2383 memory-region = <&slpi_mem>; 2384 2385 qcom,smem-states = <&slpi_smp2p_out 0>; 2386 qcom,smem-state-names = "stop"; 2387 2388 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2389 power-domain-names = "ssc_cx"; 2390 2391 status = "disabled"; 2392 2393 smd-edge { 2394 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2395 2396 label = "dsps"; 2397 mboxes = <&apcs_glb 25>; 2398 qcom,smd-edge = <3>; 2399 qcom,remote-pid = <3>; 2400 }; 2401 }; 2402 2403 mss_pil: remoteproc@2080000 { 2404 compatible = "qcom,msm8996-mss-pil"; 2405 reg = <0x2080000 0x100>, 2406 <0x2180000 0x020>; 2407 reg-names = "qdsp6", "rmb"; 2408 2409 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2410 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2411 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2412 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2413 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2414 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2415 interrupt-names = "wdog", "fatal", "ready", 2416 "handover", "stop-ack", 2417 "shutdown-ack"; 2418 2419 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2420 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2421 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2422 <&xo_board>, 2423 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2424 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2425 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2426 <&rpmcc RPM_SMD_PCNOC_CLK>, 2427 <&rpmcc RPM_SMD_QDSS_CLK>; 2428 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2429 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2430 2431 resets = <&gcc GCC_MSS_RESTART>; 2432 reset-names = "mss_restart"; 2433 2434 power-domains = <&rpmpd MSM8996_VDDCX>, 2435 <&rpmpd MSM8996_VDDMX>; 2436 power-domain-names = "cx", "mx"; 2437 2438 qcom,smem-states = <&mpss_smp2p_out 0>; 2439 qcom,smem-state-names = "stop"; 2440 2441 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2442 2443 status = "disabled"; 2444 2445 mba { 2446 memory-region = <&mba_mem>; 2447 }; 2448 2449 mpss { 2450 memory-region = <&mpss_mem>; 2451 }; 2452 2453 smd-edge { 2454 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2455 2456 label = "mpss"; 2457 mboxes = <&apcs_glb 12>; 2458 qcom,smd-edge = <0>; 2459 qcom,remote-pid = <1>; 2460 }; 2461 }; 2462 2463 stm@3002000 { 2464 compatible = "arm,coresight-stm", "arm,primecell"; 2465 reg = <0x3002000 0x1000>, 2466 <0x8280000 0x180000>; 2467 reg-names = "stm-base", "stm-stimulus-base"; 2468 2469 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2470 clock-names = "apb_pclk", "atclk"; 2471 2472 out-ports { 2473 port { 2474 stm_out: endpoint { 2475 remote-endpoint = 2476 <&funnel0_in>; 2477 }; 2478 }; 2479 }; 2480 }; 2481 2482 tpiu@3020000 { 2483 compatible = "arm,coresight-tpiu", "arm,primecell"; 2484 reg = <0x3020000 0x1000>; 2485 2486 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2487 clock-names = "apb_pclk", "atclk"; 2488 2489 in-ports { 2490 port { 2491 tpiu_in: endpoint { 2492 remote-endpoint = 2493 <&replicator_out1>; 2494 }; 2495 }; 2496 }; 2497 }; 2498 2499 funnel@3021000 { 2500 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2501 reg = <0x3021000 0x1000>; 2502 2503 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2504 clock-names = "apb_pclk", "atclk"; 2505 2506 in-ports { 2507 #address-cells = <1>; 2508 #size-cells = <0>; 2509 2510 port@7 { 2511 reg = <7>; 2512 funnel0_in: endpoint { 2513 remote-endpoint = 2514 <&stm_out>; 2515 }; 2516 }; 2517 }; 2518 2519 out-ports { 2520 port { 2521 funnel0_out: endpoint { 2522 remote-endpoint = 2523 <&merge_funnel_in0>; 2524 }; 2525 }; 2526 }; 2527 }; 2528 2529 funnel@3022000 { 2530 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2531 reg = <0x3022000 0x1000>; 2532 2533 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2534 clock-names = "apb_pclk", "atclk"; 2535 2536 in-ports { 2537 #address-cells = <1>; 2538 #size-cells = <0>; 2539 2540 port@6 { 2541 reg = <6>; 2542 funnel1_in: endpoint { 2543 remote-endpoint = 2544 <&apss_merge_funnel_out>; 2545 }; 2546 }; 2547 }; 2548 2549 out-ports { 2550 port { 2551 funnel1_out: endpoint { 2552 remote-endpoint = 2553 <&merge_funnel_in1>; 2554 }; 2555 }; 2556 }; 2557 }; 2558 2559 funnel@3023000 { 2560 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2561 reg = <0x3023000 0x1000>; 2562 2563 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2564 clock-names = "apb_pclk", "atclk"; 2565 2566 2567 out-ports { 2568 port { 2569 funnel2_out: endpoint { 2570 remote-endpoint = 2571 <&merge_funnel_in2>; 2572 }; 2573 }; 2574 }; 2575 }; 2576 2577 funnel@3025000 { 2578 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2579 reg = <0x3025000 0x1000>; 2580 2581 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2582 clock-names = "apb_pclk", "atclk"; 2583 2584 in-ports { 2585 #address-cells = <1>; 2586 #size-cells = <0>; 2587 2588 port@0 { 2589 reg = <0>; 2590 merge_funnel_in0: endpoint { 2591 remote-endpoint = 2592 <&funnel0_out>; 2593 }; 2594 }; 2595 2596 port@1 { 2597 reg = <1>; 2598 merge_funnel_in1: endpoint { 2599 remote-endpoint = 2600 <&funnel1_out>; 2601 }; 2602 }; 2603 2604 port@2 { 2605 reg = <2>; 2606 merge_funnel_in2: endpoint { 2607 remote-endpoint = 2608 <&funnel2_out>; 2609 }; 2610 }; 2611 }; 2612 2613 out-ports { 2614 port { 2615 merge_funnel_out: endpoint { 2616 remote-endpoint = 2617 <&etf_in>; 2618 }; 2619 }; 2620 }; 2621 }; 2622 2623 replicator@3026000 { 2624 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2625 reg = <0x3026000 0x1000>; 2626 2627 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2628 clock-names = "apb_pclk", "atclk"; 2629 2630 in-ports { 2631 port { 2632 replicator_in: endpoint { 2633 remote-endpoint = 2634 <&etf_out>; 2635 }; 2636 }; 2637 }; 2638 2639 out-ports { 2640 #address-cells = <1>; 2641 #size-cells = <0>; 2642 2643 port@0 { 2644 reg = <0>; 2645 replicator_out0: endpoint { 2646 remote-endpoint = 2647 <&etr_in>; 2648 }; 2649 }; 2650 2651 port@1 { 2652 reg = <1>; 2653 replicator_out1: endpoint { 2654 remote-endpoint = 2655 <&tpiu_in>; 2656 }; 2657 }; 2658 }; 2659 }; 2660 2661 etf@3027000 { 2662 compatible = "arm,coresight-tmc", "arm,primecell"; 2663 reg = <0x3027000 0x1000>; 2664 2665 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2666 clock-names = "apb_pclk", "atclk"; 2667 2668 in-ports { 2669 port { 2670 etf_in: endpoint { 2671 remote-endpoint = 2672 <&merge_funnel_out>; 2673 }; 2674 }; 2675 }; 2676 2677 out-ports { 2678 port { 2679 etf_out: endpoint { 2680 remote-endpoint = 2681 <&replicator_in>; 2682 }; 2683 }; 2684 }; 2685 }; 2686 2687 etr@3028000 { 2688 compatible = "arm,coresight-tmc", "arm,primecell"; 2689 reg = <0x3028000 0x1000>; 2690 2691 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2692 clock-names = "apb_pclk", "atclk"; 2693 arm,scatter-gather; 2694 2695 in-ports { 2696 port { 2697 etr_in: endpoint { 2698 remote-endpoint = 2699 <&replicator_out0>; 2700 }; 2701 }; 2702 }; 2703 }; 2704 2705 debug@3810000 { 2706 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2707 reg = <0x3810000 0x1000>; 2708 2709 clocks = <&rpmcc RPM_QDSS_CLK>; 2710 clock-names = "apb_pclk"; 2711 2712 cpu = <&CPU0>; 2713 }; 2714 2715 etm@3840000 { 2716 compatible = "arm,coresight-etm4x", "arm,primecell"; 2717 reg = <0x3840000 0x1000>; 2718 2719 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2720 clock-names = "apb_pclk", "atclk"; 2721 2722 cpu = <&CPU0>; 2723 2724 out-ports { 2725 port { 2726 etm0_out: endpoint { 2727 remote-endpoint = 2728 <&apss_funnel0_in0>; 2729 }; 2730 }; 2731 }; 2732 }; 2733 2734 debug@3910000 { 2735 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2736 reg = <0x3910000 0x1000>; 2737 2738 clocks = <&rpmcc RPM_QDSS_CLK>; 2739 clock-names = "apb_pclk"; 2740 2741 cpu = <&CPU1>; 2742 }; 2743 2744 etm@3940000 { 2745 compatible = "arm,coresight-etm4x", "arm,primecell"; 2746 reg = <0x3940000 0x1000>; 2747 2748 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2749 clock-names = "apb_pclk", "atclk"; 2750 2751 cpu = <&CPU1>; 2752 2753 out-ports { 2754 port { 2755 etm1_out: endpoint { 2756 remote-endpoint = 2757 <&apss_funnel0_in1>; 2758 }; 2759 }; 2760 }; 2761 }; 2762 2763 funnel@39b0000 { /* APSS Funnel 0 */ 2764 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2765 reg = <0x39b0000 0x1000>; 2766 2767 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2768 clock-names = "apb_pclk", "atclk"; 2769 2770 in-ports { 2771 #address-cells = <1>; 2772 #size-cells = <0>; 2773 2774 port@0 { 2775 reg = <0>; 2776 apss_funnel0_in0: endpoint { 2777 remote-endpoint = <&etm0_out>; 2778 }; 2779 }; 2780 2781 port@1 { 2782 reg = <1>; 2783 apss_funnel0_in1: endpoint { 2784 remote-endpoint = <&etm1_out>; 2785 }; 2786 }; 2787 }; 2788 2789 out-ports { 2790 port { 2791 apss_funnel0_out: endpoint { 2792 remote-endpoint = 2793 <&apss_merge_funnel_in0>; 2794 }; 2795 }; 2796 }; 2797 }; 2798 2799 debug@3a10000 { 2800 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2801 reg = <0x3a10000 0x1000>; 2802 2803 clocks = <&rpmcc RPM_QDSS_CLK>; 2804 clock-names = "apb_pclk"; 2805 2806 cpu = <&CPU2>; 2807 }; 2808 2809 etm@3a40000 { 2810 compatible = "arm,coresight-etm4x", "arm,primecell"; 2811 reg = <0x3a40000 0x1000>; 2812 2813 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2814 clock-names = "apb_pclk", "atclk"; 2815 2816 cpu = <&CPU2>; 2817 2818 out-ports { 2819 port { 2820 etm2_out: endpoint { 2821 remote-endpoint = 2822 <&apss_funnel1_in0>; 2823 }; 2824 }; 2825 }; 2826 }; 2827 2828 debug@3b10000 { 2829 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2830 reg = <0x3b10000 0x1000>; 2831 2832 clocks = <&rpmcc RPM_QDSS_CLK>; 2833 clock-names = "apb_pclk"; 2834 2835 cpu = <&CPU3>; 2836 }; 2837 2838 etm@3b40000 { 2839 compatible = "arm,coresight-etm4x", "arm,primecell"; 2840 reg = <0x3b40000 0x1000>; 2841 2842 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2843 clock-names = "apb_pclk", "atclk"; 2844 2845 cpu = <&CPU3>; 2846 2847 out-ports { 2848 port { 2849 etm3_out: endpoint { 2850 remote-endpoint = 2851 <&apss_funnel1_in1>; 2852 }; 2853 }; 2854 }; 2855 }; 2856 2857 funnel@3bb0000 { /* APSS Funnel 1 */ 2858 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2859 reg = <0x3bb0000 0x1000>; 2860 2861 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2862 clock-names = "apb_pclk", "atclk"; 2863 2864 in-ports { 2865 #address-cells = <1>; 2866 #size-cells = <0>; 2867 2868 port@0 { 2869 reg = <0>; 2870 apss_funnel1_in0: endpoint { 2871 remote-endpoint = <&etm2_out>; 2872 }; 2873 }; 2874 2875 port@1 { 2876 reg = <1>; 2877 apss_funnel1_in1: endpoint { 2878 remote-endpoint = <&etm3_out>; 2879 }; 2880 }; 2881 }; 2882 2883 out-ports { 2884 port { 2885 apss_funnel1_out: endpoint { 2886 remote-endpoint = 2887 <&apss_merge_funnel_in1>; 2888 }; 2889 }; 2890 }; 2891 }; 2892 2893 funnel@3bc0000 { 2894 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2895 reg = <0x3bc0000 0x1000>; 2896 2897 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2898 clock-names = "apb_pclk", "atclk"; 2899 2900 in-ports { 2901 #address-cells = <1>; 2902 #size-cells = <0>; 2903 2904 port@0 { 2905 reg = <0>; 2906 apss_merge_funnel_in0: endpoint { 2907 remote-endpoint = 2908 <&apss_funnel0_out>; 2909 }; 2910 }; 2911 2912 port@1 { 2913 reg = <1>; 2914 apss_merge_funnel_in1: endpoint { 2915 remote-endpoint = 2916 <&apss_funnel1_out>; 2917 }; 2918 }; 2919 }; 2920 2921 out-ports { 2922 port { 2923 apss_merge_funnel_out: endpoint { 2924 remote-endpoint = 2925 <&funnel1_in>; 2926 }; 2927 }; 2928 }; 2929 }; 2930 2931 kryocc: clock-controller@6400000 { 2932 compatible = "qcom,msm8996-apcc"; 2933 reg = <0x06400000 0x90000>; 2934 2935 clock-names = "xo"; 2936 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 2937 2938 #clock-cells = <1>; 2939 }; 2940 2941 usb3: usb@6af8800 { 2942 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 2943 reg = <0x06af8800 0x400>; 2944 #address-cells = <1>; 2945 #size-cells = <1>; 2946 ranges; 2947 2948 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2950 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 2951 2952 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 2953 <&gcc GCC_USB30_MASTER_CLK>, 2954 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 2955 <&gcc GCC_USB30_SLEEP_CLK>, 2956 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2957 clock-names = "cfg_noc", 2958 "core", 2959 "iface", 2960 "sleep", 2961 "mock_utmi"; 2962 2963 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2964 <&gcc GCC_USB30_MASTER_CLK>; 2965 assigned-clock-rates = <19200000>, <120000000>; 2966 2967 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 2968 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 2969 interconnect-names = "usb-ddr", "apps-usb"; 2970 2971 power-domains = <&gcc USB30_GDSC>; 2972 status = "disabled"; 2973 2974 usb3_dwc3: usb@6a00000 { 2975 compatible = "snps,dwc3"; 2976 reg = <0x06a00000 0xcc00>; 2977 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 2978 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 2979 phy-names = "usb2-phy", "usb3-phy"; 2980 snps,dis_u2_susphy_quirk; 2981 snps,dis_enblslpm_quirk; 2982 }; 2983 }; 2984 2985 usb3phy: phy@7410000 { 2986 compatible = "qcom,msm8996-qmp-usb3-phy"; 2987 reg = <0x07410000 0x1c4>; 2988 #address-cells = <1>; 2989 #size-cells = <1>; 2990 ranges; 2991 2992 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2993 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2994 <&gcc GCC_USB3_CLKREF_CLK>; 2995 clock-names = "aux", "cfg_ahb", "ref"; 2996 2997 resets = <&gcc GCC_USB3_PHY_BCR>, 2998 <&gcc GCC_USB3PHY_PHY_BCR>; 2999 reset-names = "phy", "common"; 3000 status = "disabled"; 3001 3002 ssusb_phy_0: phy@7410200 { 3003 reg = <0x07410200 0x200>, 3004 <0x07410400 0x130>, 3005 <0x07410600 0x1a8>; 3006 #phy-cells = <0>; 3007 3008 #clock-cells = <0>; 3009 clock-output-names = "usb3_phy_pipe_clk_src"; 3010 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 3011 clock-names = "pipe0"; 3012 }; 3013 }; 3014 3015 hsusb_phy1: phy@7411000 { 3016 compatible = "qcom,msm8996-qusb2-phy"; 3017 reg = <0x07411000 0x180>; 3018 #phy-cells = <0>; 3019 3020 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3021 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3022 clock-names = "cfg_ahb", "ref"; 3023 3024 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3025 nvmem-cells = <&qusb2p_hstx_trim>; 3026 status = "disabled"; 3027 }; 3028 3029 hsusb_phy2: phy@7412000 { 3030 compatible = "qcom,msm8996-qusb2-phy"; 3031 reg = <0x07412000 0x180>; 3032 #phy-cells = <0>; 3033 3034 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3035 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3036 clock-names = "cfg_ahb", "ref"; 3037 3038 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3039 nvmem-cells = <&qusb2s_hstx_trim>; 3040 status = "disabled"; 3041 }; 3042 3043 sdhc1: mmc@7464900 { 3044 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3045 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3046 reg-names = "hc", "core"; 3047 3048 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3049 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3050 interrupt-names = "hc_irq", "pwr_irq"; 3051 3052 clock-names = "iface", "core", "xo"; 3053 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3054 <&gcc GCC_SDCC1_APPS_CLK>, 3055 <&rpmcc RPM_SMD_BB_CLK1>; 3056 resets = <&gcc GCC_SDCC1_BCR>; 3057 3058 pinctrl-names = "default", "sleep"; 3059 pinctrl-0 = <&sdc1_state_on>; 3060 pinctrl-1 = <&sdc1_state_off>; 3061 3062 bus-width = <8>; 3063 non-removable; 3064 status = "disabled"; 3065 }; 3066 3067 sdhc2: mmc@74a4900 { 3068 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3069 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3070 reg-names = "hc", "core"; 3071 3072 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3074 interrupt-names = "hc_irq", "pwr_irq"; 3075 3076 clock-names = "iface", "core", "xo"; 3077 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3078 <&gcc GCC_SDCC2_APPS_CLK>, 3079 <&rpmcc RPM_SMD_BB_CLK1>; 3080 resets = <&gcc GCC_SDCC2_BCR>; 3081 3082 pinctrl-names = "default", "sleep"; 3083 pinctrl-0 = <&sdc2_state_on>; 3084 pinctrl-1 = <&sdc2_state_off>; 3085 3086 bus-width = <4>; 3087 status = "disabled"; 3088 }; 3089 3090 blsp1_dma: dma-controller@7544000 { 3091 compatible = "qcom,bam-v1.7.0"; 3092 reg = <0x07544000 0x2b000>; 3093 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3094 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3095 clock-names = "bam_clk"; 3096 qcom,controlled-remotely; 3097 #dma-cells = <1>; 3098 qcom,ee = <0>; 3099 }; 3100 3101 blsp1_uart2: serial@7570000 { 3102 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3103 reg = <0x07570000 0x1000>; 3104 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3105 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3106 <&gcc GCC_BLSP1_AHB_CLK>; 3107 clock-names = "core", "iface"; 3108 pinctrl-names = "default", "sleep"; 3109 pinctrl-0 = <&blsp1_uart2_default>; 3110 pinctrl-1 = <&blsp1_uart2_sleep>; 3111 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3112 dma-names = "tx", "rx"; 3113 status = "disabled"; 3114 }; 3115 3116 blsp1_spi1: spi@7575000 { 3117 compatible = "qcom,spi-qup-v2.2.1"; 3118 reg = <0x07575000 0x600>; 3119 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3120 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3121 <&gcc GCC_BLSP1_AHB_CLK>; 3122 clock-names = "core", "iface"; 3123 pinctrl-names = "default", "sleep"; 3124 pinctrl-0 = <&blsp1_spi1_default>; 3125 pinctrl-1 = <&blsp1_spi1_sleep>; 3126 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3127 dma-names = "tx", "rx"; 3128 #address-cells = <1>; 3129 #size-cells = <0>; 3130 status = "disabled"; 3131 }; 3132 3133 blsp1_i2c3: i2c@7577000 { 3134 compatible = "qcom,i2c-qup-v2.2.1"; 3135 reg = <0x07577000 0x1000>; 3136 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3137 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3138 <&gcc GCC_BLSP1_AHB_CLK>; 3139 clock-names = "core", "iface"; 3140 pinctrl-names = "default", "sleep"; 3141 pinctrl-0 = <&blsp1_i2c3_default>; 3142 pinctrl-1 = <&blsp1_i2c3_sleep>; 3143 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3144 dma-names = "tx", "rx"; 3145 #address-cells = <1>; 3146 #size-cells = <0>; 3147 status = "disabled"; 3148 }; 3149 3150 blsp2_dma: dma-controller@7584000 { 3151 compatible = "qcom,bam-v1.7.0"; 3152 reg = <0x07584000 0x2b000>; 3153 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3154 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3155 clock-names = "bam_clk"; 3156 qcom,controlled-remotely; 3157 #dma-cells = <1>; 3158 qcom,ee = <0>; 3159 }; 3160 3161 blsp2_uart2: serial@75b0000 { 3162 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3163 reg = <0x075b0000 0x1000>; 3164 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3165 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3166 <&gcc GCC_BLSP2_AHB_CLK>; 3167 clock-names = "core", "iface"; 3168 status = "disabled"; 3169 }; 3170 3171 blsp2_uart3: serial@75b1000 { 3172 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3173 reg = <0x075b1000 0x1000>; 3174 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3175 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3176 <&gcc GCC_BLSP2_AHB_CLK>; 3177 clock-names = "core", "iface"; 3178 status = "disabled"; 3179 }; 3180 3181 blsp2_i2c1: i2c@75b5000 { 3182 compatible = "qcom,i2c-qup-v2.2.1"; 3183 reg = <0x075b5000 0x1000>; 3184 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3185 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3186 <&gcc GCC_BLSP2_AHB_CLK>; 3187 clock-names = "core", "iface"; 3188 pinctrl-names = "default", "sleep"; 3189 pinctrl-0 = <&blsp2_i2c1_default>; 3190 pinctrl-1 = <&blsp2_i2c1_sleep>; 3191 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3192 dma-names = "tx", "rx"; 3193 #address-cells = <1>; 3194 #size-cells = <0>; 3195 status = "disabled"; 3196 }; 3197 3198 blsp2_i2c2: i2c@75b6000 { 3199 compatible = "qcom,i2c-qup-v2.2.1"; 3200 reg = <0x075b6000 0x1000>; 3201 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3202 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3203 <&gcc GCC_BLSP2_AHB_CLK>; 3204 clock-names = "core", "iface"; 3205 pinctrl-names = "default", "sleep"; 3206 pinctrl-0 = <&blsp2_i2c2_default>; 3207 pinctrl-1 = <&blsp2_i2c2_sleep>; 3208 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3209 dma-names = "tx", "rx"; 3210 #address-cells = <1>; 3211 #size-cells = <0>; 3212 status = "disabled"; 3213 }; 3214 3215 blsp2_i2c3: i2c@75b7000 { 3216 compatible = "qcom,i2c-qup-v2.2.1"; 3217 reg = <0x075b7000 0x1000>; 3218 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3219 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3220 <&gcc GCC_BLSP2_AHB_CLK>; 3221 clock-names = "core", "iface"; 3222 clock-frequency = <400000>; 3223 pinctrl-names = "default", "sleep"; 3224 pinctrl-0 = <&blsp2_i2c3_default>; 3225 pinctrl-1 = <&blsp2_i2c3_sleep>; 3226 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3227 dma-names = "tx", "rx"; 3228 #address-cells = <1>; 3229 #size-cells = <0>; 3230 status = "disabled"; 3231 }; 3232 3233 blsp2_i2c5: i2c@75b9000 { 3234 compatible = "qcom,i2c-qup-v2.2.1"; 3235 reg = <0x75b9000 0x1000>; 3236 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3237 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3238 <&gcc GCC_BLSP2_AHB_CLK>; 3239 clock-names = "core", "iface"; 3240 pinctrl-names = "default"; 3241 pinctrl-0 = <&blsp2_i2c5_default>; 3242 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3243 dma-names = "tx", "rx"; 3244 #address-cells = <1>; 3245 #size-cells = <0>; 3246 status = "disabled"; 3247 }; 3248 3249 blsp2_i2c6: i2c@75ba000 { 3250 compatible = "qcom,i2c-qup-v2.2.1"; 3251 reg = <0x75ba000 0x1000>; 3252 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3253 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3254 <&gcc GCC_BLSP2_AHB_CLK>; 3255 clock-names = "core", "iface"; 3256 pinctrl-names = "default", "sleep"; 3257 pinctrl-0 = <&blsp2_i2c6_default>; 3258 pinctrl-1 = <&blsp2_i2c6_sleep>; 3259 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3260 dma-names = "tx", "rx"; 3261 #address-cells = <1>; 3262 #size-cells = <0>; 3263 status = "disabled"; 3264 }; 3265 3266 blsp2_spi6: spi@75ba000{ 3267 compatible = "qcom,spi-qup-v2.2.1"; 3268 reg = <0x075ba000 0x600>; 3269 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3270 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3271 <&gcc GCC_BLSP2_AHB_CLK>; 3272 clock-names = "core", "iface"; 3273 pinctrl-names = "default", "sleep"; 3274 pinctrl-0 = <&blsp2_spi6_default>; 3275 pinctrl-1 = <&blsp2_spi6_sleep>; 3276 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3277 dma-names = "tx", "rx"; 3278 #address-cells = <1>; 3279 #size-cells = <0>; 3280 status = "disabled"; 3281 }; 3282 3283 usb2: usb@76f8800 { 3284 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3285 reg = <0x076f8800 0x400>; 3286 #address-cells = <1>; 3287 #size-cells = <1>; 3288 ranges; 3289 3290 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3291 <&gcc GCC_USB20_MASTER_CLK>, 3292 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3293 <&gcc GCC_USB20_SLEEP_CLK>, 3294 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3295 clock-names = "cfg_noc", 3296 "core", 3297 "iface", 3298 "sleep", 3299 "mock_utmi"; 3300 3301 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3302 <&gcc GCC_USB20_MASTER_CLK>; 3303 assigned-clock-rates = <19200000>, <60000000>; 3304 3305 power-domains = <&gcc USB30_GDSC>; 3306 qcom,select-utmi-as-pipe-clk; 3307 status = "disabled"; 3308 3309 usb2_dwc3: usb@7600000 { 3310 compatible = "snps,dwc3"; 3311 reg = <0x07600000 0xcc00>; 3312 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 3313 phys = <&hsusb_phy2>; 3314 phy-names = "usb2-phy"; 3315 maximum-speed = "high-speed"; 3316 snps,dis_u2_susphy_quirk; 3317 snps,dis_enblslpm_quirk; 3318 }; 3319 }; 3320 3321 slimbam: dma-controller@9184000 { 3322 compatible = "qcom,bam-v1.7.0"; 3323 qcom,controlled-remotely; 3324 reg = <0x09184000 0x32000>; 3325 num-channels = <31>; 3326 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 3327 #dma-cells = <1>; 3328 qcom,ee = <1>; 3329 qcom,num-ees = <2>; 3330 }; 3331 3332 slim_msm: slim@91c0000 { 3333 compatible = "qcom,slim-ngd-v1.5.0"; 3334 reg = <0x091c0000 0x2C000>; 3335 reg-names = "ctrl"; 3336 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 3337 dmas = <&slimbam 3>, <&slimbam 4>, 3338 <&slimbam 5>, <&slimbam 6>; 3339 dma-names = "rx", "tx", "tx2", "rx2"; 3340 #address-cells = <1>; 3341 #size-cells = <0>; 3342 ngd@1 { 3343 reg = <1>; 3344 #address-cells = <1>; 3345 #size-cells = <1>; 3346 3347 tasha_ifd: tas-ifd { 3348 compatible = "slim217,1a0"; 3349 reg = <0 0>; 3350 }; 3351 3352 wcd9335: codec@1{ 3353 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 3354 pinctrl-names = "default"; 3355 3356 compatible = "slim217,1a0"; 3357 reg = <1 0>; 3358 3359 interrupt-parent = <&tlmm>; 3360 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 3361 <53 IRQ_TYPE_LEVEL_HIGH>; 3362 interrupt-names = "intr1", "intr2"; 3363 interrupt-controller; 3364 #interrupt-cells = <1>; 3365 reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; 3366 3367 slim-ifc-dev = <&tasha_ifd>; 3368 3369 #sound-dai-cells = <1>; 3370 }; 3371 }; 3372 }; 3373 3374 adsp_pil: remoteproc@9300000 { 3375 compatible = "qcom,msm8996-adsp-pil"; 3376 reg = <0x09300000 0x80000>; 3377 3378 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3379 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3380 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3381 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3382 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3383 interrupt-names = "wdog", "fatal", "ready", 3384 "handover", "stop-ack"; 3385 3386 clocks = <&rpmcc RPM_SMD_BB_CLK1>; 3387 clock-names = "xo"; 3388 3389 memory-region = <&adsp_mem>; 3390 3391 qcom,smem-states = <&adsp_smp2p_out 0>; 3392 qcom,smem-state-names = "stop"; 3393 3394 power-domains = <&rpmpd MSM8996_VDDCX>; 3395 power-domain-names = "cx"; 3396 3397 status = "disabled"; 3398 3399 smd-edge { 3400 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3401 3402 label = "lpass"; 3403 mboxes = <&apcs_glb 8>; 3404 qcom,smd-edge = <1>; 3405 qcom,remote-pid = <2>; 3406 #address-cells = <1>; 3407 #size-cells = <0>; 3408 apr { 3409 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3410 compatible = "qcom,apr-v2"; 3411 qcom,smd-channels = "apr_audio_svc"; 3412 qcom,domain = <APR_DOMAIN_ADSP>; 3413 #address-cells = <1>; 3414 #size-cells = <0>; 3415 3416 q6core { 3417 reg = <APR_SVC_ADSP_CORE>; 3418 compatible = "qcom,q6core"; 3419 }; 3420 3421 q6afe: q6afe { 3422 compatible = "qcom,q6afe"; 3423 reg = <APR_SVC_AFE>; 3424 q6afedai: dais { 3425 compatible = "qcom,q6afe-dais"; 3426 #address-cells = <1>; 3427 #size-cells = <0>; 3428 #sound-dai-cells = <1>; 3429 hdmi@1 { 3430 reg = <1>; 3431 }; 3432 }; 3433 }; 3434 3435 q6asm: q6asm { 3436 compatible = "qcom,q6asm"; 3437 reg = <APR_SVC_ASM>; 3438 q6asmdai: dais { 3439 compatible = "qcom,q6asm-dais"; 3440 #address-cells = <1>; 3441 #size-cells = <0>; 3442 #sound-dai-cells = <1>; 3443 iommus = <&lpass_q6_smmu 1>; 3444 }; 3445 }; 3446 3447 q6adm: q6adm { 3448 compatible = "qcom,q6adm"; 3449 reg = <APR_SVC_ADM>; 3450 q6routing: routing { 3451 compatible = "qcom,q6adm-routing"; 3452 #sound-dai-cells = <0>; 3453 }; 3454 }; 3455 }; 3456 3457 }; 3458 }; 3459 3460 apcs_glb: mailbox@9820000 { 3461 compatible = "qcom,msm8996-apcs-hmss-global"; 3462 reg = <0x09820000 0x1000>; 3463 3464 #mbox-cells = <1>; 3465 }; 3466 3467 timer@9840000 { 3468 #address-cells = <1>; 3469 #size-cells = <1>; 3470 ranges; 3471 compatible = "arm,armv7-timer-mem"; 3472 reg = <0x09840000 0x1000>; 3473 clock-frequency = <19200000>; 3474 3475 frame@9850000 { 3476 frame-number = <0>; 3477 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3479 reg = <0x09850000 0x1000>, 3480 <0x09860000 0x1000>; 3481 }; 3482 3483 frame@9870000 { 3484 frame-number = <1>; 3485 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3486 reg = <0x09870000 0x1000>; 3487 status = "disabled"; 3488 }; 3489 3490 frame@9880000 { 3491 frame-number = <2>; 3492 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3493 reg = <0x09880000 0x1000>; 3494 status = "disabled"; 3495 }; 3496 3497 frame@9890000 { 3498 frame-number = <3>; 3499 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3500 reg = <0x09890000 0x1000>; 3501 status = "disabled"; 3502 }; 3503 3504 frame@98a0000 { 3505 frame-number = <4>; 3506 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3507 reg = <0x098a0000 0x1000>; 3508 status = "disabled"; 3509 }; 3510 3511 frame@98b0000 { 3512 frame-number = <5>; 3513 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3514 reg = <0x098b0000 0x1000>; 3515 status = "disabled"; 3516 }; 3517 3518 frame@98c0000 { 3519 frame-number = <6>; 3520 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3521 reg = <0x098c0000 0x1000>; 3522 status = "disabled"; 3523 }; 3524 }; 3525 3526 saw3: syscon@9a10000 { 3527 compatible = "syscon"; 3528 reg = <0x09a10000 0x1000>; 3529 }; 3530 3531 intc: interrupt-controller@9bc0000 { 3532 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3533 #interrupt-cells = <3>; 3534 interrupt-controller; 3535 #redistributor-regions = <1>; 3536 redistributor-stride = <0x0 0x40000>; 3537 reg = <0x09bc0000 0x10000>, 3538 <0x09c00000 0x100000>; 3539 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3540 }; 3541 }; 3542 3543 sound: sound { 3544 }; 3545 3546 thermal-zones { 3547 cpu0-thermal { 3548 polling-delay-passive = <250>; 3549 polling-delay = <1000>; 3550 3551 thermal-sensors = <&tsens0 3>; 3552 3553 trips { 3554 cpu0_alert0: trip-point0 { 3555 temperature = <75000>; 3556 hysteresis = <2000>; 3557 type = "passive"; 3558 }; 3559 3560 cpu0_crit: cpu_crit { 3561 temperature = <110000>; 3562 hysteresis = <2000>; 3563 type = "critical"; 3564 }; 3565 }; 3566 }; 3567 3568 cpu1-thermal { 3569 polling-delay-passive = <250>; 3570 polling-delay = <1000>; 3571 3572 thermal-sensors = <&tsens0 5>; 3573 3574 trips { 3575 cpu1_alert0: trip-point0 { 3576 temperature = <75000>; 3577 hysteresis = <2000>; 3578 type = "passive"; 3579 }; 3580 3581 cpu1_crit: cpu_crit { 3582 temperature = <110000>; 3583 hysteresis = <2000>; 3584 type = "critical"; 3585 }; 3586 }; 3587 }; 3588 3589 cpu2-thermal { 3590 polling-delay-passive = <250>; 3591 polling-delay = <1000>; 3592 3593 thermal-sensors = <&tsens0 8>; 3594 3595 trips { 3596 cpu2_alert0: trip-point0 { 3597 temperature = <75000>; 3598 hysteresis = <2000>; 3599 type = "passive"; 3600 }; 3601 3602 cpu2_crit: cpu_crit { 3603 temperature = <110000>; 3604 hysteresis = <2000>; 3605 type = "critical"; 3606 }; 3607 }; 3608 }; 3609 3610 cpu3-thermal { 3611 polling-delay-passive = <250>; 3612 polling-delay = <1000>; 3613 3614 thermal-sensors = <&tsens0 10>; 3615 3616 trips { 3617 cpu3_alert0: trip-point0 { 3618 temperature = <75000>; 3619 hysteresis = <2000>; 3620 type = "passive"; 3621 }; 3622 3623 cpu3_crit: cpu_crit { 3624 temperature = <110000>; 3625 hysteresis = <2000>; 3626 type = "critical"; 3627 }; 3628 }; 3629 }; 3630 3631 gpu-top-thermal { 3632 polling-delay-passive = <250>; 3633 polling-delay = <1000>; 3634 3635 thermal-sensors = <&tsens1 6>; 3636 3637 trips { 3638 gpu1_alert0: trip-point0 { 3639 temperature = <90000>; 3640 hysteresis = <2000>; 3641 type = "passive"; 3642 }; 3643 }; 3644 3645 cooling-maps { 3646 map0 { 3647 trip = <&gpu1_alert0>; 3648 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3649 }; 3650 }; 3651 }; 3652 3653 gpu-bottom-thermal { 3654 polling-delay-passive = <250>; 3655 polling-delay = <1000>; 3656 3657 thermal-sensors = <&tsens1 7>; 3658 3659 trips { 3660 gpu2_alert0: trip-point0 { 3661 temperature = <90000>; 3662 hysteresis = <2000>; 3663 type = "passive"; 3664 }; 3665 }; 3666 3667 cooling-maps { 3668 map0 { 3669 trip = <&gpu2_alert0>; 3670 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3671 }; 3672 }; 3673 }; 3674 3675 m4m-thermal { 3676 polling-delay-passive = <250>; 3677 polling-delay = <1000>; 3678 3679 thermal-sensors = <&tsens0 1>; 3680 3681 trips { 3682 m4m_alert0: trip-point0 { 3683 temperature = <90000>; 3684 hysteresis = <2000>; 3685 type = "hot"; 3686 }; 3687 }; 3688 }; 3689 3690 l3-or-venus-thermal { 3691 polling-delay-passive = <250>; 3692 polling-delay = <1000>; 3693 3694 thermal-sensors = <&tsens0 2>; 3695 3696 trips { 3697 l3_or_venus_alert0: trip-point0 { 3698 temperature = <90000>; 3699 hysteresis = <2000>; 3700 type = "hot"; 3701 }; 3702 }; 3703 }; 3704 3705 cluster0-l2-thermal { 3706 polling-delay-passive = <250>; 3707 polling-delay = <1000>; 3708 3709 thermal-sensors = <&tsens0 7>; 3710 3711 trips { 3712 cluster0_l2_alert0: trip-point0 { 3713 temperature = <90000>; 3714 hysteresis = <2000>; 3715 type = "hot"; 3716 }; 3717 }; 3718 }; 3719 3720 cluster1-l2-thermal { 3721 polling-delay-passive = <250>; 3722 polling-delay = <1000>; 3723 3724 thermal-sensors = <&tsens0 12>; 3725 3726 trips { 3727 cluster1_l2_alert0: trip-point0 { 3728 temperature = <90000>; 3729 hysteresis = <2000>; 3730 type = "hot"; 3731 }; 3732 }; 3733 }; 3734 3735 camera-thermal { 3736 polling-delay-passive = <250>; 3737 polling-delay = <1000>; 3738 3739 thermal-sensors = <&tsens1 1>; 3740 3741 trips { 3742 camera_alert0: trip-point0 { 3743 temperature = <90000>; 3744 hysteresis = <2000>; 3745 type = "hot"; 3746 }; 3747 }; 3748 }; 3749 3750 q6-dsp-thermal { 3751 polling-delay-passive = <250>; 3752 polling-delay = <1000>; 3753 3754 thermal-sensors = <&tsens1 2>; 3755 3756 trips { 3757 q6_dsp_alert0: trip-point0 { 3758 temperature = <90000>; 3759 hysteresis = <2000>; 3760 type = "hot"; 3761 }; 3762 }; 3763 }; 3764 3765 mem-thermal { 3766 polling-delay-passive = <250>; 3767 polling-delay = <1000>; 3768 3769 thermal-sensors = <&tsens1 3>; 3770 3771 trips { 3772 mem_alert0: trip-point0 { 3773 temperature = <90000>; 3774 hysteresis = <2000>; 3775 type = "hot"; 3776 }; 3777 }; 3778 }; 3779 3780 modemtx-thermal { 3781 polling-delay-passive = <250>; 3782 polling-delay = <1000>; 3783 3784 thermal-sensors = <&tsens1 4>; 3785 3786 trips { 3787 modemtx_alert0: trip-point0 { 3788 temperature = <90000>; 3789 hysteresis = <2000>; 3790 type = "hot"; 3791 }; 3792 }; 3793 }; 3794 }; 3795 3796 timer { 3797 compatible = "arm,armv8-timer"; 3798 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3799 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3800 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3801 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3802 }; 3803}; 3804