1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <dt-bindings/arm/coresight-cti-dt.h>
7#include <dt-bindings/clock/qcom,gcc-msm8916.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/interconnect/qcom,msm8916.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/power/qcom-rpmpd.h>
12#include <dt-bindings/reset/qcom,gcc-msm8916.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&intc>;
17
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		mmc0 = &sdhc_1; /* SDC1 eMMC slot */
23		mmc1 = &sdhc_2; /* SDC2 SD card slot */
24	};
25
26	chosen { };
27
28	memory@80000000 {
29		device_type = "memory";
30		/* We expect the bootloader to fill in the reg */
31		reg = <0 0x80000000 0 0>;
32	};
33
34	reserved-memory {
35		#address-cells = <2>;
36		#size-cells = <2>;
37		ranges;
38
39		tz-apps@86000000 {
40			reg = <0x0 0x86000000 0x0 0x300000>;
41			no-map;
42		};
43
44		smem@86300000 {
45			compatible = "qcom,smem";
46			reg = <0x0 0x86300000 0x0 0x100000>;
47			no-map;
48
49			hwlocks = <&tcsr_mutex 3>;
50			qcom,rpm-msg-ram = <&rpm_msg_ram>;
51		};
52
53		hypervisor@86400000 {
54			reg = <0x0 0x86400000 0x0 0x100000>;
55			no-map;
56		};
57
58		tz@86500000 {
59			reg = <0x0 0x86500000 0x0 0x180000>;
60			no-map;
61		};
62
63		reserved@86680000 {
64			reg = <0x0 0x86680000 0x0 0x80000>;
65			no-map;
66		};
67
68		rmtfs@86700000 {
69			compatible = "qcom,rmtfs-mem";
70			reg = <0x0 0x86700000 0x0 0xe0000>;
71			no-map;
72
73			qcom,client-id = <1>;
74		};
75
76		rfsa@867e0000 {
77			reg = <0x0 0x867e0000 0x0 0x20000>;
78			no-map;
79		};
80
81		mpss_mem: mpss@86800000 {
82			reg = <0x0 0x86800000 0x0 0x2b00000>;
83			no-map;
84		};
85
86		wcnss_mem: wcnss@89300000 {
87			reg = <0x0 0x89300000 0x0 0x600000>;
88			no-map;
89		};
90
91		venus_mem: venus@89900000 {
92			reg = <0x0 0x89900000 0x0 0x600000>;
93			no-map;
94		};
95
96		mba_mem: mba@8ea00000 {
97			no-map;
98			reg = <0 0x8ea00000 0 0x100000>;
99		};
100	};
101
102	clocks {
103		xo_board: xo-board {
104			compatible = "fixed-clock";
105			#clock-cells = <0>;
106			clock-frequency = <19200000>;
107		};
108
109		sleep_clk: sleep-clk {
110			compatible = "fixed-clock";
111			#clock-cells = <0>;
112			clock-frequency = <32768>;
113		};
114	};
115
116	cpus {
117		#address-cells = <1>;
118		#size-cells = <0>;
119
120		CPU0: cpu@0 {
121			device_type = "cpu";
122			compatible = "arm,cortex-a53";
123			reg = <0x0>;
124			next-level-cache = <&L2_0>;
125			enable-method = "psci";
126			clocks = <&apcs>;
127			operating-points-v2 = <&cpu_opp_table>;
128			#cooling-cells = <2>;
129			power-domains = <&CPU_PD0>;
130			power-domain-names = "psci";
131			qcom,acc = <&cpu0_acc>;
132			qcom,saw = <&cpu0_saw>;
133		};
134
135		CPU1: cpu@1 {
136			device_type = "cpu";
137			compatible = "arm,cortex-a53";
138			reg = <0x1>;
139			next-level-cache = <&L2_0>;
140			enable-method = "psci";
141			clocks = <&apcs>;
142			operating-points-v2 = <&cpu_opp_table>;
143			#cooling-cells = <2>;
144			power-domains = <&CPU_PD1>;
145			power-domain-names = "psci";
146			qcom,acc = <&cpu1_acc>;
147			qcom,saw = <&cpu1_saw>;
148		};
149
150		CPU2: cpu@2 {
151			device_type = "cpu";
152			compatible = "arm,cortex-a53";
153			reg = <0x2>;
154			next-level-cache = <&L2_0>;
155			enable-method = "psci";
156			clocks = <&apcs>;
157			operating-points-v2 = <&cpu_opp_table>;
158			#cooling-cells = <2>;
159			power-domains = <&CPU_PD2>;
160			power-domain-names = "psci";
161			qcom,acc = <&cpu2_acc>;
162			qcom,saw = <&cpu2_saw>;
163		};
164
165		CPU3: cpu@3 {
166			device_type = "cpu";
167			compatible = "arm,cortex-a53";
168			reg = <0x3>;
169			next-level-cache = <&L2_0>;
170			enable-method = "psci";
171			clocks = <&apcs>;
172			operating-points-v2 = <&cpu_opp_table>;
173			#cooling-cells = <2>;
174			power-domains = <&CPU_PD3>;
175			power-domain-names = "psci";
176			qcom,acc = <&cpu3_acc>;
177			qcom,saw = <&cpu3_saw>;
178		};
179
180		L2_0: l2-cache {
181			compatible = "cache";
182			cache-level = <2>;
183		};
184
185		idle-states {
186			entry-method = "psci";
187
188			CPU_SLEEP_0: cpu-sleep-0 {
189				compatible = "arm,idle-state";
190				idle-state-name = "standalone-power-collapse";
191				arm,psci-suspend-param = <0x40000002>;
192				entry-latency-us = <130>;
193				exit-latency-us = <150>;
194				min-residency-us = <2000>;
195				local-timer-stop;
196			};
197		};
198
199		domain-idle-states {
200
201			CLUSTER_RET: cluster-retention {
202				compatible = "domain-idle-state";
203				arm,psci-suspend-param = <0x41000012>;
204				entry-latency-us = <500>;
205				exit-latency-us = <500>;
206				min-residency-us = <2000>;
207			};
208
209			CLUSTER_PWRDN: cluster-gdhs {
210				compatible = "domain-idle-state";
211				arm,psci-suspend-param = <0x41000032>;
212				entry-latency-us = <2000>;
213				exit-latency-us = <2000>;
214				min-residency-us = <6000>;
215			};
216		};
217	};
218
219	cpu_opp_table: cpu-opp-table {
220		compatible = "operating-points-v2";
221		opp-shared;
222
223		opp-200000000 {
224			opp-hz = /bits/ 64 <200000000>;
225		};
226		opp-400000000 {
227			opp-hz = /bits/ 64 <400000000>;
228		};
229		opp-800000000 {
230			opp-hz = /bits/ 64 <800000000>;
231		};
232		opp-998400000 {
233			opp-hz = /bits/ 64 <998400000>;
234		};
235	};
236
237	firmware {
238		scm: scm {
239			compatible = "qcom,scm-msm8916", "qcom,scm";
240			clocks = <&gcc GCC_CRYPTO_CLK>,
241				 <&gcc GCC_CRYPTO_AXI_CLK>,
242				 <&gcc GCC_CRYPTO_AHB_CLK>;
243			clock-names = "core", "bus", "iface";
244			#reset-cells = <1>;
245
246			qcom,dload-mode = <&tcsr 0x6100>;
247		};
248	};
249
250	pmu {
251		compatible = "arm,cortex-a53-pmu";
252		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
253	};
254
255	psci {
256		compatible = "arm,psci-1.0";
257		method = "smc";
258
259		CPU_PD0: power-domain-cpu0 {
260			#power-domain-cells = <0>;
261			power-domains = <&CLUSTER_PD>;
262			domain-idle-states = <&CPU_SLEEP_0>;
263		};
264
265		CPU_PD1: power-domain-cpu1 {
266			#power-domain-cells = <0>;
267			power-domains = <&CLUSTER_PD>;
268			domain-idle-states = <&CPU_SLEEP_0>;
269		};
270
271		CPU_PD2: power-domain-cpu2 {
272			#power-domain-cells = <0>;
273			power-domains = <&CLUSTER_PD>;
274			domain-idle-states = <&CPU_SLEEP_0>;
275		};
276
277		CPU_PD3: power-domain-cpu3 {
278			#power-domain-cells = <0>;
279			power-domains = <&CLUSTER_PD>;
280			domain-idle-states = <&CPU_SLEEP_0>;
281		};
282
283		CLUSTER_PD: power-domain-cluster {
284			#power-domain-cells = <0>;
285			domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
286		};
287	};
288
289	smd {
290		compatible = "qcom,smd";
291
292		rpm {
293			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
294			qcom,ipc = <&apcs 8 0>;
295			qcom,smd-edge = <15>;
296
297			rpm_requests: rpm-requests {
298				compatible = "qcom,rpm-msm8916";
299				qcom,smd-channels = "rpm_requests";
300
301				rpmcc: clock-controller {
302					compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
303					#clock-cells = <1>;
304				};
305
306				rpmpd: power-controller {
307					compatible = "qcom,msm8916-rpmpd";
308					#power-domain-cells = <1>;
309					operating-points-v2 = <&rpmpd_opp_table>;
310
311					rpmpd_opp_table: opp-table {
312						compatible = "operating-points-v2";
313
314						rpmpd_opp_ret: opp1 {
315							opp-level = <1>;
316						};
317						rpmpd_opp_svs_krait: opp2 {
318							opp-level = <2>;
319						};
320						rpmpd_opp_svs_soc: opp3 {
321							opp-level = <3>;
322						};
323						rpmpd_opp_nom: opp4 {
324							opp-level = <4>;
325						};
326						rpmpd_opp_turbo: opp5 {
327							opp-level = <5>;
328						};
329						rpmpd_opp_super_turbo: opp6 {
330							opp-level = <6>;
331						};
332					};
333				};
334			};
335		};
336	};
337
338	smp2p-hexagon {
339		compatible = "qcom,smp2p";
340		qcom,smem = <435>, <428>;
341
342		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
343
344		qcom,ipc = <&apcs 8 14>;
345
346		qcom,local-pid = <0>;
347		qcom,remote-pid = <1>;
348
349		hexagon_smp2p_out: master-kernel {
350			qcom,entry-name = "master-kernel";
351
352			#qcom,smem-state-cells = <1>;
353		};
354
355		hexagon_smp2p_in: slave-kernel {
356			qcom,entry-name = "slave-kernel";
357
358			interrupt-controller;
359			#interrupt-cells = <2>;
360		};
361	};
362
363	smp2p-wcnss {
364		compatible = "qcom,smp2p";
365		qcom,smem = <451>, <431>;
366
367		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
368
369		qcom,ipc = <&apcs 8 18>;
370
371		qcom,local-pid = <0>;
372		qcom,remote-pid = <4>;
373
374		wcnss_smp2p_out: master-kernel {
375			qcom,entry-name = "master-kernel";
376
377			#qcom,smem-state-cells = <1>;
378		};
379
380		wcnss_smp2p_in: slave-kernel {
381			qcom,entry-name = "slave-kernel";
382
383			interrupt-controller;
384			#interrupt-cells = <2>;
385		};
386	};
387
388	smsm {
389		compatible = "qcom,smsm";
390
391		#address-cells = <1>;
392		#size-cells = <0>;
393
394		qcom,ipc-1 = <&apcs 8 13>;
395		qcom,ipc-3 = <&apcs 8 19>;
396
397		apps_smsm: apps@0 {
398			reg = <0>;
399
400			#qcom,smem-state-cells = <1>;
401		};
402
403		hexagon_smsm: hexagon@1 {
404			reg = <1>;
405			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
406
407			interrupt-controller;
408			#interrupt-cells = <2>;
409		};
410
411		wcnss_smsm: wcnss@6 {
412			reg = <6>;
413			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
414
415			interrupt-controller;
416			#interrupt-cells = <2>;
417		};
418	};
419
420	soc: soc@0 {
421		#address-cells = <1>;
422		#size-cells = <1>;
423		ranges = <0 0 0 0xffffffff>;
424		compatible = "simple-bus";
425
426		rng@22000 {
427			compatible = "qcom,prng";
428			reg = <0x00022000 0x200>;
429			clocks = <&gcc GCC_PRNG_AHB_CLK>;
430			clock-names = "core";
431		};
432
433		restart@4ab000 {
434			compatible = "qcom,pshold";
435			reg = <0x004ab000 0x4>;
436		};
437
438		qfprom: qfprom@5c000 {
439			compatible = "qcom,qfprom";
440			reg = <0x0005c000 0x1000>;
441			#address-cells = <1>;
442			#size-cells = <1>;
443			tsens_caldata: caldata@d0 {
444				reg = <0xd0 0x8>;
445			};
446			tsens_calsel: calsel@ec {
447				reg = <0xec 0x4>;
448			};
449		};
450
451		rpm_msg_ram: sram@60000 {
452			compatible = "qcom,rpm-msg-ram";
453			reg = <0x00060000 0x8000>;
454		};
455
456		sram@290000 {
457			compatible = "qcom,msm8916-rpm-stats";
458			reg = <0x00290000 0x10000>;
459		};
460
461		bimc: interconnect@400000 {
462			compatible = "qcom,msm8916-bimc";
463			reg = <0x00400000 0x62000>;
464			#interconnect-cells = <1>;
465			clock-names = "bus", "bus_a";
466			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
467				 <&rpmcc RPM_SMD_BIMC_A_CLK>;
468		};
469
470		tsens: thermal-sensor@4a9000 {
471			compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
472			reg = <0x004a9000 0x1000>, /* TM */
473			      <0x004a8000 0x1000>; /* SROT */
474			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
475			nvmem-cell-names = "calib", "calib_sel";
476			#qcom,sensors = <5>;
477			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
478			interrupt-names = "uplow";
479			#thermal-sensor-cells = <1>;
480		};
481
482		pcnoc: interconnect@500000 {
483			compatible = "qcom,msm8916-pcnoc";
484			reg = <0x00500000 0x11000>;
485			#interconnect-cells = <1>;
486			clock-names = "bus", "bus_a";
487			clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
488				 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
489		};
490
491		snoc: interconnect@580000 {
492			compatible = "qcom,msm8916-snoc";
493			reg = <0x00580000 0x14000>;
494			#interconnect-cells = <1>;
495			clock-names = "bus", "bus_a";
496			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
497				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
498		};
499
500		stm: stm@802000 {
501			compatible = "arm,coresight-stm", "arm,primecell";
502			reg = <0x00802000 0x1000>,
503			      <0x09280000 0x180000>;
504			reg-names = "stm-base", "stm-stimulus-base";
505
506			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
507			clock-names = "apb_pclk", "atclk";
508
509			status = "disabled";
510
511			out-ports {
512				port {
513					stm_out: endpoint {
514						remote-endpoint = <&funnel0_in7>;
515					};
516				};
517			};
518		};
519
520		/* System CTIs */
521		/* CTI 0 - TMC connections */
522		cti0: cti@810000 {
523			compatible = "arm,coresight-cti", "arm,primecell";
524			reg = <0x00810000 0x1000>;
525
526			clocks = <&rpmcc RPM_QDSS_CLK>;
527			clock-names = "apb_pclk";
528
529			status = "disabled";
530		};
531
532		/* CTI 1 - TPIU connections */
533		cti1: cti@811000 {
534			compatible = "arm,coresight-cti", "arm,primecell";
535			reg = <0x00811000 0x1000>;
536
537			clocks = <&rpmcc RPM_QDSS_CLK>;
538			clock-names = "apb_pclk";
539
540			status = "disabled";
541		};
542
543		/* CTIs 2-11 - no information - not instantiated */
544
545		tpiu: tpiu@820000 {
546			compatible = "arm,coresight-tpiu", "arm,primecell";
547			reg = <0x00820000 0x1000>;
548
549			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
550			clock-names = "apb_pclk", "atclk";
551
552			status = "disabled";
553
554			in-ports {
555				port {
556					tpiu_in: endpoint {
557						remote-endpoint = <&replicator_out1>;
558					};
559				};
560			};
561		};
562
563		funnel0: funnel@821000 {
564			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
565			reg = <0x00821000 0x1000>;
566
567			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
568			clock-names = "apb_pclk", "atclk";
569
570			status = "disabled";
571
572			in-ports {
573				#address-cells = <1>;
574				#size-cells = <0>;
575
576				/*
577				 * Not described input ports:
578				 * 0 - connected to Resource and Power Manger CPU ETM
579				 * 1 - not-connected
580				 * 2 - connected to Modem CPU ETM
581				 * 3 - not-connected
582				 * 5 - not-connected
583				 * 6 - connected trought funnel to Wireless CPU ETM
584				 * 7 - connected to STM component
585				 */
586
587				port@4 {
588					reg = <4>;
589					funnel0_in4: endpoint {
590						remote-endpoint = <&funnel1_out>;
591					};
592				};
593
594				port@7 {
595					reg = <7>;
596					funnel0_in7: endpoint {
597						remote-endpoint = <&stm_out>;
598					};
599				};
600			};
601
602			out-ports {
603				port {
604					funnel0_out: endpoint {
605						remote-endpoint = <&etf_in>;
606					};
607				};
608			};
609		};
610
611		replicator: replicator@824000 {
612			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
613			reg = <0x00824000 0x1000>;
614
615			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
616			clock-names = "apb_pclk", "atclk";
617
618			status = "disabled";
619
620			out-ports {
621				#address-cells = <1>;
622				#size-cells = <0>;
623
624				port@0 {
625					reg = <0>;
626					replicator_out0: endpoint {
627						remote-endpoint = <&etr_in>;
628					};
629				};
630				port@1 {
631					reg = <1>;
632					replicator_out1: endpoint {
633						remote-endpoint = <&tpiu_in>;
634					};
635				};
636			};
637
638			in-ports {
639				port {
640					replicator_in: endpoint {
641						remote-endpoint = <&etf_out>;
642					};
643				};
644			};
645		};
646
647		etf: etf@825000 {
648			compatible = "arm,coresight-tmc", "arm,primecell";
649			reg = <0x00825000 0x1000>;
650
651			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
652			clock-names = "apb_pclk", "atclk";
653
654			status = "disabled";
655
656			in-ports {
657				port {
658					etf_in: endpoint {
659						remote-endpoint = <&funnel0_out>;
660					};
661				};
662			};
663
664			out-ports {
665				port {
666					etf_out: endpoint {
667						remote-endpoint = <&replicator_in>;
668					};
669				};
670			};
671		};
672
673		etr: etr@826000 {
674			compatible = "arm,coresight-tmc", "arm,primecell";
675			reg = <0x00826000 0x1000>;
676
677			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
678			clock-names = "apb_pclk", "atclk";
679
680			status = "disabled";
681
682			in-ports {
683				port {
684					etr_in: endpoint {
685						remote-endpoint = <&replicator_out0>;
686					};
687				};
688			};
689		};
690
691		funnel1: funnel@841000 {	/* APSS funnel only 4 inputs are used */
692			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
693			reg = <0x00841000 0x1000>;
694
695			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
696			clock-names = "apb_pclk", "atclk";
697
698			status = "disabled";
699
700			in-ports {
701				#address-cells = <1>;
702				#size-cells = <0>;
703
704				port@0 {
705					reg = <0>;
706					funnel1_in0: endpoint {
707						remote-endpoint = <&etm0_out>;
708					};
709				};
710				port@1 {
711					reg = <1>;
712					funnel1_in1: endpoint {
713						remote-endpoint = <&etm1_out>;
714					};
715				};
716				port@2 {
717					reg = <2>;
718					funnel1_in2: endpoint {
719						remote-endpoint = <&etm2_out>;
720					};
721				};
722				port@3 {
723					reg = <3>;
724					funnel1_in3: endpoint {
725						remote-endpoint = <&etm3_out>;
726					};
727				};
728			};
729
730			out-ports {
731				port {
732					funnel1_out: endpoint {
733						remote-endpoint = <&funnel0_in4>;
734					};
735				};
736			};
737		};
738
739		debug0: debug@850000 {
740			compatible = "arm,coresight-cpu-debug", "arm,primecell";
741			reg = <0x00850000 0x1000>;
742			clocks = <&rpmcc RPM_QDSS_CLK>;
743			clock-names = "apb_pclk";
744			cpu = <&CPU0>;
745			status = "disabled";
746		};
747
748		debug1: debug@852000 {
749			compatible = "arm,coresight-cpu-debug", "arm,primecell";
750			reg = <0x00852000 0x1000>;
751			clocks = <&rpmcc RPM_QDSS_CLK>;
752			clock-names = "apb_pclk";
753			cpu = <&CPU1>;
754			status = "disabled";
755		};
756
757		debug2: debug@854000 {
758			compatible = "arm,coresight-cpu-debug", "arm,primecell";
759			reg = <0x00854000 0x1000>;
760			clocks = <&rpmcc RPM_QDSS_CLK>;
761			clock-names = "apb_pclk";
762			cpu = <&CPU2>;
763			status = "disabled";
764		};
765
766		debug3: debug@856000 {
767			compatible = "arm,coresight-cpu-debug", "arm,primecell";
768			reg = <0x00856000 0x1000>;
769			clocks = <&rpmcc RPM_QDSS_CLK>;
770			clock-names = "apb_pclk";
771			cpu = <&CPU3>;
772			status = "disabled";
773		};
774
775		/* Core CTIs; CTIs 12-15 */
776		/* CTI - CPU-0 */
777		cti12: cti@858000 {
778			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
779				     "arm,primecell";
780			reg = <0x00858000 0x1000>;
781
782			clocks = <&rpmcc RPM_QDSS_CLK>;
783			clock-names = "apb_pclk";
784
785			cpu = <&CPU0>;
786			arm,cs-dev-assoc = <&etm0>;
787
788			status = "disabled";
789		};
790
791		/* CTI - CPU-1 */
792		cti13: cti@859000 {
793			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
794				     "arm,primecell";
795			reg = <0x00859000 0x1000>;
796
797			clocks = <&rpmcc RPM_QDSS_CLK>;
798			clock-names = "apb_pclk";
799
800			cpu = <&CPU1>;
801			arm,cs-dev-assoc = <&etm1>;
802
803			status = "disabled";
804		};
805
806		/* CTI - CPU-2 */
807		cti14: cti@85a000 {
808			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
809				     "arm,primecell";
810			reg = <0x0085a000 0x1000>;
811
812			clocks = <&rpmcc RPM_QDSS_CLK>;
813			clock-names = "apb_pclk";
814
815			cpu = <&CPU2>;
816			arm,cs-dev-assoc = <&etm2>;
817
818			status = "disabled";
819		};
820
821		/* CTI - CPU-3 */
822		cti15: cti@85b000 {
823			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
824				     "arm,primecell";
825			reg = <0x0085b000 0x1000>;
826
827			clocks = <&rpmcc RPM_QDSS_CLK>;
828			clock-names = "apb_pclk";
829
830			cpu = <&CPU3>;
831			arm,cs-dev-assoc = <&etm3>;
832
833			status = "disabled";
834		};
835
836		etm0: etm@85c000 {
837			compatible = "arm,coresight-etm4x", "arm,primecell";
838			reg = <0x0085c000 0x1000>;
839
840			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
841			clock-names = "apb_pclk", "atclk";
842			arm,coresight-loses-context-with-cpu;
843
844			cpu = <&CPU0>;
845
846			status = "disabled";
847
848			out-ports {
849				port {
850					etm0_out: endpoint {
851						remote-endpoint = <&funnel1_in0>;
852					};
853				};
854			};
855		};
856
857		etm1: etm@85d000 {
858			compatible = "arm,coresight-etm4x", "arm,primecell";
859			reg = <0x0085d000 0x1000>;
860
861			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
862			clock-names = "apb_pclk", "atclk";
863			arm,coresight-loses-context-with-cpu;
864
865			cpu = <&CPU1>;
866
867			status = "disabled";
868
869			out-ports {
870				port {
871					etm1_out: endpoint {
872						remote-endpoint = <&funnel1_in1>;
873					};
874				};
875			};
876		};
877
878		etm2: etm@85e000 {
879			compatible = "arm,coresight-etm4x", "arm,primecell";
880			reg = <0x0085e000 0x1000>;
881
882			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
883			clock-names = "apb_pclk", "atclk";
884			arm,coresight-loses-context-with-cpu;
885
886			cpu = <&CPU2>;
887
888			status = "disabled";
889
890			out-ports {
891				port {
892					etm2_out: endpoint {
893						remote-endpoint = <&funnel1_in2>;
894					};
895				};
896			};
897		};
898
899		etm3: etm@85f000 {
900			compatible = "arm,coresight-etm4x", "arm,primecell";
901			reg = <0x0085f000 0x1000>;
902
903			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
904			clock-names = "apb_pclk", "atclk";
905			arm,coresight-loses-context-with-cpu;
906
907			cpu = <&CPU3>;
908
909			status = "disabled";
910
911			out-ports {
912				port {
913					etm3_out: endpoint {
914						remote-endpoint = <&funnel1_in3>;
915					};
916				};
917			};
918		};
919
920		msmgpio: pinctrl@1000000 {
921			compatible = "qcom,msm8916-pinctrl";
922			reg = <0x01000000 0x300000>;
923			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
924			gpio-controller;
925			gpio-ranges = <&msmgpio 0 0 122>;
926			#gpio-cells = <2>;
927			interrupt-controller;
928			#interrupt-cells = <2>;
929		};
930
931		gcc: clock-controller@1800000 {
932			compatible = "qcom,gcc-msm8916";
933			#clock-cells = <1>;
934			#reset-cells = <1>;
935			#power-domain-cells = <1>;
936			reg = <0x01800000 0x80000>;
937		};
938
939		tcsr_mutex: hwlock@1905000 {
940			compatible = "qcom,tcsr-mutex";
941			reg = <0x01905000 0x20000>;
942			#hwlock-cells = <1>;
943		};
944
945		tcsr: syscon@1937000 {
946			compatible = "qcom,tcsr-msm8916", "syscon";
947			reg = <0x01937000 0x30000>;
948		};
949
950		mdss: mdss@1a00000 {
951			status = "disabled";
952			compatible = "qcom,mdss";
953			reg = <0x01a00000 0x1000>,
954			      <0x01ac8000 0x3000>;
955			reg-names = "mdss_phys", "vbif_phys";
956
957			power-domains = <&gcc MDSS_GDSC>;
958
959			clocks = <&gcc GCC_MDSS_AHB_CLK>,
960				 <&gcc GCC_MDSS_AXI_CLK>,
961				 <&gcc GCC_MDSS_VSYNC_CLK>;
962			clock-names = "iface",
963				      "bus",
964				      "vsync";
965
966			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
967
968			interrupt-controller;
969			#interrupt-cells = <1>;
970
971			#address-cells = <1>;
972			#size-cells = <1>;
973			ranges;
974
975			mdp: mdp@1a01000 {
976				compatible = "qcom,mdp5";
977				reg = <0x01a01000 0x89000>;
978				reg-names = "mdp_phys";
979
980				interrupt-parent = <&mdss>;
981				interrupts = <0>;
982
983				clocks = <&gcc GCC_MDSS_AHB_CLK>,
984					 <&gcc GCC_MDSS_AXI_CLK>,
985					 <&gcc GCC_MDSS_MDP_CLK>,
986					 <&gcc GCC_MDSS_VSYNC_CLK>;
987				clock-names = "iface",
988					      "bus",
989					      "core",
990					      "vsync";
991
992				iommus = <&apps_iommu 4>;
993
994				ports {
995					#address-cells = <1>;
996					#size-cells = <0>;
997
998					port@0 {
999						reg = <0>;
1000						mdp5_intf1_out: endpoint {
1001							remote-endpoint = <&dsi0_in>;
1002						};
1003					};
1004				};
1005			};
1006
1007			dsi0: dsi@1a98000 {
1008				compatible = "qcom,mdss-dsi-ctrl";
1009				reg = <0x01a98000 0x25c>;
1010				reg-names = "dsi_ctrl";
1011
1012				interrupt-parent = <&mdss>;
1013				interrupts = <4>;
1014
1015				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1016						  <&gcc PCLK0_CLK_SRC>;
1017				assigned-clock-parents = <&dsi_phy0 0>,
1018							 <&dsi_phy0 1>;
1019
1020				clocks = <&gcc GCC_MDSS_MDP_CLK>,
1021					 <&gcc GCC_MDSS_AHB_CLK>,
1022					 <&gcc GCC_MDSS_AXI_CLK>,
1023					 <&gcc GCC_MDSS_BYTE0_CLK>,
1024					 <&gcc GCC_MDSS_PCLK0_CLK>,
1025					 <&gcc GCC_MDSS_ESC0_CLK>;
1026				clock-names = "mdp_core",
1027					      "iface",
1028					      "bus",
1029					      "byte",
1030					      "pixel",
1031					      "core";
1032				phys = <&dsi_phy0>;
1033				phy-names = "dsi-phy";
1034
1035				#address-cells = <1>;
1036				#size-cells = <0>;
1037
1038				ports {
1039					#address-cells = <1>;
1040					#size-cells = <0>;
1041
1042					port@0 {
1043						reg = <0>;
1044						dsi0_in: endpoint {
1045							remote-endpoint = <&mdp5_intf1_out>;
1046						};
1047					};
1048
1049					port@1 {
1050						reg = <1>;
1051						dsi0_out: endpoint {
1052						};
1053					};
1054				};
1055			};
1056
1057			dsi_phy0: dsi-phy@1a98300 {
1058				compatible = "qcom,dsi-phy-28nm-lp";
1059				reg = <0x01a98300 0xd4>,
1060				      <0x01a98500 0x280>,
1061				      <0x01a98780 0x30>;
1062				reg-names = "dsi_pll",
1063					    "dsi_phy",
1064					    "dsi_phy_regulator";
1065
1066				#clock-cells = <1>;
1067				#phy-cells = <0>;
1068
1069				clocks = <&gcc GCC_MDSS_AHB_CLK>,
1070					 <&xo_board>;
1071				clock-names = "iface", "ref";
1072			};
1073		};
1074
1075		camss: camss@1b00000 {
1076			compatible = "qcom,msm8916-camss";
1077			reg = <0x01b0ac00 0x200>,
1078				<0x01b00030 0x4>,
1079				<0x01b0b000 0x200>,
1080				<0x01b00038 0x4>,
1081				<0x01b08000 0x100>,
1082				<0x01b08400 0x100>,
1083				<0x01b0a000 0x500>,
1084				<0x01b00020 0x10>,
1085				<0x01b10000 0x1000>;
1086			reg-names = "csiphy0",
1087				"csiphy0_clk_mux",
1088				"csiphy1",
1089				"csiphy1_clk_mux",
1090				"csid0",
1091				"csid1",
1092				"ispif",
1093				"csi_clk_mux",
1094				"vfe0";
1095			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1096				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1097				<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1098				<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1099				<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1100				<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1101			interrupt-names = "csiphy0",
1102				"csiphy1",
1103				"csid0",
1104				"csid1",
1105				"ispif",
1106				"vfe0";
1107			power-domains = <&gcc VFE_GDSC>;
1108			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1109				<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1110				<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1111				<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1112				<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1113				<&gcc GCC_CAMSS_CSI0_CLK>,
1114				<&gcc GCC_CAMSS_CSI0PHY_CLK>,
1115				<&gcc GCC_CAMSS_CSI0PIX_CLK>,
1116				<&gcc GCC_CAMSS_CSI0RDI_CLK>,
1117				<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1118				<&gcc GCC_CAMSS_CSI1_CLK>,
1119				<&gcc GCC_CAMSS_CSI1PHY_CLK>,
1120				<&gcc GCC_CAMSS_CSI1PIX_CLK>,
1121				<&gcc GCC_CAMSS_CSI1RDI_CLK>,
1122				<&gcc GCC_CAMSS_AHB_CLK>,
1123				<&gcc GCC_CAMSS_VFE0_CLK>,
1124				<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1125				<&gcc GCC_CAMSS_VFE_AHB_CLK>,
1126				<&gcc GCC_CAMSS_VFE_AXI_CLK>;
1127			clock-names = "top_ahb",
1128				"ispif_ahb",
1129				"csiphy0_timer",
1130				"csiphy1_timer",
1131				"csi0_ahb",
1132				"csi0",
1133				"csi0_phy",
1134				"csi0_pix",
1135				"csi0_rdi",
1136				"csi1_ahb",
1137				"csi1",
1138				"csi1_phy",
1139				"csi1_pix",
1140				"csi1_rdi",
1141				"ahb",
1142				"vfe0",
1143				"csi_vfe0",
1144				"vfe_ahb",
1145				"vfe_axi";
1146			iommus = <&apps_iommu 3>;
1147			status = "disabled";
1148			ports {
1149				#address-cells = <1>;
1150				#size-cells = <0>;
1151			};
1152		};
1153
1154		cci: cci@1b0c000 {
1155			compatible = "qcom,msm8916-cci";
1156			#address-cells = <1>;
1157			#size-cells = <0>;
1158			reg = <0x01b0c000 0x1000>;
1159			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1160			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1161				<&gcc GCC_CAMSS_CCI_AHB_CLK>,
1162				<&gcc GCC_CAMSS_CCI_CLK>,
1163				<&gcc GCC_CAMSS_AHB_CLK>;
1164			clock-names = "camss_top_ahb", "cci_ahb",
1165					  "cci", "camss_ahb";
1166			assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1167					  <&gcc GCC_CAMSS_CCI_CLK>;
1168			assigned-clock-rates = <80000000>, <19200000>;
1169			pinctrl-names = "default";
1170			pinctrl-0 = <&cci0_default>;
1171			status = "disabled";
1172
1173			cci_i2c0: i2c-bus@0 {
1174				reg = <0>;
1175				clock-frequency = <400000>;
1176				#address-cells = <1>;
1177				#size-cells = <0>;
1178			};
1179		};
1180
1181		gpu@1c00000 {
1182			compatible = "qcom,adreno-306.0", "qcom,adreno";
1183			reg = <0x01c00000 0x20000>;
1184			reg-names = "kgsl_3d0_reg_memory";
1185			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1186			interrupt-names = "kgsl_3d0_irq";
1187			clock-names =
1188			    "core",
1189			    "iface",
1190			    "mem",
1191			    "mem_iface",
1192			    "alt_mem_iface",
1193			    "gfx3d";
1194			clocks =
1195			    <&gcc GCC_OXILI_GFX3D_CLK>,
1196			    <&gcc GCC_OXILI_AHB_CLK>,
1197			    <&gcc GCC_OXILI_GMEM_CLK>,
1198			    <&gcc GCC_BIMC_GFX_CLK>,
1199			    <&gcc GCC_BIMC_GPU_CLK>,
1200			    <&gcc GFX3D_CLK_SRC>;
1201			power-domains = <&gcc OXILI_GDSC>;
1202			operating-points-v2 = <&gpu_opp_table>;
1203			iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1204
1205			gpu_opp_table: opp-table {
1206				compatible = "operating-points-v2";
1207
1208				opp-400000000 {
1209					opp-hz = /bits/ 64 <400000000>;
1210				};
1211				opp-19200000 {
1212					opp-hz = /bits/ 64 <19200000>;
1213				};
1214			};
1215		};
1216
1217		venus: video-codec@1d00000 {
1218			compatible = "qcom,msm8916-venus";
1219			reg = <0x01d00000 0xff000>;
1220			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1221			power-domains = <&gcc VENUS_GDSC>;
1222			clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1223				 <&gcc GCC_VENUS0_AHB_CLK>,
1224				 <&gcc GCC_VENUS0_AXI_CLK>;
1225			clock-names = "core", "iface", "bus";
1226			iommus = <&apps_iommu 5>;
1227			memory-region = <&venus_mem>;
1228			status = "okay";
1229
1230			video-decoder {
1231				compatible = "venus-decoder";
1232			};
1233
1234			video-encoder {
1235				compatible = "venus-encoder";
1236			};
1237		};
1238
1239		apps_iommu: iommu@1ef0000 {
1240			#address-cells = <1>;
1241			#size-cells = <1>;
1242			#iommu-cells = <1>;
1243			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1244			ranges = <0 0x01e20000 0x40000>;
1245			reg = <0x01ef0000 0x3000>;
1246			clocks = <&gcc GCC_SMMU_CFG_CLK>,
1247				 <&gcc GCC_APSS_TCU_CLK>;
1248			clock-names = "iface", "bus";
1249			qcom,iommu-secure-id = <17>;
1250
1251			// vfe:
1252			iommu-ctx@3000 {
1253				compatible = "qcom,msm-iommu-v1-sec";
1254				reg = <0x3000 0x1000>;
1255				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1256			};
1257
1258			// mdp_0:
1259			iommu-ctx@4000 {
1260				compatible = "qcom,msm-iommu-v1-ns";
1261				reg = <0x4000 0x1000>;
1262				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1263			};
1264
1265			// venus_ns:
1266			iommu-ctx@5000 {
1267				compatible = "qcom,msm-iommu-v1-sec";
1268				reg = <0x5000 0x1000>;
1269				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1270			};
1271		};
1272
1273		gpu_iommu: iommu@1f08000 {
1274			#address-cells = <1>;
1275			#size-cells = <1>;
1276			#iommu-cells = <1>;
1277			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1278			ranges = <0 0x01f08000 0x10000>;
1279			clocks = <&gcc GCC_SMMU_CFG_CLK>,
1280				 <&gcc GCC_GFX_TCU_CLK>;
1281			clock-names = "iface", "bus";
1282			qcom,iommu-secure-id = <18>;
1283
1284			// gfx3d_user:
1285			iommu-ctx@1000 {
1286				compatible = "qcom,msm-iommu-v1-ns";
1287				reg = <0x1000 0x1000>;
1288				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1289			};
1290
1291			// gfx3d_priv:
1292			iommu-ctx@2000 {
1293				compatible = "qcom,msm-iommu-v1-ns";
1294				reg = <0x2000 0x1000>;
1295				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1296			};
1297		};
1298
1299		spmi_bus: spmi@200f000 {
1300			compatible = "qcom,spmi-pmic-arb";
1301			reg = <0x0200f000 0x001000>,
1302			      <0x02400000 0x400000>,
1303			      <0x02c00000 0x400000>,
1304			      <0x03800000 0x200000>,
1305			      <0x0200a000 0x002100>;
1306			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1307			interrupt-names = "periph_irq";
1308			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1309			qcom,ee = <0>;
1310			qcom,channel = <0>;
1311			#address-cells = <2>;
1312			#size-cells = <0>;
1313			interrupt-controller;
1314			#interrupt-cells = <4>;
1315		};
1316
1317		bam_dmux_dma: dma-controller@4044000 {
1318			compatible = "qcom,bam-v1.7.0";
1319			reg = <0x04044000 0x19000>;
1320			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1321			#dma-cells = <1>;
1322			qcom,ee = <0>;
1323
1324			num-channels = <6>;
1325			qcom,num-ees = <1>;
1326			qcom,powered-remotely;
1327
1328			status = "disabled";
1329		};
1330
1331		mpss: remoteproc@4080000 {
1332			compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
1333			reg = <0x04080000 0x100>,
1334			      <0x04020000 0x040>;
1335
1336			reg-names = "qdsp6", "rmb";
1337
1338			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1339					      <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1340					      <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1341					      <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1342					      <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1343			interrupt-names = "wdog", "fatal", "ready",
1344					  "handover", "stop-ack";
1345
1346			power-domains = <&rpmpd MSM8916_VDDCX>,
1347					<&rpmpd MSM8916_VDDMX>;
1348			power-domain-names = "cx", "mx";
1349
1350			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1351				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1352				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1353				 <&xo_board>;
1354			clock-names = "iface", "bus", "mem", "xo";
1355
1356			qcom,smem-states = <&hexagon_smp2p_out 0>;
1357			qcom,smem-state-names = "stop";
1358
1359			resets = <&scm 0>;
1360			reset-names = "mss_restart";
1361
1362			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1363
1364			status = "disabled";
1365
1366			mba {
1367				memory-region = <&mba_mem>;
1368			};
1369
1370			mpss {
1371				memory-region = <&mpss_mem>;
1372			};
1373
1374			bam_dmux: bam-dmux {
1375				compatible = "qcom,bam-dmux";
1376
1377				interrupt-parent = <&hexagon_smsm>;
1378				interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1379				interrupt-names = "pc", "pc-ack";
1380
1381				qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1382				qcom,smem-state-names = "pc", "pc-ack";
1383
1384				dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1385				dma-names = "tx", "rx";
1386
1387				status = "disabled";
1388			};
1389
1390			smd-edge {
1391				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1392
1393				qcom,smd-edge = <0>;
1394				qcom,ipc = <&apcs 8 12>;
1395				qcom,remote-pid = <1>;
1396
1397				label = "hexagon";
1398
1399				fastrpc {
1400					compatible = "qcom,fastrpc";
1401					qcom,smd-channels = "fastrpcsmd-apps-dsp";
1402					label = "adsp";
1403					qcom,non-secure-domain;
1404
1405					#address-cells = <1>;
1406					#size-cells = <0>;
1407
1408					cb@1 {
1409						compatible = "qcom,fastrpc-compute-cb";
1410						reg = <1>;
1411					};
1412				};
1413			};
1414		};
1415
1416		sound: sound@7702000 {
1417			status = "disabled";
1418			compatible = "qcom,apq8016-sbc-sndcard";
1419			reg = <0x07702000 0x4>, <0x07702004 0x4>;
1420			reg-names = "mic-iomux", "spkr-iomux";
1421		};
1422
1423		lpass: audio-controller@7708000 {
1424			status = "disabled";
1425			compatible = "qcom,lpass-cpu-apq8016";
1426
1427			/*
1428			 * Note: Unlike the name would suggest, the SEC_I2S_CLK
1429			 * is actually only used by Tertiary MI2S while
1430			 * Primary/Secondary MI2S both use the PRI_I2S_CLK.
1431			 */
1432			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1433				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1434				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
1435				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1436				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1437				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1438				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
1439
1440			clock-names = "ahbix-clk",
1441					"pcnoc-mport-clk",
1442					"pcnoc-sway-clk",
1443					"mi2s-bit-clk0",
1444					"mi2s-bit-clk1",
1445					"mi2s-bit-clk2",
1446					"mi2s-bit-clk3";
1447			#sound-dai-cells = <1>;
1448
1449			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1450			interrupt-names = "lpass-irq-lpaif";
1451			reg = <0x07708000 0x10000>;
1452			reg-names = "lpass-lpaif";
1453
1454			#address-cells = <1>;
1455			#size-cells = <0>;
1456		};
1457
1458		lpass_codec: audio-codec@771c000 {
1459			compatible = "qcom,msm8916-wcd-digital-codec";
1460			reg = <0x0771c000 0x400>;
1461			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1462				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1463			clock-names = "ahbix-clk", "mclk";
1464			#sound-dai-cells = <1>;
1465		};
1466
1467		sdhc_1: sdhci@7824000 {
1468			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1469			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1470			reg-names = "hc_mem", "core_mem";
1471
1472			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1473				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1474			interrupt-names = "hc_irq", "pwr_irq";
1475			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1476				 <&gcc GCC_SDCC1_AHB_CLK>,
1477				 <&xo_board>;
1478			clock-names = "core", "iface", "xo";
1479			mmc-ddr-1_8v;
1480			bus-width = <8>;
1481			non-removable;
1482			status = "disabled";
1483		};
1484
1485		sdhc_2: sdhci@7864000 {
1486			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1487			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1488			reg-names = "hc_mem", "core_mem";
1489
1490			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1491				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1492			interrupt-names = "hc_irq", "pwr_irq";
1493			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1494				 <&gcc GCC_SDCC2_AHB_CLK>,
1495				 <&xo_board>;
1496			clock-names = "core", "iface", "xo";
1497			bus-width = <4>;
1498			status = "disabled";
1499		};
1500
1501		blsp_dma: dma-controller@7884000 {
1502			compatible = "qcom,bam-v1.7.0";
1503			reg = <0x07884000 0x23000>;
1504			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1505			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1506			clock-names = "bam_clk";
1507			#dma-cells = <1>;
1508			qcom,ee = <0>;
1509			status = "disabled";
1510		};
1511
1512		blsp1_uart1: serial@78af000 {
1513			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1514			reg = <0x078af000 0x200>;
1515			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1516			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1517			clock-names = "core", "iface";
1518			dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1519			dma-names = "tx", "rx";
1520			pinctrl-names = "default", "sleep";
1521			pinctrl-0 = <&blsp1_uart1_default>;
1522			pinctrl-1 = <&blsp1_uart1_sleep>;
1523			status = "disabled";
1524		};
1525
1526		blsp1_uart2: serial@78b0000 {
1527			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1528			reg = <0x078b0000 0x200>;
1529			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1530			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1531			clock-names = "core", "iface";
1532			dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1533			dma-names = "tx", "rx";
1534			pinctrl-names = "default", "sleep";
1535			pinctrl-0 = <&blsp1_uart2_default>;
1536			pinctrl-1 = <&blsp1_uart2_sleep>;
1537			status = "disabled";
1538		};
1539
1540		blsp_i2c1: i2c@78b5000 {
1541			compatible = "qcom,i2c-qup-v2.2.1";
1542			reg = <0x078b5000 0x500>;
1543			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1544			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1545				 <&gcc GCC_BLSP1_AHB_CLK>;
1546			clock-names = "core", "iface";
1547			pinctrl-names = "default", "sleep";
1548			pinctrl-0 = <&i2c1_default>;
1549			pinctrl-1 = <&i2c1_sleep>;
1550			#address-cells = <1>;
1551			#size-cells = <0>;
1552			status = "disabled";
1553		};
1554
1555		blsp_spi1: spi@78b5000 {
1556			compatible = "qcom,spi-qup-v2.2.1";
1557			reg = <0x078b5000 0x500>;
1558			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1559			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1560				 <&gcc GCC_BLSP1_AHB_CLK>;
1561			clock-names = "core", "iface";
1562			dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1563			dma-names = "tx", "rx";
1564			pinctrl-names = "default", "sleep";
1565			pinctrl-0 = <&spi1_default>;
1566			pinctrl-1 = <&spi1_sleep>;
1567			#address-cells = <1>;
1568			#size-cells = <0>;
1569			status = "disabled";
1570		};
1571
1572		blsp_i2c2: i2c@78b6000 {
1573			compatible = "qcom,i2c-qup-v2.2.1";
1574			reg = <0x078b6000 0x500>;
1575			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1576			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1577				 <&gcc GCC_BLSP1_AHB_CLK>;
1578			clock-names = "core", "iface";
1579			pinctrl-names = "default", "sleep";
1580			pinctrl-0 = <&i2c2_default>;
1581			pinctrl-1 = <&i2c2_sleep>;
1582			#address-cells = <1>;
1583			#size-cells = <0>;
1584			status = "disabled";
1585		};
1586
1587		blsp_spi2: spi@78b6000 {
1588			compatible = "qcom,spi-qup-v2.2.1";
1589			reg = <0x078b6000 0x500>;
1590			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1591			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1592				 <&gcc GCC_BLSP1_AHB_CLK>;
1593			clock-names = "core", "iface";
1594			dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1595			dma-names = "tx", "rx";
1596			pinctrl-names = "default", "sleep";
1597			pinctrl-0 = <&spi2_default>;
1598			pinctrl-1 = <&spi2_sleep>;
1599			#address-cells = <1>;
1600			#size-cells = <0>;
1601			status = "disabled";
1602		};
1603
1604		blsp_i2c3: i2c@78b7000 {
1605			compatible = "qcom,i2c-qup-v2.2.1";
1606			reg = <0x078b7000 0x500>;
1607			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1608			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1609				 <&gcc GCC_BLSP1_AHB_CLK>;
1610			clock-names = "core", "iface";
1611			pinctrl-names = "default", "sleep";
1612			pinctrl-0 = <&i2c3_default>;
1613			pinctrl-1 = <&i2c3_sleep>;
1614			#address-cells = <1>;
1615			#size-cells = <0>;
1616			status = "disabled";
1617		};
1618
1619		blsp_spi3: spi@78b7000 {
1620			compatible = "qcom,spi-qup-v2.2.1";
1621			reg = <0x078b7000 0x500>;
1622			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1623			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1624				 <&gcc GCC_BLSP1_AHB_CLK>;
1625			clock-names = "core", "iface";
1626			dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1627			dma-names = "tx", "rx";
1628			pinctrl-names = "default", "sleep";
1629			pinctrl-0 = <&spi3_default>;
1630			pinctrl-1 = <&spi3_sleep>;
1631			#address-cells = <1>;
1632			#size-cells = <0>;
1633			status = "disabled";
1634		};
1635
1636		blsp_i2c4: i2c@78b8000 {
1637			compatible = "qcom,i2c-qup-v2.2.1";
1638			reg = <0x078b8000 0x500>;
1639			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1640			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1641				 <&gcc GCC_BLSP1_AHB_CLK>;
1642			clock-names = "core", "iface";
1643			pinctrl-names = "default", "sleep";
1644			pinctrl-0 = <&i2c4_default>;
1645			pinctrl-1 = <&i2c4_sleep>;
1646			#address-cells = <1>;
1647			#size-cells = <0>;
1648			status = "disabled";
1649		};
1650
1651		blsp_spi4: spi@78b8000 {
1652			compatible = "qcom,spi-qup-v2.2.1";
1653			reg = <0x078b8000 0x500>;
1654			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1655			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1656				 <&gcc GCC_BLSP1_AHB_CLK>;
1657			clock-names = "core", "iface";
1658			dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1659			dma-names = "tx", "rx";
1660			pinctrl-names = "default", "sleep";
1661			pinctrl-0 = <&spi4_default>;
1662			pinctrl-1 = <&spi4_sleep>;
1663			#address-cells = <1>;
1664			#size-cells = <0>;
1665			status = "disabled";
1666		};
1667
1668		blsp_i2c5: i2c@78b9000 {
1669			compatible = "qcom,i2c-qup-v2.2.1";
1670			reg = <0x078b9000 0x500>;
1671			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1672			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1673				 <&gcc GCC_BLSP1_AHB_CLK>;
1674			clock-names = "core", "iface";
1675			pinctrl-names = "default", "sleep";
1676			pinctrl-0 = <&i2c5_default>;
1677			pinctrl-1 = <&i2c5_sleep>;
1678			#address-cells = <1>;
1679			#size-cells = <0>;
1680			status = "disabled";
1681		};
1682
1683		blsp_spi5: spi@78b9000 {
1684			compatible = "qcom,spi-qup-v2.2.1";
1685			reg = <0x078b9000 0x500>;
1686			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1687			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1688				 <&gcc GCC_BLSP1_AHB_CLK>;
1689			clock-names = "core", "iface";
1690			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1691			dma-names = "tx", "rx";
1692			pinctrl-names = "default", "sleep";
1693			pinctrl-0 = <&spi5_default>;
1694			pinctrl-1 = <&spi5_sleep>;
1695			#address-cells = <1>;
1696			#size-cells = <0>;
1697			status = "disabled";
1698		};
1699
1700		blsp_i2c6: i2c@78ba000 {
1701			compatible = "qcom,i2c-qup-v2.2.1";
1702			reg = <0x078ba000 0x500>;
1703			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1704			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1705				 <&gcc GCC_BLSP1_AHB_CLK>;
1706			clock-names = "core", "iface";
1707			pinctrl-names = "default", "sleep";
1708			pinctrl-0 = <&i2c6_default>;
1709			pinctrl-1 = <&i2c6_sleep>;
1710			#address-cells = <1>;
1711			#size-cells = <0>;
1712			status = "disabled";
1713		};
1714
1715		blsp_spi6: spi@78ba000 {
1716			compatible = "qcom,spi-qup-v2.2.1";
1717			reg = <0x078ba000 0x500>;
1718			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1719			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1720				 <&gcc GCC_BLSP1_AHB_CLK>;
1721			clock-names = "core", "iface";
1722			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1723			dma-names = "tx", "rx";
1724			pinctrl-names = "default", "sleep";
1725			pinctrl-0 = <&spi6_default>;
1726			pinctrl-1 = <&spi6_sleep>;
1727			#address-cells = <1>;
1728			#size-cells = <0>;
1729			status = "disabled";
1730		};
1731
1732		usb: usb@78d9000 {
1733			compatible = "qcom,ci-hdrc";
1734			reg = <0x078d9000 0x200>,
1735			      <0x078d9200 0x200>;
1736			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1737				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1738			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1739				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1740			clock-names = "iface", "core";
1741			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1742			assigned-clock-rates = <80000000>;
1743			resets = <&gcc GCC_USB_HS_BCR>;
1744			reset-names = "core";
1745			phy_type = "ulpi";
1746			dr_mode = "otg";
1747			hnp-disable;
1748			srp-disable;
1749			adp-disable;
1750			ahb-burst-config = <0>;
1751			phy-names = "usb-phy";
1752			phys = <&usb_hs_phy>;
1753			status = "disabled";
1754			#reset-cells = <1>;
1755
1756			ulpi {
1757				usb_hs_phy: phy {
1758					compatible = "qcom,usb-hs-phy-msm8916",
1759						     "qcom,usb-hs-phy";
1760					#phy-cells = <0>;
1761					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1762					clock-names = "ref", "sleep";
1763					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1764					reset-names = "phy", "por";
1765					qcom,init-seq = /bits/ 8 <0x0 0x44>,
1766								 <0x1 0x6b>,
1767								 <0x2 0x24>,
1768								 <0x3 0x13>;
1769				};
1770			};
1771		};
1772
1773		pronto: remoteproc@a21b000 {
1774			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1775			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1776			reg-names = "ccu", "dxe", "pmu";
1777
1778			memory-region = <&wcnss_mem>;
1779
1780			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1781					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1782					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1783					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1784					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1785			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1786
1787			power-domains = <&rpmpd MSM8916_VDDCX>,
1788					<&rpmpd MSM8916_VDDMX>;
1789			power-domain-names = "cx", "mx";
1790
1791			qcom,smem-states = <&wcnss_smp2p_out 0>;
1792			qcom,smem-state-names = "stop";
1793
1794			pinctrl-names = "default";
1795			pinctrl-0 = <&wcnss_pin_a>;
1796
1797			status = "disabled";
1798
1799			iris {
1800				compatible = "qcom,wcn3620";
1801
1802				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1803				clock-names = "xo";
1804			};
1805
1806			smd-edge {
1807				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1808
1809				qcom,ipc = <&apcs 8 17>;
1810				qcom,smd-edge = <6>;
1811				qcom,remote-pid = <4>;
1812
1813				label = "pronto";
1814
1815				wcnss_ctrl: wcnss {
1816					compatible = "qcom,wcnss";
1817					qcom,smd-channels = "WCNSS_CTRL";
1818
1819					qcom,mmio = <&pronto>;
1820
1821					bluetooth {
1822						compatible = "qcom,wcnss-bt";
1823					};
1824
1825					wifi {
1826						compatible = "qcom,wcnss-wlan";
1827
1828						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1829							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1830						interrupt-names = "tx", "rx";
1831
1832						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1833						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1834					};
1835				};
1836			};
1837		};
1838
1839		intc: interrupt-controller@b000000 {
1840			compatible = "qcom,msm-qgic2";
1841			interrupt-controller;
1842			#interrupt-cells = <3>;
1843			reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
1844			      <0x0b001000 0x1000>, <0x0b004000 0x2000>;
1845			interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1846		};
1847
1848		apcs: mailbox@b011000 {
1849			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
1850			reg = <0x0b011000 0x1000>;
1851			#mbox-cells = <1>;
1852			clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
1853			clock-names = "pll", "aux";
1854			#clock-cells = <0>;
1855		};
1856
1857		a53pll: clock@b016000 {
1858			compatible = "qcom,msm8916-a53pll";
1859			reg = <0x0b016000 0x40>;
1860			#clock-cells = <0>;
1861		};
1862
1863		timer@b020000 {
1864			#address-cells = <1>;
1865			#size-cells = <1>;
1866			ranges;
1867			compatible = "arm,armv7-timer-mem";
1868			reg = <0x0b020000 0x1000>;
1869			clock-frequency = <19200000>;
1870
1871			frame@b021000 {
1872				frame-number = <0>;
1873				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1874					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1875				reg = <0x0b021000 0x1000>,
1876				      <0x0b022000 0x1000>;
1877			};
1878
1879			frame@b023000 {
1880				frame-number = <1>;
1881				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1882				reg = <0x0b023000 0x1000>;
1883				status = "disabled";
1884			};
1885
1886			frame@b024000 {
1887				frame-number = <2>;
1888				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1889				reg = <0x0b024000 0x1000>;
1890				status = "disabled";
1891			};
1892
1893			frame@b025000 {
1894				frame-number = <3>;
1895				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1896				reg = <0x0b025000 0x1000>;
1897				status = "disabled";
1898			};
1899
1900			frame@b026000 {
1901				frame-number = <4>;
1902				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1903				reg = <0x0b026000 0x1000>;
1904				status = "disabled";
1905			};
1906
1907			frame@b027000 {
1908				frame-number = <5>;
1909				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1910				reg = <0x0b027000 0x1000>;
1911				status = "disabled";
1912			};
1913
1914			frame@b028000 {
1915				frame-number = <6>;
1916				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1917				reg = <0x0b028000 0x1000>;
1918				status = "disabled";
1919			};
1920		};
1921
1922		cpu0_acc: power-manager@b088000 {
1923			compatible = "qcom,msm8916-acc";
1924			reg = <0x0b088000 0x1000>;
1925			status = "reserved"; /* Controlled by PSCI firmware */
1926		};
1927
1928		cpu0_saw: power-manager@b089000 {
1929			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1930			reg = <0x0b089000 0x1000>;
1931			status = "reserved"; /* Controlled by PSCI firmware */
1932		};
1933
1934		cpu1_acc: power-manager@b098000 {
1935			compatible = "qcom,msm8916-acc";
1936			reg = <0x0b098000 0x1000>;
1937			status = "reserved"; /* Controlled by PSCI firmware */
1938		};
1939
1940		cpu1_saw: power-manager@b099000 {
1941			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1942			reg = <0x0b099000 0x1000>;
1943			status = "reserved"; /* Controlled by PSCI firmware */
1944		};
1945
1946		cpu2_acc: power-manager@b0a8000 {
1947			compatible = "qcom,msm8916-acc";
1948			reg = <0x0b0a8000 0x1000>;
1949			status = "reserved"; /* Controlled by PSCI firmware */
1950		};
1951
1952		cpu2_saw: power-manager@b0a9000 {
1953			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1954			reg = <0x0b0a9000 0x1000>;
1955			status = "reserved"; /* Controlled by PSCI firmware */
1956		};
1957
1958		cpu3_acc: power-manager@b0b8000 {
1959			compatible = "qcom,msm8916-acc";
1960			reg = <0x0b0b8000 0x1000>;
1961			status = "reserved"; /* Controlled by PSCI firmware */
1962		};
1963
1964		cpu3_saw: power-manager@b0b9000 {
1965			compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
1966			reg = <0x0b0b9000 0x1000>;
1967			status = "reserved"; /* Controlled by PSCI firmware */
1968		};
1969	};
1970
1971	thermal-zones {
1972		cpu0-1-thermal {
1973			polling-delay-passive = <250>;
1974			polling-delay = <1000>;
1975
1976			thermal-sensors = <&tsens 5>;
1977
1978			trips {
1979				cpu0_1_alert0: trip-point0 {
1980					temperature = <75000>;
1981					hysteresis = <2000>;
1982					type = "passive";
1983				};
1984				cpu0_1_crit: cpu_crit {
1985					temperature = <110000>;
1986					hysteresis = <2000>;
1987					type = "critical";
1988				};
1989			};
1990
1991			cooling-maps {
1992				map0 {
1993					trip = <&cpu0_1_alert0>;
1994					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1995							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1996							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1997							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1998				};
1999			};
2000		};
2001
2002		cpu2-3-thermal {
2003			polling-delay-passive = <250>;
2004			polling-delay = <1000>;
2005
2006			thermal-sensors = <&tsens 4>;
2007
2008			trips {
2009				cpu2_3_alert0: trip-point0 {
2010					temperature = <75000>;
2011					hysteresis = <2000>;
2012					type = "passive";
2013				};
2014				cpu2_3_crit: cpu_crit {
2015					temperature = <110000>;
2016					hysteresis = <2000>;
2017					type = "critical";
2018				};
2019			};
2020
2021			cooling-maps {
2022				map0 {
2023					trip = <&cpu2_3_alert0>;
2024					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2025							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2026							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2027							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2028				};
2029			};
2030		};
2031
2032		gpu-thermal {
2033			polling-delay-passive = <250>;
2034			polling-delay = <1000>;
2035
2036			thermal-sensors = <&tsens 2>;
2037
2038			trips {
2039				gpu_alert0: trip-point0 {
2040					temperature = <75000>;
2041					hysteresis = <2000>;
2042					type = "passive";
2043				};
2044				gpu_crit: gpu_crit {
2045					temperature = <95000>;
2046					hysteresis = <2000>;
2047					type = "critical";
2048				};
2049			};
2050		};
2051
2052		camera-thermal {
2053			polling-delay-passive = <250>;
2054			polling-delay = <1000>;
2055
2056			thermal-sensors = <&tsens 1>;
2057
2058			trips {
2059				cam_alert0: trip-point0 {
2060					temperature = <75000>;
2061					hysteresis = <2000>;
2062					type = "hot";
2063				};
2064			};
2065		};
2066
2067		modem-thermal {
2068			polling-delay-passive = <250>;
2069			polling-delay = <1000>;
2070
2071			thermal-sensors = <&tsens 0>;
2072
2073			trips {
2074				modem_alert0: trip-point0 {
2075					temperature = <85000>;
2076					hysteresis = <2000>;
2077					type = "hot";
2078				};
2079			};
2080		};
2081
2082	};
2083
2084	timer {
2085		compatible = "arm,armv8-timer";
2086		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2087			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2088			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2089			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2090	};
2091};
2092
2093#include "msm8916-pins.dtsi"
2094