1/* 2 * MPC8641 HPCN Device Tree Source 3 * 4 * Copyright 2006 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "MPC8641HPCN"; 16 compatible = "fsl,mpc8641hpcn"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 ethernet2 = &enet2; 24 ethernet3 = &enet3; 25 serial0 = &serial0; 26 serial1 = &serial1; 27 pci0 = &pci0; 28 pci1 = &pci1; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 PowerPC,8641@0 { 36 device_type = "cpu"; 37 reg = <0>; 38 d-cache-line-size = <32>; 39 i-cache-line-size = <32>; 40 d-cache-size = <32768>; // L1 41 i-cache-size = <32768>; // L1 42 timebase-frequency = <0>; // From uboot 43 bus-frequency = <0>; // From uboot 44 clock-frequency = <0>; // From uboot 45 }; 46 PowerPC,8641@1 { 47 device_type = "cpu"; 48 reg = <1>; 49 d-cache-line-size = <32>; 50 i-cache-line-size = <32>; 51 d-cache-size = <32768>; 52 i-cache-size = <32768>; 53 timebase-frequency = <0>; // From uboot 54 bus-frequency = <0>; // From uboot 55 clock-frequency = <0>; // From uboot 56 }; 57 }; 58 59 memory { 60 device_type = "memory"; 61 reg = <0x00000000 0x40000000>; // 1G at 0x0 62 }; 63 64 localbus@ffe05000 { 65 #address-cells = <2>; 66 #size-cells = <1>; 67 compatible = "fsl,mpc8641-localbus", "simple-bus"; 68 reg = <0xffe05000 0x1000>; 69 interrupts = <19 2>; 70 interrupt-parent = <&mpic>; 71 72 ranges = <0 0 0xef800000 0x00800000 73 2 0 0xffdf8000 0x00008000 74 3 0 0xffdf0000 0x00008000>; 75 76 flash@0,0 { 77 compatible = "cfi-flash"; 78 reg = <0 0 0x00800000>; 79 bank-width = <2>; 80 device-width = <2>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 partition@0 { 84 label = "kernel"; 85 reg = <0x00000000 0x00300000>; 86 }; 87 partition@300000 { 88 label = "firmware b"; 89 reg = <0x00300000 0x00100000>; 90 read-only; 91 }; 92 partition@400000 { 93 label = "fs"; 94 reg = <0x00400000 0x00300000>; 95 }; 96 partition@700000 { 97 label = "firmware a"; 98 reg = <0x00700000 0x00100000>; 99 read-only; 100 }; 101 }; 102 }; 103 104 soc8641@ffe00000 { 105 #address-cells = <1>; 106 #size-cells = <1>; 107 device_type = "soc"; 108 compatible = "simple-bus"; 109 ranges = <0x00000000 0xffe00000 0x00100000>; 110 bus-frequency = <0>; 111 112 mcm-law@0 { 113 compatible = "fsl,mcm-law"; 114 reg = <0x0 0x1000>; 115 fsl,num-laws = <10>; 116 }; 117 118 mcm@1000 { 119 compatible = "fsl,mpc8641-mcm", "fsl,mcm"; 120 reg = <0x1000 0x1000>; 121 interrupts = <17 2>; 122 interrupt-parent = <&mpic>; 123 }; 124 125 i2c@3000 { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 cell-index = <0>; 129 compatible = "fsl-i2c"; 130 reg = <0x3000 0x100>; 131 interrupts = <43 2>; 132 interrupt-parent = <&mpic>; 133 dfsrr; 134 }; 135 136 i2c@3100 { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 cell-index = <1>; 140 compatible = "fsl-i2c"; 141 reg = <0x3100 0x100>; 142 interrupts = <43 2>; 143 interrupt-parent = <&mpic>; 144 dfsrr; 145 }; 146 147 dma@21300 { 148 #address-cells = <1>; 149 #size-cells = <1>; 150 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; 151 reg = <0x21300 0x4>; 152 ranges = <0x0 0x21100 0x200>; 153 cell-index = <0>; 154 dma-channel@0 { 155 compatible = "fsl,mpc8641-dma-channel", 156 "fsl,eloplus-dma-channel"; 157 reg = <0x0 0x80>; 158 cell-index = <0>; 159 interrupt-parent = <&mpic>; 160 interrupts = <20 2>; 161 }; 162 dma-channel@80 { 163 compatible = "fsl,mpc8641-dma-channel", 164 "fsl,eloplus-dma-channel"; 165 reg = <0x80 0x80>; 166 cell-index = <1>; 167 interrupt-parent = <&mpic>; 168 interrupts = <21 2>; 169 }; 170 dma-channel@100 { 171 compatible = "fsl,mpc8641-dma-channel", 172 "fsl,eloplus-dma-channel"; 173 reg = <0x100 0x80>; 174 cell-index = <2>; 175 interrupt-parent = <&mpic>; 176 interrupts = <22 2>; 177 }; 178 dma-channel@180 { 179 compatible = "fsl,mpc8641-dma-channel", 180 "fsl,eloplus-dma-channel"; 181 reg = <0x180 0x80>; 182 cell-index = <3>; 183 interrupt-parent = <&mpic>; 184 interrupts = <23 2>; 185 }; 186 }; 187 188 enet0: ethernet@24000 { 189 #address-cells = <1>; 190 #size-cells = <1>; 191 cell-index = <0>; 192 device_type = "network"; 193 model = "TSEC"; 194 compatible = "gianfar"; 195 reg = <0x24000 0x1000>; 196 ranges = <0x0 0x24000 0x1000>; 197 local-mac-address = [ 00 00 00 00 00 00 ]; 198 interrupts = <29 2 30 2 34 2>; 199 interrupt-parent = <&mpic>; 200 tbi-handle = <&tbi0>; 201 phy-handle = <&phy0>; 202 phy-connection-type = "rgmii-id"; 203 204 mdio@520 { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 compatible = "fsl,gianfar-mdio"; 208 reg = <0x520 0x20>; 209 210 phy0: ethernet-phy@0 { 211 interrupt-parent = <&mpic>; 212 interrupts = <10 1>; 213 reg = <0>; 214 device_type = "ethernet-phy"; 215 }; 216 phy1: ethernet-phy@1 { 217 interrupt-parent = <&mpic>; 218 interrupts = <10 1>; 219 reg = <1>; 220 device_type = "ethernet-phy"; 221 }; 222 phy2: ethernet-phy@2 { 223 interrupt-parent = <&mpic>; 224 interrupts = <10 1>; 225 reg = <2>; 226 device_type = "ethernet-phy"; 227 }; 228 phy3: ethernet-phy@3 { 229 interrupt-parent = <&mpic>; 230 interrupts = <10 1>; 231 reg = <3>; 232 device_type = "ethernet-phy"; 233 }; 234 tbi0: tbi-phy@11 { 235 reg = <0x11>; 236 device_type = "tbi-phy"; 237 }; 238 }; 239 }; 240 241 enet1: ethernet@25000 { 242 #address-cells = <1>; 243 #size-cells = <1>; 244 cell-index = <1>; 245 device_type = "network"; 246 model = "TSEC"; 247 compatible = "gianfar"; 248 reg = <0x25000 0x1000>; 249 ranges = <0x0 0x25000 0x1000>; 250 local-mac-address = [ 00 00 00 00 00 00 ]; 251 interrupts = <35 2 36 2 40 2>; 252 interrupt-parent = <&mpic>; 253 tbi-handle = <&tbi1>; 254 phy-handle = <&phy1>; 255 phy-connection-type = "rgmii-id"; 256 257 mdio@520 { 258 #address-cells = <1>; 259 #size-cells = <0>; 260 compatible = "fsl,gianfar-tbi"; 261 reg = <0x520 0x20>; 262 263 tbi1: tbi-phy@11 { 264 reg = <0x11>; 265 device_type = "tbi-phy"; 266 }; 267 }; 268 }; 269 270 enet2: ethernet@26000 { 271 #address-cells = <1>; 272 #size-cells = <1>; 273 cell-index = <2>; 274 device_type = "network"; 275 model = "TSEC"; 276 compatible = "gianfar"; 277 reg = <0x26000 0x1000>; 278 ranges = <0x0 0x26000 0x1000>; 279 local-mac-address = [ 00 00 00 00 00 00 ]; 280 interrupts = <31 2 32 2 33 2>; 281 interrupt-parent = <&mpic>; 282 tbi-handle = <&tbi2>; 283 phy-handle = <&phy2>; 284 phy-connection-type = "rgmii-id"; 285 286 mdio@520 { 287 #address-cells = <1>; 288 #size-cells = <0>; 289 compatible = "fsl,gianfar-tbi"; 290 reg = <0x520 0x20>; 291 292 tbi2: tbi-phy@11 { 293 reg = <0x11>; 294 device_type = "tbi-phy"; 295 }; 296 }; 297 }; 298 299 enet3: ethernet@27000 { 300 #address-cells = <1>; 301 #size-cells = <1>; 302 cell-index = <3>; 303 device_type = "network"; 304 model = "TSEC"; 305 compatible = "gianfar"; 306 reg = <0x27000 0x1000>; 307 ranges = <0x0 0x27000 0x1000>; 308 local-mac-address = [ 00 00 00 00 00 00 ]; 309 interrupts = <37 2 38 2 39 2>; 310 interrupt-parent = <&mpic>; 311 tbi-handle = <&tbi3>; 312 phy-handle = <&phy3>; 313 phy-connection-type = "rgmii-id"; 314 315 mdio@520 { 316 #address-cells = <1>; 317 #size-cells = <0>; 318 compatible = "fsl,gianfar-tbi"; 319 reg = <0x520 0x20>; 320 321 tbi3: tbi-phy@11 { 322 reg = <0x11>; 323 device_type = "tbi-phy"; 324 }; 325 }; 326 }; 327 328 serial0: serial@4500 { 329 cell-index = <0>; 330 device_type = "serial"; 331 compatible = "fsl,ns16550", "ns16550"; 332 reg = <0x4500 0x100>; 333 clock-frequency = <0>; 334 interrupts = <42 2>; 335 interrupt-parent = <&mpic>; 336 }; 337 338 serial1: serial@4600 { 339 cell-index = <1>; 340 device_type = "serial"; 341 compatible = "fsl,ns16550", "ns16550"; 342 reg = <0x4600 0x100>; 343 clock-frequency = <0>; 344 interrupts = <28 2>; 345 interrupt-parent = <&mpic>; 346 }; 347 348 mpic: pic@40000 { 349 interrupt-controller; 350 #address-cells = <0>; 351 #interrupt-cells = <2>; 352 reg = <0x40000 0x40000>; 353 compatible = "chrp,open-pic"; 354 device_type = "open-pic"; 355 }; 356 357 rmu: rmu@d3000 { 358 #address-cells = <1>; 359 #size-cells = <1>; 360 compatible = "fsl,srio-rmu"; 361 reg = <0xd3000 0x500>; 362 ranges = <0x0 0xd3000 0x500>; 363 364 message-unit@0 { 365 compatible = "fsl,srio-msg-unit"; 366 reg = <0x0 0x100>; 367 interrupts = < 368 53 2 /* msg1_tx_irq */ 369 54 2>;/* msg1_rx_irq */ 370 }; 371 message-unit@100 { 372 compatible = "fsl,srio-msg-unit"; 373 reg = <0x100 0x100>; 374 interrupts = < 375 55 2 /* msg2_tx_irq */ 376 56 2>;/* msg2_rx_irq */ 377 }; 378 doorbell-unit@400 { 379 compatible = "fsl,srio-dbell-unit"; 380 reg = <0x400 0x80>; 381 interrupts = < 382 49 2 /* bell_outb_irq */ 383 50 2>;/* bell_inb_irq */ 384 }; 385 port-write-unit@4e0 { 386 compatible = "fsl,srio-port-write-unit"; 387 reg = <0x4e0 0x20>; 388 interrupts = <48 2>; 389 }; 390 }; 391 392 global-utilities@e0000 { 393 compatible = "fsl,mpc8641-guts"; 394 reg = <0xe0000 0x1000>; 395 fsl,has-rstcr; 396 }; 397 }; 398 399 pci0: pcie@ffe08000 { 400 compatible = "fsl,mpc8641-pcie"; 401 device_type = "pci"; 402 #interrupt-cells = <1>; 403 #size-cells = <2>; 404 #address-cells = <3>; 405 reg = <0xffe08000 0x1000>; 406 bus-range = <0x0 0xff>; 407 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 408 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>; 409 clock-frequency = <33333333>; 410 interrupt-parent = <&mpic>; 411 interrupts = <24 2>; 412 interrupt-map-mask = <0xff00 0 0 7>; 413 interrupt-map = < 414 /* IDSEL 0x11 func 0 - PCI slot 1 */ 415 0x8800 0 0 1 &mpic 2 1 416 0x8800 0 0 2 &mpic 3 1 417 0x8800 0 0 3 &mpic 4 1 418 0x8800 0 0 4 &mpic 1 1 419 420 /* IDSEL 0x11 func 1 - PCI slot 1 */ 421 0x8900 0 0 1 &mpic 2 1 422 0x8900 0 0 2 &mpic 3 1 423 0x8900 0 0 3 &mpic 4 1 424 0x8900 0 0 4 &mpic 1 1 425 426 /* IDSEL 0x11 func 2 - PCI slot 1 */ 427 0x8a00 0 0 1 &mpic 2 1 428 0x8a00 0 0 2 &mpic 3 1 429 0x8a00 0 0 3 &mpic 4 1 430 0x8a00 0 0 4 &mpic 1 1 431 432 /* IDSEL 0x11 func 3 - PCI slot 1 */ 433 0x8b00 0 0 1 &mpic 2 1 434 0x8b00 0 0 2 &mpic 3 1 435 0x8b00 0 0 3 &mpic 4 1 436 0x8b00 0 0 4 &mpic 1 1 437 438 /* IDSEL 0x11 func 4 - PCI slot 1 */ 439 0x8c00 0 0 1 &mpic 2 1 440 0x8c00 0 0 2 &mpic 3 1 441 0x8c00 0 0 3 &mpic 4 1 442 0x8c00 0 0 4 &mpic 1 1 443 444 /* IDSEL 0x11 func 5 - PCI slot 1 */ 445 0x8d00 0 0 1 &mpic 2 1 446 0x8d00 0 0 2 &mpic 3 1 447 0x8d00 0 0 3 &mpic 4 1 448 0x8d00 0 0 4 &mpic 1 1 449 450 /* IDSEL 0x11 func 6 - PCI slot 1 */ 451 0x8e00 0 0 1 &mpic 2 1 452 0x8e00 0 0 2 &mpic 3 1 453 0x8e00 0 0 3 &mpic 4 1 454 0x8e00 0 0 4 &mpic 1 1 455 456 /* IDSEL 0x11 func 7 - PCI slot 1 */ 457 0x8f00 0 0 1 &mpic 2 1 458 0x8f00 0 0 2 &mpic 3 1 459 0x8f00 0 0 3 &mpic 4 1 460 0x8f00 0 0 4 &mpic 1 1 461 462 /* IDSEL 0x12 func 0 - PCI slot 2 */ 463 0x9000 0 0 1 &mpic 3 1 464 0x9000 0 0 2 &mpic 4 1 465 0x9000 0 0 3 &mpic 1 1 466 0x9000 0 0 4 &mpic 2 1 467 468 /* IDSEL 0x12 func 1 - PCI slot 2 */ 469 0x9100 0 0 1 &mpic 3 1 470 0x9100 0 0 2 &mpic 4 1 471 0x9100 0 0 3 &mpic 1 1 472 0x9100 0 0 4 &mpic 2 1 473 474 /* IDSEL 0x12 func 2 - PCI slot 2 */ 475 0x9200 0 0 1 &mpic 3 1 476 0x9200 0 0 2 &mpic 4 1 477 0x9200 0 0 3 &mpic 1 1 478 0x9200 0 0 4 &mpic 2 1 479 480 /* IDSEL 0x12 func 3 - PCI slot 2 */ 481 0x9300 0 0 1 &mpic 3 1 482 0x9300 0 0 2 &mpic 4 1 483 0x9300 0 0 3 &mpic 1 1 484 0x9300 0 0 4 &mpic 2 1 485 486 /* IDSEL 0x12 func 4 - PCI slot 2 */ 487 0x9400 0 0 1 &mpic 3 1 488 0x9400 0 0 2 &mpic 4 1 489 0x9400 0 0 3 &mpic 1 1 490 0x9400 0 0 4 &mpic 2 1 491 492 /* IDSEL 0x12 func 5 - PCI slot 2 */ 493 0x9500 0 0 1 &mpic 3 1 494 0x9500 0 0 2 &mpic 4 1 495 0x9500 0 0 3 &mpic 1 1 496 0x9500 0 0 4 &mpic 2 1 497 498 /* IDSEL 0x12 func 6 - PCI slot 2 */ 499 0x9600 0 0 1 &mpic 3 1 500 0x9600 0 0 2 &mpic 4 1 501 0x9600 0 0 3 &mpic 1 1 502 0x9600 0 0 4 &mpic 2 1 503 504 /* IDSEL 0x12 func 7 - PCI slot 2 */ 505 0x9700 0 0 1 &mpic 3 1 506 0x9700 0 0 2 &mpic 4 1 507 0x9700 0 0 3 &mpic 1 1 508 0x9700 0 0 4 &mpic 2 1 509 510 // IDSEL 0x1c USB 511 0xe000 0 0 1 &i8259 12 2 512 0xe100 0 0 2 &i8259 9 2 513 0xe200 0 0 3 &i8259 10 2 514 0xe300 0 0 4 &i8259 11 2 515 516 // IDSEL 0x1d Audio 517 0xe800 0 0 1 &i8259 6 2 518 519 // IDSEL 0x1e Legacy 520 0xf000 0 0 1 &i8259 7 2 521 0xf100 0 0 1 &i8259 7 2 522 523 // IDSEL 0x1f IDE/SATA 524 0xf800 0 0 1 &i8259 14 2 525 0xf900 0 0 1 &i8259 5 2 526 >; 527 528 pcie@0 { 529 reg = <0 0 0 0 0>; 530 #size-cells = <2>; 531 #address-cells = <3>; 532 device_type = "pci"; 533 ranges = <0x02000000 0x0 0x80000000 534 0x02000000 0x0 0x80000000 535 0x0 0x20000000 536 537 0x01000000 0x0 0x00000000 538 0x01000000 0x0 0x00000000 539 0x0 0x00010000>; 540 uli1575@0 { 541 reg = <0 0 0 0 0>; 542 #size-cells = <2>; 543 #address-cells = <3>; 544 ranges = <0x02000000 0x0 0x80000000 545 0x02000000 0x0 0x80000000 546 0x0 0x20000000 547 0x01000000 0x0 0x00000000 548 0x01000000 0x0 0x00000000 549 0x0 0x00010000>; 550 isa@1e { 551 device_type = "isa"; 552 #interrupt-cells = <2>; 553 #size-cells = <1>; 554 #address-cells = <2>; 555 reg = <0xf000 0 0 0 0>; 556 ranges = <1 0 0x01000000 0 0 557 0x00001000>; 558 interrupt-parent = <&i8259>; 559 560 i8259: interrupt-controller@20 { 561 reg = <1 0x20 2 562 1 0xa0 2 563 1 0x4d0 2>; 564 interrupt-controller; 565 device_type = "interrupt-controller"; 566 #address-cells = <0>; 567 #interrupt-cells = <2>; 568 compatible = "chrp,iic"; 569 interrupts = <9 2>; 570 interrupt-parent = <&mpic>; 571 }; 572 573 i8042@60 { 574 #size-cells = <0>; 575 #address-cells = <1>; 576 reg = <1 0x60 1 1 0x64 1>; 577 interrupts = <1 3 12 3>; 578 interrupt-parent = 579 <&i8259>; 580 581 keyboard@0 { 582 reg = <0>; 583 compatible = "pnpPNP,303"; 584 }; 585 586 mouse@1 { 587 reg = <1>; 588 compatible = "pnpPNP,f03"; 589 }; 590 }; 591 592 rtc@70 { 593 compatible = 594 "pnpPNP,b00"; 595 reg = <1 0x70 2>; 596 }; 597 598 gpio@400 { 599 reg = <1 0x400 0x80>; 600 }; 601 }; 602 }; 603 }; 604 605 }; 606 607 pci1: pcie@ffe09000 { 608 compatible = "fsl,mpc8641-pcie"; 609 device_type = "pci"; 610 #interrupt-cells = <1>; 611 #size-cells = <2>; 612 #address-cells = <3>; 613 reg = <0xffe09000 0x1000>; 614 bus-range = <0 0xff>; 615 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 616 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>; 617 clock-frequency = <33333333>; 618 interrupt-parent = <&mpic>; 619 interrupts = <25 2>; 620 interrupt-map-mask = <0xf800 0 0 7>; 621 interrupt-map = < 622 /* IDSEL 0x0 */ 623 0x0000 0 0 1 &mpic 4 1 624 0x0000 0 0 2 &mpic 5 1 625 0x0000 0 0 3 &mpic 6 1 626 0x0000 0 0 4 &mpic 7 1 627 >; 628 pcie@0 { 629 reg = <0 0 0 0 0>; 630 #size-cells = <2>; 631 #address-cells = <3>; 632 device_type = "pci"; 633 ranges = <0x02000000 0x0 0xa0000000 634 0x02000000 0x0 0xa0000000 635 0x0 0x20000000 636 637 0x01000000 0x0 0x00000000 638 0x01000000 0x0 0x00000000 639 0x0 0x00010000>; 640 }; 641 }; 642/* 643 * Only one of Rapid IO or PCI can be present due to HW limitations and 644 * due to the fact that the 2 now share address space in the new memory 645 * map. The most likely case is that we have PCI, so comment out the 646 * rapidio node. Leave it here for reference. 647 648 rapidio@ffec0000 { 649 reg = <0xffec0000 0x11000>; 650 compatible = "fsl,srio"; 651 interrupt-parent = <&mpic>; 652 interrupts = <48 2>; 653 #address-cells = <2>; 654 #size-cells = <2>; 655 fsl,srio-rmu-handle = <&rmu>; 656 ranges; 657 658 port1 { 659 #address-cells = <2>; 660 #size-cells = <2>; 661 cell-index = <1>; 662 ranges = <0 0 0x80000000 0 0x20000000>; 663 }; 664 }; 665*/ 666 667}; 668