1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2018 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_MMU_UP_REGS_H_
14 #define ASIC_REG_MMU_UP_REGS_H_
15 
16 /*
17  *****************************************
18  *   MMU_UP (Prototype: MMU)
19  *****************************************
20  */
21 
22 #define mmMMU_UP_MMU_ENABLE                                          0xC1100C
23 
24 #define mmMMU_UP_FORCE_ORDERING                                      0xC11010
25 
26 #define mmMMU_UP_FEATURE_ENABLE                                      0xC11014
27 
28 #define mmMMU_UP_VA_ORDERING_MASK_31_7                               0xC11018
29 
30 #define mmMMU_UP_VA_ORDERING_MASK_49_32                              0xC1101C
31 
32 #define mmMMU_UP_LOG2_DDR_SIZE                                       0xC11020
33 
34 #define mmMMU_UP_SCRAMBLER                                           0xC11024
35 
36 #define mmMMU_UP_MEM_INIT_BUSY                                       0xC11028
37 
38 #define mmMMU_UP_SPI_MASK                                            0xC1102C
39 
40 #define mmMMU_UP_SPI_CAUSE                                           0xC11030
41 
42 #define mmMMU_UP_PAGE_ERROR_CAPTURE                                  0xC11034
43 
44 #define mmMMU_UP_PAGE_ERROR_CAPTURE_VA                               0xC11038
45 
46 #define mmMMU_UP_ACCESS_ERROR_CAPTURE                                0xC1103C
47 
48 #define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA                             0xC11040
49 
50 #define mmMMU_UP_SPI_INTERRUPT_CLR                                   0xC11044
51 
52 #define mmMMU_UP_SPI_INTERRUPT_MASK                                  0xC11048
53 
54 #define mmMMU_UP_DBG_MEM_WRAP_RM                                     0xC1104C
55 
56 #define mmMMU_UP_SPI_CAUSE_CLR                                       0xC11050
57 
58 #define mmMMU_UP_SLICE_CREDIT                                        0xC11054
59 
60 #define mmMMU_UP_PIPE_CREDIT                                         0xC11058
61 
62 #define mmMMU_UP_RAZWI_WRITE_VLD                                     0xC1105C
63 
64 #define mmMMU_UP_RAZWI_WRITE_ID                                      0xC11060
65 
66 #define mmMMU_UP_RAZWI_READ_VLD                                      0xC11064
67 
68 #define mmMMU_UP_RAZWI_READ_ID                                       0xC11068
69 
70 #define mmMMU_UP_MMU_BYPASS                                          0xC1106C
71 
72 #endif /* ASIC_REG_MMU_UP_REGS_H_ */
73