1 /***************************************************************************** 2 * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. 3 * 4 * Unless you and Broadcom execute a separate written software license 5 * agreement governing use of this software, this software is licensed to you 6 * under the terms of the GNU General Public License version 2, available at 7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). 8 * 9 * Notwithstanding the above, under no circumstances may you combine this 10 * software in any way with any other Broadcom software provided under a 11 * license other than the GPL, without Broadcom's express prior written 12 * consent. 13 *****************************************************************************/ 14 15 #ifndef MEMORY_SETTINGS_H 16 #define MEMORY_SETTINGS_H 17 18 /* ---- Include Files ---------------------------------------- */ 19 /* ---- Constants and Types ---------------------------------- */ 20 21 /* Memory devices */ 22 /* NAND Flash timing for 166 MHz setting */ 23 #define HW_CFG_NAND_tBTA (5 << 16) /* Bus turnaround cycle (n) 0-7 (30 ns) */ 24 #define HW_CFG_NAND_tWP (4 << 11) /* Write pulse width cycle (n+1) 0-31 (25 ns) */ 25 #define HW_CFG_NAND_tWR (1 << 9) /* Write recovery cycle (n+1) 0-3 (10 ns) */ 26 #define HW_CFG_NAND_tAS (0 << 7) /* Write address setup cycle (n+1) 0-3 ( 0 ns) */ 27 #define HW_CFG_NAND_tOE (3 << 5) /* Output enable delay cycle (n) 0-3 (15 ns) */ 28 #define HW_CFG_NAND_tRC (7 << 0) /* Read access cycle (n+2) 0-31 (50 ns) */ 29 30 #define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \ 31 | HW_CFG_NAND_tWP \ 32 | HW_CFG_NAND_tWR \ 33 | HW_CFG_NAND_tAS \ 34 | HW_CFG_NAND_tOE \ 35 | HW_CFG_NAND_tRC) 36 37 /* NOR Flash timing for 166 MHz setting */ 38 #define HW_CFG_NOR_TPRC_TWLC (0 << 19) /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */ 39 #define HW_CFG_NOR_TBTA (0 << 16) /* Bus turnaround cycle (n) (DNA) */ 40 #define HW_CFG_NOR_TWP (6 << 11) /* Write pulse width cycle (n+1) (35ns) */ 41 #define HW_CFG_NOR_TWR (0 << 9) /* Write recovery cycle (n+1) (0ns) */ 42 #define HW_CFG_NOR_TAS (0 << 7) /* Write address setup cycle (n+1) (0ns) */ 43 #define HW_CFG_NOR_TOE (0 << 5) /* Output enable delay cycle (n) (max 25ns) */ 44 #define HW_CFG_NOR_TRC_TLC (0x10 << 0) /* Read access cycle / Burst read latency (n+2 / n+1) (100ns) */ 45 46 #define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \ 47 | HW_CFG_NOR_TBTA \ 48 | HW_CFG_NOR_TWP \ 49 | HW_CFG_NOR_TWR \ 50 | HW_CFG_NOR_TAS \ 51 | HW_CFG_NOR_TOE \ 52 | HW_CFG_NOR_TRC_TLC) 53 54 #define HW_CFG_FLASH1_TCR HW_CFG_FLASH0_TCR 55 #define HW_CFG_FLASH2_TCR HW_CFG_FLASH0_TCR 56 57 /* SDRAM Settings */ 58 /* #define HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */ 59 /* #define HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */ 60 /* #define HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */ 61 /* #define HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */ 62 #define HW_CFG_SDRAM_SIZE_BYTES 0x10000000 /* Total memory, not per device size */ 63 64 /* ---- Variable Externs ------------------------------------- */ 65 /* ---- Function Prototypes ---------------------------------- */ 66 67 #endif /* MEMORY_SETTINGS_H */ 68