1 /*****************************************************************************
2 * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3 *
4 * Unless you and Broadcom execute a separate written software license
5 * agreement governing use of this software, this software is licensed to you
6 * under the terms of the GNU General Public License version 2, available at
7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8 *
9 * Notwithstanding the above, under no circumstances may you combine this
10 * software in any way with any other Broadcom software provided under a
11 * license other than the GPL, without Broadcom's express prior written
12 * consent.
13 *****************************************************************************/
14
15 #ifndef CHIPC_INLINE_H
16 #define CHIPC_INLINE_H
17
18 /* ---- Include Files ----------------------------------------------------- */
19
20 #include <csp/errno.h>
21 #include <csp/reg.h>
22 #include <mach/csp/chipcHw_reg.h>
23 #include <mach/csp/chipcHw_def.h>
24
25 /* ---- Private Constants and Types --------------------------------------- */
26 typedef enum {
27 chipcHw_OPTYPE_BYPASS, /* Bypass operation */
28 chipcHw_OPTYPE_OUTPUT /* Output operation */
29 } chipcHw_OPTYPE_e;
30
31 /* ---- Public Constants and Types ---------------------------------------- */
32 /* ---- Public Variable Externs ------------------------------------------- */
33 /* ---- Public Function Prototypes ---------------------------------------- */
34 /* ---- Private Function Prototypes --------------------------------------- */
35 static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
36 chipcHw_OPTYPE_e type, int mode);
37
38 /****************************************************************************/
39 /**
40 * @brief Get Numeric Chip ID
41 *
42 * This function returns Chip ID that includes the revison number
43 *
44 * @return Complete numeric Chip ID
45 *
46 */
47 /****************************************************************************/
chipcHw_getChipId(void)48 static inline uint32_t chipcHw_getChipId(void)
49 {
50 return pChipcHw->ChipId;
51 }
52
53 /****************************************************************************/
54 /**
55 * @brief Enable Spread Spectrum
56 *
57 * @note chipcHw_Init() must be called earlier
58 */
59 /****************************************************************************/
chipcHw_enableSpreadSpectrum(void)60 static inline void chipcHw_enableSpreadSpectrum(void)
61 {
62 if ((pChipcHw->
63 PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
64 chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
65 ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
66 (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
67 (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
68 ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
69 ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
70 ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
71 }
72 }
73
74 /****************************************************************************/
75 /**
76 * @brief Disable Spread Spectrum
77 *
78 */
79 /****************************************************************************/
chipcHw_disableSpreadSpectrum(void)80 static inline void chipcHw_disableSpreadSpectrum(void)
81 {
82 ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
83 }
84
85 /****************************************************************************/
86 /**
87 * @brief Get Chip Product ID
88 *
89 * This function returns Chip Product ID
90 *
91 * @return Chip Product ID
92 */
93 /****************************************************************************/
chipcHw_getChipProductId(void)94 static inline uint32_t chipcHw_getChipProductId(void)
95 {
96 return (pChipcHw->
97 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
98 chipcHw_REG_CHIPID_BASE_SHIFT;
99 }
100
101 /****************************************************************************/
102 /**
103 * @brief Get revision number
104 *
105 * This function returns revision number of the chip
106 *
107 * @return Revision number
108 */
109 /****************************************************************************/
chipcHw_getChipRevisionNumber(void)110 static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
111 {
112 return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
113 }
114
115 /****************************************************************************/
116 /**
117 * @brief Enables bus interface clock
118 *
119 * Enables bus interface clock of various device
120 *
121 * @return void
122 *
123 * @note use chipcHw_REG_BUS_CLOCK_XXXX for mask
124 */
125 /****************************************************************************/
chipcHw_busInterfaceClockEnable(uint32_t mask)126 static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
127 {
128 reg32_modify_or(&pChipcHw->BusIntfClock, mask);
129 }
130
131 /****************************************************************************/
132 /**
133 * @brief Disables bus interface clock
134 *
135 * Disables bus interface clock of various device
136 *
137 * @return void
138 *
139 * @note use chipcHw_REG_BUS_CLOCK_XXXX
140 */
141 /****************************************************************************/
chipcHw_busInterfaceClockDisable(uint32_t mask)142 static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
143 {
144 reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
145 }
146
147 /****************************************************************************/
148 /**
149 * @brief Get status (enabled/disabled) of bus interface clock
150 *
151 * This function returns the status of devices' bus interface clock
152 *
153 * @return Bus interface clock
154 *
155 */
156 /****************************************************************************/
chipcHw_getBusInterfaceClockStatus(void)157 static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
158 {
159 return pChipcHw->BusIntfClock;
160 }
161
162 /****************************************************************************/
163 /**
164 * @brief Enables various audio channels
165 *
166 * Enables audio channel
167 *
168 * @return void
169 *
170 * @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
171 */
172 /****************************************************************************/
chipcHw_audioChannelEnable(uint32_t mask)173 static inline void chipcHw_audioChannelEnable(uint32_t mask)
174 {
175 reg32_modify_or(&pChipcHw->AudioEnable, mask);
176 }
177
178 /****************************************************************************/
179 /**
180 * @brief Disables various audio channels
181 *
182 * Disables audio channel
183 *
184 * @return void
185 *
186 * @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
187 */
188 /****************************************************************************/
chipcHw_audioChannelDisable(uint32_t mask)189 static inline void chipcHw_audioChannelDisable(uint32_t mask)
190 {
191 reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
192 }
193
194 /****************************************************************************/
195 /**
196 * @brief Soft resets devices
197 *
198 * Soft resets various devices
199 *
200 * @return void
201 *
202 * @note use chipcHw_REG_SOFT_RESET_XXXXXX defines
203 */
204 /****************************************************************************/
chipcHw_softReset(uint64_t mask)205 static inline void chipcHw_softReset(uint64_t mask)
206 {
207 chipcHw_softResetEnable(mask);
208 chipcHw_softResetDisable(mask);
209 }
210
chipcHw_softResetDisable(uint64_t mask)211 static inline void chipcHw_softResetDisable(uint64_t mask)
212 {
213 uint32_t ctrl1 = (uint32_t) mask;
214 uint32_t ctrl2 = (uint32_t) (mask >> 32);
215
216 /* Deassert module soft reset */
217 REG_LOCAL_IRQ_SAVE;
218 pChipcHw->SoftReset1 ^= ctrl1;
219 pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
220 REG_LOCAL_IRQ_RESTORE;
221 }
222
chipcHw_softResetEnable(uint64_t mask)223 static inline void chipcHw_softResetEnable(uint64_t mask)
224 {
225 uint32_t ctrl1 = (uint32_t) mask;
226 uint32_t ctrl2 = (uint32_t) (mask >> 32);
227 uint32_t unhold = 0;
228
229 REG_LOCAL_IRQ_SAVE;
230 pChipcHw->SoftReset1 |= ctrl1;
231 /* Mask out unhold request bits */
232 pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
233
234 /* Process unhold requests */
235 if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
236 unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
237 }
238
239 if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
240 unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
241 }
242
243 if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
244 unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
245 }
246
247 if (unhold) {
248 /* Make sure unhold request is effective */
249 pChipcHw->SoftReset1 &= ~unhold;
250 }
251 REG_LOCAL_IRQ_RESTORE;
252 }
253
254 /****************************************************************************/
255 /**
256 * @brief Configures misc CHIP functionality
257 *
258 * Configures CHIP functionality
259 *
260 * @return void
261 *
262 * @note use chipcHw_REG_MISC_CTRL_XXXXXX
263 */
264 /****************************************************************************/
chipcHw_miscControl(uint32_t mask)265 static inline void chipcHw_miscControl(uint32_t mask)
266 {
267 reg32_write(&pChipcHw->MiscCtrl, mask);
268 }
269
chipcHw_miscControlDisable(uint32_t mask)270 static inline void chipcHw_miscControlDisable(uint32_t mask)
271 {
272 reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
273 }
274
chipcHw_miscControlEnable(uint32_t mask)275 static inline void chipcHw_miscControlEnable(uint32_t mask)
276 {
277 reg32_modify_or(&pChipcHw->MiscCtrl, mask);
278 }
279
280 /****************************************************************************/
281 /**
282 * @brief Set OTP options
283 *
284 * Set OTP options
285 *
286 * @return void
287 *
288 * @note use chipcHw_REG_OTP_XXXXXX
289 */
290 /****************************************************************************/
chipcHw_setOTPOption(uint64_t mask)291 static inline void chipcHw_setOTPOption(uint64_t mask)
292 {
293 uint32_t ctrl1 = (uint32_t) mask;
294 uint32_t ctrl2 = (uint32_t) (mask >> 32);
295
296 reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
297 reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
298 }
299
300 /****************************************************************************/
301 /**
302 * @brief Get sticky bits
303 *
304 * @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
305 *
306 */
307 /****************************************************************************/
chipcHw_getStickyBits(void)308 static inline uint32_t chipcHw_getStickyBits(void)
309 {
310 return pChipcHw->Sticky;
311 }
312
313 /****************************************************************************/
314 /**
315 * @brief Set sticky bits
316 *
317 * @return void
318 *
319 * @note use chipcHw_REG_STICKY_XXXXXX
320 */
321 /****************************************************************************/
chipcHw_setStickyBits(uint32_t mask)322 static inline void chipcHw_setStickyBits(uint32_t mask)
323 {
324 uint32_t bits = 0;
325
326 REG_LOCAL_IRQ_SAVE;
327 if (mask & chipcHw_REG_STICKY_POR_BROM) {
328 bits |= chipcHw_REG_STICKY_POR_BROM;
329 } else {
330 uint32_t sticky;
331 sticky = pChipcHw->Sticky;
332
333 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
334 && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
335 bits |= chipcHw_REG_STICKY_BOOT_DONE;
336 }
337 if ((mask & chipcHw_REG_STICKY_GENERAL_1)
338 && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
339 bits |= chipcHw_REG_STICKY_GENERAL_1;
340 }
341 if ((mask & chipcHw_REG_STICKY_GENERAL_2)
342 && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
343 bits |= chipcHw_REG_STICKY_GENERAL_2;
344 }
345 if ((mask & chipcHw_REG_STICKY_GENERAL_3)
346 && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
347 bits |= chipcHw_REG_STICKY_GENERAL_3;
348 }
349 if ((mask & chipcHw_REG_STICKY_GENERAL_4)
350 && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
351 bits |= chipcHw_REG_STICKY_GENERAL_4;
352 }
353 if ((mask & chipcHw_REG_STICKY_GENERAL_5)
354 && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
355 bits |= chipcHw_REG_STICKY_GENERAL_5;
356 }
357 }
358 pChipcHw->Sticky = bits;
359 REG_LOCAL_IRQ_RESTORE;
360 }
361
362 /****************************************************************************/
363 /**
364 * @brief Clear sticky bits
365 *
366 * @return void
367 *
368 * @note use chipcHw_REG_STICKY_XXXXXX
369 */
370 /****************************************************************************/
chipcHw_clearStickyBits(uint32_t mask)371 static inline void chipcHw_clearStickyBits(uint32_t mask)
372 {
373 uint32_t bits = 0;
374
375 REG_LOCAL_IRQ_SAVE;
376 if (mask &
377 (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
378 chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
379 chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
380 uint32_t sticky = pChipcHw->Sticky;
381
382 if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
383 && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
384 bits = chipcHw_REG_STICKY_BOOT_DONE;
385 mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
386 }
387 if ((mask & chipcHw_REG_STICKY_GENERAL_1)
388 && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
389 bits |= chipcHw_REG_STICKY_GENERAL_1;
390 mask &= ~chipcHw_REG_STICKY_GENERAL_1;
391 }
392 if ((mask & chipcHw_REG_STICKY_GENERAL_2)
393 && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
394 bits |= chipcHw_REG_STICKY_GENERAL_2;
395 mask &= ~chipcHw_REG_STICKY_GENERAL_2;
396 }
397 if ((mask & chipcHw_REG_STICKY_GENERAL_3)
398 && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
399 bits |= chipcHw_REG_STICKY_GENERAL_3;
400 mask &= ~chipcHw_REG_STICKY_GENERAL_3;
401 }
402 if ((mask & chipcHw_REG_STICKY_GENERAL_4)
403 && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
404 bits |= chipcHw_REG_STICKY_GENERAL_4;
405 mask &= ~chipcHw_REG_STICKY_GENERAL_4;
406 }
407 if ((mask & chipcHw_REG_STICKY_GENERAL_5)
408 && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
409 bits |= chipcHw_REG_STICKY_GENERAL_5;
410 mask &= ~chipcHw_REG_STICKY_GENERAL_5;
411 }
412 }
413 pChipcHw->Sticky = bits | mask;
414 REG_LOCAL_IRQ_RESTORE;
415 }
416
417 /****************************************************************************/
418 /**
419 * @brief Get software strap value
420 *
421 * Retrieves software strap value
422 *
423 * @return Software strap value
424 *
425 */
426 /****************************************************************************/
chipcHw_getSoftStraps(void)427 static inline uint32_t chipcHw_getSoftStraps(void)
428 {
429 return pChipcHw->SoftStraps;
430 }
431
432 /****************************************************************************/
433 /**
434 * @brief Set software override strap options
435 *
436 * set software override strap options
437 *
438 * @return nothing
439 *
440 */
441 /****************************************************************************/
chipcHw_setSoftStraps(uint32_t strapOptions)442 static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
443 {
444 reg32_write(&pChipcHw->SoftStraps, strapOptions);
445 }
446
447 /****************************************************************************/
448 /**
449 * @brief Get Pin Strap Options
450 *
451 * This function returns the raw boot strap options
452 *
453 * @return strap options
454 *
455 */
456 /****************************************************************************/
chipcHw_getPinStraps(void)457 static inline uint32_t chipcHw_getPinStraps(void)
458 {
459 return pChipcHw->PinStraps;
460 }
461
462 /****************************************************************************/
463 /**
464 * @brief Get Valid Strap Options
465 *
466 * This function returns the valid raw boot strap options
467 *
468 * @return strap options
469 *
470 */
471 /****************************************************************************/
chipcHw_getValidStraps(void)472 static inline uint32_t chipcHw_getValidStraps(void)
473 {
474 uint32_t softStraps;
475
476 /*
477 ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
478 ** which copies HW straps to soft straps if there is no override
479 */
480 softStraps = chipcHw_getSoftStraps();
481
482 return softStraps;
483 }
484
485 /****************************************************************************/
486 /**
487 * @brief Initialize valid pin strap options
488 *
489 * Retrieves valid pin strap options by copying HW strap options to soft register
490 * (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
491 *
492 * @return nothing
493 *
494 */
495 /****************************************************************************/
chipcHw_initValidStraps(void)496 static inline void chipcHw_initValidStraps(void)
497 {
498 uint32_t softStraps;
499
500 REG_LOCAL_IRQ_SAVE;
501 softStraps = chipcHw_getSoftStraps();
502
503 if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
504 /* Copy HW straps to software straps */
505 chipcHw_setSoftStraps(chipcHw_getPinStraps());
506 }
507 REG_LOCAL_IRQ_RESTORE;
508 }
509
510 /****************************************************************************/
511 /**
512 * @brief Get boot device
513 *
514 * This function returns the device type used in booting the system
515 *
516 * @return Boot device of type chipcHw_BOOT_DEVICE
517 *
518 */
519 /****************************************************************************/
chipcHw_getBootDevice(void)520 static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
521 {
522 return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
523 }
524
525 /****************************************************************************/
526 /**
527 * @brief Get boot mode
528 *
529 * This function returns the way the system was booted
530 *
531 * @return Boot mode of type chipcHw_BOOT_MODE
532 *
533 */
534 /****************************************************************************/
chipcHw_getBootMode(void)535 static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
536 {
537 return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
538 }
539
540 /****************************************************************************/
541 /**
542 * @brief Get NAND flash page size
543 *
544 * This function returns the NAND device page size
545 *
546 * @return Boot NAND device page size
547 *
548 */
549 /****************************************************************************/
chipcHw_getNandPageSize(void)550 static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
551 {
552 return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
553 }
554
555 /****************************************************************************/
556 /**
557 * @brief Get NAND flash address cycle configuration
558 *
559 * This function returns the NAND flash address cycle configuration
560 *
561 * @return 0 = Do not extra address cycle, 1 = Add extra cycle
562 *
563 */
564 /****************************************************************************/
chipcHw_getNandExtraCycle(void)565 static inline int chipcHw_getNandExtraCycle(void)
566 {
567 if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
568 return 1;
569 } else {
570 return 0;
571 }
572 }
573
574 /****************************************************************************/
575 /**
576 * @brief Activates PIF interface
577 *
578 * This function activates PIF interface by taking control of LCD pins
579 *
580 * @note
581 * When activated, LCD pins will be defined as follows for PIF operation
582 *
583 * CLD[17:0] = pif_data[17:0]
584 * CLD[23:18] = pif_address[5:0]
585 * CLPOWER = pif_wr_str
586 * CLCP = pif_rd_str
587 * CLAC = pif_hat1
588 * CLFP = pif_hrdy1
589 * CLLP = pif_hat2
590 * GPIO[42] = pif_hrdy2
591 *
592 * In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
593 *
594 */
595 /****************************************************************************/
chipcHw_activatePifInterface(void)596 static inline void chipcHw_activatePifInterface(void)
597 {
598 reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
599 }
600
601 /****************************************************************************/
602 /**
603 * @brief Activates LCD interface
604 *
605 * This function activates LCD interface
606 *
607 * @note
608 * When activated, LCD pins will be defined as follows
609 *
610 * CLD[17:0] = LCD data
611 * CLD[23:18] = LCD data
612 * CLPOWER = LCD power
613 * CLCP =
614 * CLAC = LCD ack
615 * CLFP =
616 * CLLP =
617 */
618 /****************************************************************************/
chipcHw_activateLcdInterface(void)619 static inline void chipcHw_activateLcdInterface(void)
620 {
621 reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
622 }
623
624 /****************************************************************************/
625 /**
626 * @brief Deactivates PIF/LCD interface
627 *
628 * This function deactivates PIF/LCD interface
629 *
630 * @note
631 * When deactivated LCD pins will be in rti-stated
632 *
633 */
634 /****************************************************************************/
chipcHw_deactivatePifLcdInterface(void)635 static inline void chipcHw_deactivatePifLcdInterface(void)
636 {
637 reg32_write(&pChipcHw->LcdPifMode, 0);
638 }
639
640 /****************************************************************************/
641 /**
642 * @brief Select GE2
643 *
644 * This function select GE2 as the graphic engine
645 *
646 */
647 /****************************************************************************/
chipcHw_selectGE2(void)648 static inline void chipcHw_selectGE2(void)
649 {
650 reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
651 }
652
653 /****************************************************************************/
654 /**
655 * @brief Select GE3
656 *
657 * This function select GE3 as the graphic engine
658 *
659 */
660 /****************************************************************************/
chipcHw_selectGE3(void)661 static inline void chipcHw_selectGE3(void)
662 {
663 reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
664 }
665
666 /****************************************************************************/
667 /**
668 * @brief Get to know the configuration of GPIO pin
669 *
670 */
671 /****************************************************************************/
chipcHw_getGpioPinFunction(int pin)672 static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
673 {
674 return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
675 (chipcHw_REG_GPIO_MUX_MASK <<
676 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
677 chipcHw_REG_GPIO_MUX_POSITION(pin);
678 }
679
680 /****************************************************************************/
681 /**
682 * @brief Configure GPIO pin function
683 *
684 */
685 /****************************************************************************/
chipcHw_setGpioPinFunction(int pin,chipcHw_GPIO_FUNCTION_e func)686 static inline void chipcHw_setGpioPinFunction(int pin,
687 chipcHw_GPIO_FUNCTION_e func)
688 {
689 REG_LOCAL_IRQ_SAVE;
690 *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
691 ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
692 *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
693 func << chipcHw_REG_GPIO_MUX_POSITION(pin);
694 REG_LOCAL_IRQ_RESTORE;
695 }
696
697 /****************************************************************************/
698 /**
699 * @brief Set Pin slew rate
700 *
701 * This function sets the slew of individual pin
702 *
703 */
704 /****************************************************************************/
chipcHw_setPinSlewRate(uint32_t pin,chipcHw_PIN_SLEW_RATE_e slewRate)705 static inline void chipcHw_setPinSlewRate(uint32_t pin,
706 chipcHw_PIN_SLEW_RATE_e slewRate)
707 {
708 REG_LOCAL_IRQ_SAVE;
709 *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
710 ~(chipcHw_REG_SLEW_RATE_MASK <<
711 chipcHw_REG_SLEW_RATE_POSITION(pin));
712 *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
713 (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
714 REG_LOCAL_IRQ_RESTORE;
715 }
716
717 /****************************************************************************/
718 /**
719 * @brief Set Pin output drive current
720 *
721 * This function sets output drive current of individual pin
722 *
723 * Note: Avoid the use of the word 'current' since linux headers define this
724 * to be the current task.
725 */
726 /****************************************************************************/
chipcHw_setPinOutputCurrent(uint32_t pin,chipcHw_PIN_CURRENT_STRENGTH_e curr)727 static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
728 chipcHw_PIN_CURRENT_STRENGTH_e
729 curr)
730 {
731 REG_LOCAL_IRQ_SAVE;
732 *((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
733 ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
734 *((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
735 (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
736 REG_LOCAL_IRQ_RESTORE;
737 }
738
739 /****************************************************************************/
740 /**
741 * @brief Set Pin pullup register
742 *
743 * This function sets pullup register of individual pin
744 *
745 */
746 /****************************************************************************/
chipcHw_setPinPullup(uint32_t pin,chipcHw_PIN_PULL_e pullup)747 static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup)
748 {
749 REG_LOCAL_IRQ_SAVE;
750 *((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
751 ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
752 *((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
753 (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
754 REG_LOCAL_IRQ_RESTORE;
755 }
756
757 /****************************************************************************/
758 /**
759 * @brief Set Pin input type
760 *
761 * This function sets input type of individual pin
762 *
763 */
764 /****************************************************************************/
chipcHw_setPinInputType(uint32_t pin,chipcHw_PIN_INPUTTYPE_e inputType)765 static inline void chipcHw_setPinInputType(uint32_t pin,
766 chipcHw_PIN_INPUTTYPE_e inputType)
767 {
768 REG_LOCAL_IRQ_SAVE;
769 *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
770 ~(chipcHw_REG_INPUTTYPE_MASK <<
771 chipcHw_REG_INPUTTYPE_POSITION(pin));
772 *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
773 (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
774 REG_LOCAL_IRQ_RESTORE;
775 }
776
777 /****************************************************************************/
778 /**
779 * @brief Power up the USB PHY
780 *
781 * This function powers up the USB PHY
782 *
783 */
784 /****************************************************************************/
chipcHw_powerUpUsbPhy(void)785 static inline void chipcHw_powerUpUsbPhy(void)
786 {
787 reg32_modify_and(&pChipcHw->MiscCtrl,
788 chipcHw_REG_MISC_CTRL_USB_POWERON);
789 }
790
791 /****************************************************************************/
792 /**
793 * @brief Power down the USB PHY
794 *
795 * This function powers down the USB PHY
796 *
797 */
798 /****************************************************************************/
chipcHw_powerDownUsbPhy(void)799 static inline void chipcHw_powerDownUsbPhy(void)
800 {
801 reg32_modify_or(&pChipcHw->MiscCtrl,
802 chipcHw_REG_MISC_CTRL_USB_POWEROFF);
803 }
804
805 /****************************************************************************/
806 /**
807 * @brief Set the 2nd USB as host
808 *
809 * This function sets the 2nd USB as host
810 *
811 */
812 /****************************************************************************/
chipcHw_setUsbHost(void)813 static inline void chipcHw_setUsbHost(void)
814 {
815 reg32_modify_or(&pChipcHw->MiscCtrl,
816 chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
817 }
818
819 /****************************************************************************/
820 /**
821 * @brief Set the 2nd USB as device
822 *
823 * This function sets the 2nd USB as device
824 *
825 */
826 /****************************************************************************/
chipcHw_setUsbDevice(void)827 static inline void chipcHw_setUsbDevice(void)
828 {
829 reg32_modify_and(&pChipcHw->MiscCtrl,
830 chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
831 }
832
833 /****************************************************************************/
834 /**
835 * @brief Lower layer function to enable/disable a clock of a certain device
836 *
837 * This function enables/disables a core clock
838 *
839 */
840 /****************************************************************************/
chipcHw_setClock(chipcHw_CLOCK_e clock,chipcHw_OPTYPE_e type,int mode)841 static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
842 chipcHw_OPTYPE_e type, int mode)
843 {
844 volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
845 volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
846
847 switch (clock) {
848 case chipcHw_CLOCK_DDR:
849 pPLLReg = &pChipcHw->DDRClock;
850 break;
851 case chipcHw_CLOCK_ARM:
852 pPLLReg = &pChipcHw->ARMClock;
853 break;
854 case chipcHw_CLOCK_ESW:
855 pPLLReg = &pChipcHw->ESWClock;
856 break;
857 case chipcHw_CLOCK_VPM:
858 pPLLReg = &pChipcHw->VPMClock;
859 break;
860 case chipcHw_CLOCK_ESW125:
861 pPLLReg = &pChipcHw->ESW125Clock;
862 break;
863 case chipcHw_CLOCK_UART:
864 pPLLReg = &pChipcHw->UARTClock;
865 break;
866 case chipcHw_CLOCK_SDIO0:
867 pPLLReg = &pChipcHw->SDIO0Clock;
868 break;
869 case chipcHw_CLOCK_SDIO1:
870 pPLLReg = &pChipcHw->SDIO1Clock;
871 break;
872 case chipcHw_CLOCK_SPI:
873 pPLLReg = &pChipcHw->SPIClock;
874 break;
875 case chipcHw_CLOCK_ETM:
876 pPLLReg = &pChipcHw->ETMClock;
877 break;
878 case chipcHw_CLOCK_USB:
879 pPLLReg = &pChipcHw->USBClock;
880 if (type == chipcHw_OPTYPE_OUTPUT) {
881 if (mode) {
882 reg32_modify_and(pPLLReg,
883 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
884 } else {
885 reg32_modify_or(pPLLReg,
886 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
887 }
888 }
889 break;
890 case chipcHw_CLOCK_LCD:
891 pPLLReg = &pChipcHw->LCDClock;
892 if (type == chipcHw_OPTYPE_OUTPUT) {
893 if (mode) {
894 reg32_modify_and(pPLLReg,
895 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
896 } else {
897 reg32_modify_or(pPLLReg,
898 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
899 }
900 }
901 break;
902 case chipcHw_CLOCK_APM:
903 pPLLReg = &pChipcHw->APMClock;
904 if (type == chipcHw_OPTYPE_OUTPUT) {
905 if (mode) {
906 reg32_modify_and(pPLLReg,
907 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
908 } else {
909 reg32_modify_or(pPLLReg,
910 chipcHw_REG_PLL_CLOCK_POWER_DOWN);
911 }
912 }
913 break;
914 case chipcHw_CLOCK_BUS:
915 pClockCtrl = &pChipcHw->ACLKClock;
916 break;
917 case chipcHw_CLOCK_OTP:
918 pClockCtrl = &pChipcHw->OTPClock;
919 break;
920 case chipcHw_CLOCK_I2C:
921 pClockCtrl = &pChipcHw->I2CClock;
922 break;
923 case chipcHw_CLOCK_I2S0:
924 pClockCtrl = &pChipcHw->I2S0Clock;
925 break;
926 case chipcHw_CLOCK_RTBUS:
927 pClockCtrl = &pChipcHw->RTBUSClock;
928 break;
929 case chipcHw_CLOCK_APM100:
930 pClockCtrl = &pChipcHw->APM100Clock;
931 break;
932 case chipcHw_CLOCK_TSC:
933 pClockCtrl = &pChipcHw->TSCClock;
934 break;
935 case chipcHw_CLOCK_LED:
936 pClockCtrl = &pChipcHw->LEDClock;
937 break;
938 case chipcHw_CLOCK_I2S1:
939 pClockCtrl = &pChipcHw->I2S1Clock;
940 break;
941 }
942
943 if (pPLLReg) {
944 switch (type) {
945 case chipcHw_OPTYPE_OUTPUT:
946 /* PLL clock output enable/disable */
947 if (mode) {
948 if (clock == chipcHw_CLOCK_DDR) {
949 /* DDR clock enable is inverted */
950 reg32_modify_and(pPLLReg,
951 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
952 } else {
953 reg32_modify_or(pPLLReg,
954 chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
955 }
956 } else {
957 if (clock == chipcHw_CLOCK_DDR) {
958 /* DDR clock disable is inverted */
959 reg32_modify_or(pPLLReg,
960 chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
961 } else {
962 reg32_modify_and(pPLLReg,
963 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
964 }
965 }
966 break;
967 case chipcHw_OPTYPE_BYPASS:
968 /* PLL clock bypass enable/disable */
969 if (mode) {
970 reg32_modify_or(pPLLReg,
971 chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
972 } else {
973 reg32_modify_and(pPLLReg,
974 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
975 }
976 break;
977 }
978 } else if (pClockCtrl) {
979 switch (type) {
980 case chipcHw_OPTYPE_OUTPUT:
981 if (mode) {
982 reg32_modify_or(pClockCtrl,
983 chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
984 } else {
985 reg32_modify_and(pClockCtrl,
986 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
987 }
988 break;
989 case chipcHw_OPTYPE_BYPASS:
990 if (mode) {
991 reg32_modify_or(pClockCtrl,
992 chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
993 } else {
994 reg32_modify_and(pClockCtrl,
995 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
996 }
997 break;
998 }
999 }
1000 }
1001
1002 /****************************************************************************/
1003 /**
1004 * @brief Disables a core clock of a certain device
1005 *
1006 * This function disables a core clock
1007 *
1008 * @note no change in power consumption
1009 */
1010 /****************************************************************************/
chipcHw_setClockDisable(chipcHw_CLOCK_e clock)1011 static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
1012 {
1013
1014 /* Disable output of the clock */
1015 chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
1016 }
1017
1018 /****************************************************************************/
1019 /**
1020 * @brief Enable a core clock of a certain device
1021 *
1022 * This function enables a core clock
1023 *
1024 * @note no change in power consumption
1025 */
1026 /****************************************************************************/
chipcHw_setClockEnable(chipcHw_CLOCK_e clock)1027 static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
1028 {
1029
1030 /* Enable output of the clock */
1031 chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
1032 }
1033
1034 /****************************************************************************/
1035 /**
1036 * @brief Enables bypass clock of a certain device
1037 *
1038 * This function enables bypass clock
1039 *
1040 * @note Doesnot affect the bus interface clock
1041 */
1042 /****************************************************************************/
chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)1043 static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
1044 {
1045 /* Enable bypass clock */
1046 chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
1047 }
1048
1049 /****************************************************************************/
1050 /**
1051 * @brief Disabled bypass clock of a certain device
1052 *
1053 * This function disables bypass clock
1054 *
1055 * @note Doesnot affect the bus interface clock
1056 */
1057 /****************************************************************************/
chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)1058 static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
1059 {
1060 /* Disable bypass clock */
1061 chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
1062
1063 }
1064
1065 /****************************************************************************/
1066 /** @brief Checks if software strap is enabled
1067 *
1068 * @return 1 : When enable
1069 * 0 : When disable
1070 */
1071 /****************************************************************************/
chipcHw_isSoftwareStrapsEnable(void)1072 static inline int chipcHw_isSoftwareStrapsEnable(void)
1073 {
1074 return pChipcHw->SoftStraps & 0x00000001;
1075 }
1076
1077 /****************************************************************************/
1078 /** @brief Enable software strap
1079 */
1080 /****************************************************************************/
chipcHw_softwareStrapsEnable(void)1081 static inline void chipcHw_softwareStrapsEnable(void)
1082 {
1083 reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
1084 }
1085
1086 /****************************************************************************/
1087 /** @brief Disable software strap
1088 */
1089 /****************************************************************************/
chipcHw_softwareStrapsDisable(void)1090 static inline void chipcHw_softwareStrapsDisable(void)
1091 {
1092 reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
1093 }
1094
1095 /****************************************************************************/
1096 /** @brief PLL test enable
1097 */
1098 /****************************************************************************/
chipcHw_pllTestEnable(void)1099 static inline void chipcHw_pllTestEnable(void)
1100 {
1101 reg32_modify_or(&pChipcHw->PLLConfig,
1102 chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1103 }
1104
1105 /****************************************************************************/
1106 /** @brief PLL2 test enable
1107 */
1108 /****************************************************************************/
chipcHw_pll2TestEnable(void)1109 static inline void chipcHw_pll2TestEnable(void)
1110 {
1111 reg32_modify_or(&pChipcHw->PLLConfig2,
1112 chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1113 }
1114
1115 /****************************************************************************/
1116 /** @brief PLL test disable
1117 */
1118 /****************************************************************************/
chipcHw_pllTestDisable(void)1119 static inline void chipcHw_pllTestDisable(void)
1120 {
1121 reg32_modify_and(&pChipcHw->PLLConfig,
1122 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1123 }
1124
1125 /****************************************************************************/
1126 /** @brief PLL2 test disable
1127 */
1128 /****************************************************************************/
chipcHw_pll2TestDisable(void)1129 static inline void chipcHw_pll2TestDisable(void)
1130 {
1131 reg32_modify_and(&pChipcHw->PLLConfig2,
1132 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
1133 }
1134
1135 /****************************************************************************/
1136 /** @brief Get PLL test status
1137 */
1138 /****************************************************************************/
chipcHw_isPllTestEnable(void)1139 static inline int chipcHw_isPllTestEnable(void)
1140 {
1141 return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1142 }
1143
1144 /****************************************************************************/
1145 /** @brief Get PLL2 test status
1146 */
1147 /****************************************************************************/
chipcHw_isPll2TestEnable(void)1148 static inline int chipcHw_isPll2TestEnable(void)
1149 {
1150 return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
1151 }
1152
1153 /****************************************************************************/
1154 /** @brief PLL test select
1155 */
1156 /****************************************************************************/
chipcHw_pllTestSelect(uint32_t val)1157 static inline void chipcHw_pllTestSelect(uint32_t val)
1158 {
1159 REG_LOCAL_IRQ_SAVE;
1160 pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1161 pChipcHw->PLLConfig |=
1162 (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
1163 REG_LOCAL_IRQ_RESTORE;
1164 }
1165
1166 /****************************************************************************/
1167 /** @brief PLL2 test select
1168 */
1169 /****************************************************************************/
chipcHw_pll2TestSelect(uint32_t val)1170 static inline void chipcHw_pll2TestSelect(uint32_t val)
1171 {
1172
1173 REG_LOCAL_IRQ_SAVE;
1174 pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
1175 pChipcHw->PLLConfig2 |=
1176 (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
1177 REG_LOCAL_IRQ_RESTORE;
1178 }
1179
1180 /****************************************************************************/
1181 /** @brief Get PLL test selected option
1182 */
1183 /****************************************************************************/
chipcHw_getPllTestSelected(void)1184 static inline uint8_t chipcHw_getPllTestSelected(void)
1185 {
1186 return (uint8_t) ((pChipcHw->
1187 PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1188 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1189 }
1190
1191 /****************************************************************************/
1192 /** @brief Get PLL2 test selected option
1193 */
1194 /****************************************************************************/
chipcHw_getPll2TestSelected(void)1195 static inline uint8_t chipcHw_getPll2TestSelected(void)
1196 {
1197 return (uint8_t) ((pChipcHw->
1198 PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
1199 >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
1200 }
1201
1202 /****************************************************************************/
1203 /**
1204 * @brief Disable the PLL1
1205 *
1206 */
1207 /****************************************************************************/
chipcHw_pll1Disable(void)1208 static inline void chipcHw_pll1Disable(void)
1209 {
1210 REG_LOCAL_IRQ_SAVE;
1211 pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
1212 REG_LOCAL_IRQ_RESTORE;
1213 }
1214
1215 /****************************************************************************/
1216 /**
1217 * @brief Disable the PLL2
1218 *
1219 */
1220 /****************************************************************************/
chipcHw_pll2Disable(void)1221 static inline void chipcHw_pll2Disable(void)
1222 {
1223 REG_LOCAL_IRQ_SAVE;
1224 pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
1225 REG_LOCAL_IRQ_RESTORE;
1226 }
1227
1228 /****************************************************************************/
1229 /**
1230 * @brief Enables DDR SW phase alignment interrupt
1231 */
1232 /****************************************************************************/
chipcHw_ddrPhaseAlignInterruptEnable(void)1233 static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
1234 {
1235 REG_LOCAL_IRQ_SAVE;
1236 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
1237 REG_LOCAL_IRQ_RESTORE;
1238 }
1239
1240 /****************************************************************************/
1241 /**
1242 * @brief Disables DDR SW phase alignment interrupt
1243 */
1244 /****************************************************************************/
chipcHw_ddrPhaseAlignInterruptDisable(void)1245 static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
1246 {
1247 REG_LOCAL_IRQ_SAVE;
1248 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
1249 REG_LOCAL_IRQ_RESTORE;
1250 }
1251
1252 /****************************************************************************/
1253 /**
1254 * @brief Set VPM SW phase alignment interrupt mode
1255 *
1256 * This function sets VPM phase alignment interrupt
1257 */
1258 /****************************************************************************/
1259 static inline void
chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)1260 chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
1261 {
1262 REG_LOCAL_IRQ_SAVE;
1263 if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
1264 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1265 } else {
1266 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
1267 }
1268 pChipcHw->VPMPhaseCtrl2 =
1269 (pChipcHw->
1270 VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
1271 chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
1272 REG_LOCAL_IRQ_RESTORE;
1273 }
1274
1275 /****************************************************************************/
1276 /**
1277 * @brief Enable DDR phase alignment in software
1278 *
1279 */
1280 /****************************************************************************/
chipcHw_ddrSwPhaseAlignEnable(void)1281 static inline void chipcHw_ddrSwPhaseAlignEnable(void)
1282 {
1283 REG_LOCAL_IRQ_SAVE;
1284 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1285 REG_LOCAL_IRQ_RESTORE;
1286 }
1287
1288 /****************************************************************************/
1289 /**
1290 * @brief Disable DDR phase alignment in software
1291 *
1292 */
1293 /****************************************************************************/
chipcHw_ddrSwPhaseAlignDisable(void)1294 static inline void chipcHw_ddrSwPhaseAlignDisable(void)
1295 {
1296 REG_LOCAL_IRQ_SAVE;
1297 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1298 REG_LOCAL_IRQ_RESTORE;
1299 }
1300
1301 /****************************************************************************/
1302 /**
1303 * @brief Enable DDR phase alignment in hardware
1304 *
1305 */
1306 /****************************************************************************/
chipcHw_ddrHwPhaseAlignEnable(void)1307 static inline void chipcHw_ddrHwPhaseAlignEnable(void)
1308 {
1309 REG_LOCAL_IRQ_SAVE;
1310 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1311 REG_LOCAL_IRQ_RESTORE;
1312 }
1313
1314 /****************************************************************************/
1315 /**
1316 * @brief Disable DDR phase alignment in hardware
1317 *
1318 */
1319 /****************************************************************************/
chipcHw_ddrHwPhaseAlignDisable(void)1320 static inline void chipcHw_ddrHwPhaseAlignDisable(void)
1321 {
1322 REG_LOCAL_IRQ_SAVE;
1323 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1324 REG_LOCAL_IRQ_RESTORE;
1325 }
1326
1327 /****************************************************************************/
1328 /**
1329 * @brief Enable VPM phase alignment in software
1330 *
1331 */
1332 /****************************************************************************/
chipcHw_vpmSwPhaseAlignEnable(void)1333 static inline void chipcHw_vpmSwPhaseAlignEnable(void)
1334 {
1335 REG_LOCAL_IRQ_SAVE;
1336 pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
1337 REG_LOCAL_IRQ_RESTORE;
1338 }
1339
1340 /****************************************************************************/
1341 /**
1342 * @brief Disable VPM phase alignment in software
1343 *
1344 */
1345 /****************************************************************************/
chipcHw_vpmSwPhaseAlignDisable(void)1346 static inline void chipcHw_vpmSwPhaseAlignDisable(void)
1347 {
1348 REG_LOCAL_IRQ_SAVE;
1349 pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
1350 REG_LOCAL_IRQ_RESTORE;
1351 }
1352
1353 /****************************************************************************/
1354 /**
1355 * @brief Enable VPM phase alignment in hardware
1356 *
1357 */
1358 /****************************************************************************/
chipcHw_vpmHwPhaseAlignEnable(void)1359 static inline void chipcHw_vpmHwPhaseAlignEnable(void)
1360 {
1361 REG_LOCAL_IRQ_SAVE;
1362 pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
1363 REG_LOCAL_IRQ_RESTORE;
1364 }
1365
1366 /****************************************************************************/
1367 /**
1368 * @brief Disable VPM phase alignment in hardware
1369 *
1370 */
1371 /****************************************************************************/
chipcHw_vpmHwPhaseAlignDisable(void)1372 static inline void chipcHw_vpmHwPhaseAlignDisable(void)
1373 {
1374 REG_LOCAL_IRQ_SAVE;
1375 pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
1376 REG_LOCAL_IRQ_RESTORE;
1377 }
1378
1379 /****************************************************************************/
1380 /**
1381 * @brief Set DDR phase alignment margin in hardware
1382 *
1383 */
1384 /****************************************************************************/
1385 static inline void
chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)1386 chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
1387 {
1388 uint32_t ge = 0;
1389 uint32_t le = 0;
1390
1391 switch (margin) {
1392 case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
1393 ge = 0x0F;
1394 le = 0x0F;
1395 break;
1396 case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
1397 ge = 0x03;
1398 le = 0x3F;
1399 break;
1400 case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
1401 ge = 0x01;
1402 le = 0x7F;
1403 break;
1404 }
1405
1406 {
1407 REG_LOCAL_IRQ_SAVE;
1408
1409 pChipcHw->DDRPhaseCtrl1 &=
1410 ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
1411 chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
1412 || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
1413 chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
1414
1415 pChipcHw->DDRPhaseCtrl1 |=
1416 ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
1417 || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
1418
1419 REG_LOCAL_IRQ_RESTORE;
1420 }
1421 }
1422
1423 /****************************************************************************/
1424 /**
1425 * @brief Set VPM phase alignment margin in hardware
1426 *
1427 */
1428 /****************************************************************************/
1429 static inline void
chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)1430 chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
1431 {
1432 uint32_t ge = 0;
1433 uint32_t le = 0;
1434
1435 switch (margin) {
1436 case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
1437 ge = 0x0F;
1438 le = 0x0F;
1439 break;
1440 case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
1441 ge = 0x03;
1442 le = 0x3F;
1443 break;
1444 case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
1445 ge = 0x01;
1446 le = 0x7F;
1447 break;
1448 }
1449
1450 {
1451 REG_LOCAL_IRQ_SAVE;
1452
1453 pChipcHw->VPMPhaseCtrl1 &=
1454 ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
1455 chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
1456 || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
1457 chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
1458
1459 pChipcHw->VPMPhaseCtrl1 |=
1460 ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
1461 || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
1462
1463 REG_LOCAL_IRQ_RESTORE;
1464 }
1465 }
1466
1467 /****************************************************************************/
1468 /**
1469 * @brief Checks DDR phase aligned status done by HW
1470 *
1471 * @return 1: When aligned
1472 * 0: When not aligned
1473 */
1474 /****************************************************************************/
chipcHw_isDdrHwPhaseAligned(void)1475 static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
1476 {
1477 return (pChipcHw->
1478 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
1479 }
1480
1481 /****************************************************************************/
1482 /**
1483 * @brief Checks VPM phase aligned status done by HW
1484 *
1485 * @return 1: When aligned
1486 * 0: When not aligned
1487 */
1488 /****************************************************************************/
chipcHw_isVpmHwPhaseAligned(void)1489 static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
1490 {
1491 return (pChipcHw->
1492 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
1493 }
1494
1495 /****************************************************************************/
1496 /**
1497 * @brief Get DDR phase aligned status done by HW
1498 *
1499 */
1500 /****************************************************************************/
chipcHw_getDdrHwPhaseAlignStatus(void)1501 static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
1502 {
1503 return (pChipcHw->
1504 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
1505 chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
1506 }
1507
1508 /****************************************************************************/
1509 /**
1510 * @brief Get VPM phase aligned status done by HW
1511 *
1512 */
1513 /****************************************************************************/
chipcHw_getVpmHwPhaseAlignStatus(void)1514 static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
1515 {
1516 return (pChipcHw->
1517 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
1518 chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
1519 }
1520
1521 /****************************************************************************/
1522 /**
1523 * @brief Get DDR phase control value
1524 *
1525 */
1526 /****************************************************************************/
chipcHw_getDdrPhaseControl(void)1527 static inline uint32_t chipcHw_getDdrPhaseControl(void)
1528 {
1529 return (pChipcHw->
1530 PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
1531 chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
1532 }
1533
1534 /****************************************************************************/
1535 /**
1536 * @brief Get VPM phase control value
1537 *
1538 */
1539 /****************************************************************************/
chipcHw_getVpmPhaseControl(void)1540 static inline uint32_t chipcHw_getVpmPhaseControl(void)
1541 {
1542 return (pChipcHw->
1543 PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
1544 chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
1545 }
1546
1547 /****************************************************************************/
1548 /**
1549 * @brief DDR phase alignment timeout count
1550 *
1551 * @note If HW fails to perform the phase alignment, it will trigger
1552 * a DDR phase alignment timeout interrupt.
1553 */
1554 /****************************************************************************/
chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)1555 static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
1556 {
1557 REG_LOCAL_IRQ_SAVE;
1558 pChipcHw->DDRPhaseCtrl2 &=
1559 ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
1560 chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
1561 pChipcHw->DDRPhaseCtrl2 |=
1562 (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
1563 chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
1564 REG_LOCAL_IRQ_RESTORE;
1565 }
1566
1567 /****************************************************************************/
1568 /**
1569 * @brief VPM phase alignment timeout count
1570 *
1571 * @note If HW fails to perform the phase alignment, it will trigger
1572 * a VPM phase alignment timeout interrupt.
1573 */
1574 /****************************************************************************/
chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)1575 static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
1576 {
1577 REG_LOCAL_IRQ_SAVE;
1578 pChipcHw->VPMPhaseCtrl2 &=
1579 ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
1580 chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
1581 pChipcHw->VPMPhaseCtrl2 |=
1582 (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
1583 chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
1584 REG_LOCAL_IRQ_RESTORE;
1585 }
1586
1587 /****************************************************************************/
1588 /**
1589 * @brief Clear DDR phase alignment timeout interrupt
1590 *
1591 */
1592 /****************************************************************************/
chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)1593 static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
1594 {
1595 REG_LOCAL_IRQ_SAVE;
1596 /* Clear timeout interrupt service bit */
1597 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
1598 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
1599 REG_LOCAL_IRQ_RESTORE;
1600 }
1601
1602 /****************************************************************************/
1603 /**
1604 * @brief Clear VPM phase alignment timeout interrupt
1605 *
1606 */
1607 /****************************************************************************/
chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)1608 static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
1609 {
1610 REG_LOCAL_IRQ_SAVE;
1611 /* Clear timeout interrupt service bit */
1612 pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
1613 pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
1614 REG_LOCAL_IRQ_RESTORE;
1615 }
1616
1617 /****************************************************************************/
1618 /**
1619 * @brief DDR phase alignment timeout interrupt enable
1620 *
1621 */
1622 /****************************************************************************/
chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)1623 static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
1624 {
1625 REG_LOCAL_IRQ_SAVE;
1626 chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
1627 /* Enable timeout interrupt */
1628 pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1629 REG_LOCAL_IRQ_RESTORE;
1630 }
1631
1632 /****************************************************************************/
1633 /**
1634 * @brief VPM phase alignment timeout interrupt enable
1635 *
1636 */
1637 /****************************************************************************/
chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)1638 static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
1639 {
1640 REG_LOCAL_IRQ_SAVE;
1641 chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
1642 /* Enable timeout interrupt */
1643 pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1644 REG_LOCAL_IRQ_RESTORE;
1645 }
1646
1647 /****************************************************************************/
1648 /**
1649 * @brief DDR phase alignment timeout interrupt disable
1650 *
1651 */
1652 /****************************************************************************/
chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)1653 static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
1654 {
1655 REG_LOCAL_IRQ_SAVE;
1656 pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
1657 REG_LOCAL_IRQ_RESTORE;
1658 }
1659
1660 /****************************************************************************/
1661 /**
1662 * @brief VPM phase alignment timeout interrupt disable
1663 *
1664 */
1665 /****************************************************************************/
chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)1666 static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
1667 {
1668 REG_LOCAL_IRQ_SAVE;
1669 pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
1670 REG_LOCAL_IRQ_RESTORE;
1671 }
1672
1673 #endif /* CHIPC_INLINE_H */
1674