1/*
2 * ARM Ltd. Juno Platform
3 *
4 * Copyright (c) 2015 ARM Ltd.
5 *
6 * This file is licensed under a dual GPLv2 or BSD license.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/arm/coresight-cti-dt.h>
13#include "juno-base.dtsi"
14#include "juno-cs-r1r2.dtsi"
15
16/ {
17	model = "ARM Juno development board (r2)";
18	compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19	interrupt-parent = <&gic>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	aliases {
24		serial0 = &soc_uart0;
25	};
26
27	chosen {
28		stdout-path = "serial0:115200n8";
29	};
30
31	psci {
32		compatible = "arm,psci-0.2";
33		method = "smc";
34	};
35
36	cpus {
37		#address-cells = <2>;
38		#size-cells = <0>;
39
40		cpu-map {
41			cluster0 {
42				core0 {
43					cpu = <&A72_0>;
44				};
45				core1 {
46					cpu = <&A72_1>;
47				};
48			};
49
50			cluster1 {
51				core0 {
52					cpu = <&A53_0>;
53				};
54				core1 {
55					cpu = <&A53_1>;
56				};
57				core2 {
58					cpu = <&A53_2>;
59				};
60				core3 {
61					cpu = <&A53_3>;
62				};
63			};
64		};
65
66		idle-states {
67			entry-method = "psci";
68
69			CPU_SLEEP_0: cpu-sleep-0 {
70				compatible = "arm,idle-state";
71				arm,psci-suspend-param = <0x0010000>;
72				local-timer-stop;
73				entry-latency-us = <300>;
74				exit-latency-us = <1200>;
75				min-residency-us = <2000>;
76			};
77
78			CLUSTER_SLEEP_0: cluster-sleep-0 {
79				compatible = "arm,idle-state";
80				arm,psci-suspend-param = <0x1010000>;
81				local-timer-stop;
82				entry-latency-us = <400>;
83				exit-latency-us = <1200>;
84				min-residency-us = <2500>;
85			};
86		};
87
88		A72_0: cpu@0 {
89			compatible = "arm,cortex-a72";
90			reg = <0x0 0x0>;
91			device_type = "cpu";
92			enable-method = "psci";
93			i-cache-size = <0xc000>;
94			i-cache-line-size = <64>;
95			i-cache-sets = <256>;
96			d-cache-size = <0x8000>;
97			d-cache-line-size = <64>;
98			d-cache-sets = <256>;
99			next-level-cache = <&A72_L2>;
100			clocks = <&scpi_dvfs 0>;
101			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102			capacity-dmips-mhz = <1024>;
103			dynamic-power-coefficient = <450>;
104		};
105
106		A72_1: cpu@1 {
107			compatible = "arm,cortex-a72";
108			reg = <0x0 0x1>;
109			device_type = "cpu";
110			enable-method = "psci";
111			i-cache-size = <0xc000>;
112			i-cache-line-size = <64>;
113			i-cache-sets = <256>;
114			d-cache-size = <0x8000>;
115			d-cache-line-size = <64>;
116			d-cache-sets = <256>;
117			next-level-cache = <&A72_L2>;
118			clocks = <&scpi_dvfs 0>;
119			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
120			capacity-dmips-mhz = <1024>;
121			dynamic-power-coefficient = <450>;
122		};
123
124		A53_0: cpu@100 {
125			compatible = "arm,cortex-a53";
126			reg = <0x0 0x100>;
127			device_type = "cpu";
128			enable-method = "psci";
129			i-cache-size = <0x8000>;
130			i-cache-line-size = <64>;
131			i-cache-sets = <256>;
132			d-cache-size = <0x8000>;
133			d-cache-line-size = <64>;
134			d-cache-sets = <128>;
135			next-level-cache = <&A53_L2>;
136			clocks = <&scpi_dvfs 1>;
137			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
138			capacity-dmips-mhz = <485>;
139			dynamic-power-coefficient = <140>;
140		};
141
142		A53_1: cpu@101 {
143			compatible = "arm,cortex-a53";
144			reg = <0x0 0x101>;
145			device_type = "cpu";
146			enable-method = "psci";
147			i-cache-size = <0x8000>;
148			i-cache-line-size = <64>;
149			i-cache-sets = <256>;
150			d-cache-size = <0x8000>;
151			d-cache-line-size = <64>;
152			d-cache-sets = <128>;
153			next-level-cache = <&A53_L2>;
154			clocks = <&scpi_dvfs 1>;
155			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
156			capacity-dmips-mhz = <485>;
157			dynamic-power-coefficient = <140>;
158		};
159
160		A53_2: cpu@102 {
161			compatible = "arm,cortex-a53";
162			reg = <0x0 0x102>;
163			device_type = "cpu";
164			enable-method = "psci";
165			i-cache-size = <0x8000>;
166			i-cache-line-size = <64>;
167			i-cache-sets = <256>;
168			d-cache-size = <0x8000>;
169			d-cache-line-size = <64>;
170			d-cache-sets = <128>;
171			next-level-cache = <&A53_L2>;
172			clocks = <&scpi_dvfs 1>;
173			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
174			capacity-dmips-mhz = <485>;
175			dynamic-power-coefficient = <140>;
176		};
177
178		A53_3: cpu@103 {
179			compatible = "arm,cortex-a53";
180			reg = <0x0 0x103>;
181			device_type = "cpu";
182			enable-method = "psci";
183			i-cache-size = <0x8000>;
184			i-cache-line-size = <64>;
185			i-cache-sets = <256>;
186			d-cache-size = <0x8000>;
187			d-cache-line-size = <64>;
188			d-cache-sets = <128>;
189			next-level-cache = <&A53_L2>;
190			clocks = <&scpi_dvfs 1>;
191			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
192			capacity-dmips-mhz = <485>;
193			dynamic-power-coefficient = <140>;
194		};
195
196		A72_L2: l2-cache0 {
197			compatible = "cache";
198			cache-size = <0x200000>;
199			cache-line-size = <64>;
200			cache-sets = <2048>;
201			cache-level = <2>;
202		};
203
204		A53_L2: l2-cache1 {
205			compatible = "cache";
206			cache-size = <0x100000>;
207			cache-line-size = <64>;
208			cache-sets = <1024>;
209			cache-level = <2>;
210		};
211	};
212
213	pmu-a72 {
214		compatible = "arm,cortex-a72-pmu";
215		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
216			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
217		interrupt-affinity = <&A72_0>,
218				     <&A72_1>;
219	};
220
221	pmu-a53 {
222		compatible = "arm,cortex-a53-pmu";
223		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
224			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
225			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
226			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
227		interrupt-affinity = <&A53_0>,
228				     <&A53_1>,
229				     <&A53_2>,
230				     <&A53_3>;
231	};
232};
233
234&memtimer {
235	status = "okay";
236};
237
238&pcie_ctlr {
239	status = "okay";
240};
241
242&smmu_pcie {
243	status = "okay";
244};
245
246&etm0 {
247	cpu = <&A72_0>;
248};
249
250&etm1 {
251	cpu = <&A72_1>;
252};
253
254&etm2 {
255	cpu = <&A53_0>;
256};
257
258&etm3 {
259	cpu = <&A53_1>;
260};
261
262&etm4 {
263	cpu = <&A53_2>;
264};
265
266&etm5 {
267	cpu = <&A53_3>;
268};
269
270&big_cluster_thermal_zone {
271	status = "okay";
272};
273
274&little_cluster_thermal_zone {
275	status = "okay";
276};
277
278&gpu0_thermal_zone {
279	status = "okay";
280};
281
282&gpu1_thermal_zone {
283	status = "okay";
284};
285
286&etf0_out_port {
287	remote-endpoint = <&csys2_funnel_in_port0>;
288};
289
290&replicator_in_port0 {
291	remote-endpoint = <&csys2_funnel_out_port>;
292};
293
294&csys1_funnel_in_port0 {
295	remote-endpoint = <&stm_out_port>;
296};
297
298&stm_out_port {
299	remote-endpoint = <&csys1_funnel_in_port0>;
300};
301
302&cpu_debug0 {
303	cpu = <&A72_0>;
304};
305
306&cpu_debug1 {
307	cpu = <&A72_1>;
308};
309
310&cpu_debug2 {
311	cpu = <&A53_0>;
312};
313
314&cpu_debug3 {
315	cpu = <&A53_1>;
316};
317
318&cpu_debug4 {
319	cpu = <&A53_2>;
320};
321
322&cpu_debug5 {
323	cpu = <&A53_3>;
324};
325
326&cti0 {
327	cpu = <&A72_0>;
328};
329
330&cti1 {
331	cpu = <&A72_1>;
332};
333
334&cti2 {
335	cpu = <&A53_0>;
336};
337
338&cti3 {
339	cpu = <&A53_1>;
340};
341
342&cti4 {
343	cpu = <&A53_2>;
344};
345
346&cti5 {
347	cpu = <&A53_3>;
348};
349