1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Tegra host1x Interrupt Management
4 *
5 * Copyright (C) 2010 Google, Inc.
6 * Copyright (c) 2010-2013, NVIDIA Corporation.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/io.h>
12
13 #include "../intr.h"
14 #include "../dev.h"
15
16 /*
17 * Sync point threshold interrupt service function
18 * Handles sync point threshold triggers, in interrupt context
19 */
host1x_intr_syncpt_handle(struct host1x_syncpt * syncpt)20 static void host1x_intr_syncpt_handle(struct host1x_syncpt *syncpt)
21 {
22 unsigned int id = syncpt->id;
23 struct host1x *host = syncpt->host;
24
25 host1x_sync_writel(host, BIT(id % 32),
26 HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id / 32));
27 host1x_sync_writel(host, BIT(id % 32),
28 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id / 32));
29
30 schedule_work(&syncpt->intr.work);
31 }
32
syncpt_thresh_isr(int irq,void * dev_id)33 static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id)
34 {
35 struct host1x *host = dev_id;
36 unsigned long reg;
37 unsigned int i, id;
38
39 for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) {
40 reg = host1x_sync_readl(host,
41 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
42 for_each_set_bit(id, ®, 32) {
43 struct host1x_syncpt *syncpt =
44 host->syncpt + (i * 32 + id);
45 host1x_intr_syncpt_handle(syncpt);
46 }
47 }
48
49 return IRQ_HANDLED;
50 }
51
_host1x_intr_disable_all_syncpt_intrs(struct host1x * host)52 static void _host1x_intr_disable_all_syncpt_intrs(struct host1x *host)
53 {
54 unsigned int i;
55
56 for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); ++i) {
57 host1x_sync_writel(host, 0xffffffffu,
58 HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i));
59 host1x_sync_writel(host, 0xffffffffu,
60 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
61 }
62 }
63
intr_hw_init(struct host1x * host,u32 cpm)64 static void intr_hw_init(struct host1x *host, u32 cpm)
65 {
66 #if HOST1X_HW < 6
67 /* disable the ip_busy_timeout. this prevents write drops */
68 host1x_sync_writel(host, 0, HOST1X_SYNC_IP_BUSY_TIMEOUT);
69
70 /*
71 * increase the auto-ack timout to the maximum value. 2d will hang
72 * otherwise on Tegra2.
73 */
74 host1x_sync_writel(host, 0xff, HOST1X_SYNC_CTXSW_TIMEOUT_CFG);
75
76 /* update host clocks per usec */
77 host1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK);
78 #endif
79 #if HOST1X_HW >= 8
80 u32 id;
81
82 /*
83 * Program threshold interrupt destination among 8 lines per VM,
84 * per syncpoint. For now, just direct all to the first interrupt
85 * line.
86 */
87 for (id = 0; id < host->info->nb_pts; id++)
88 host1x_sync_writel(host, 0, HOST1X_SYNC_SYNCPT_INTR_DEST(id));
89 #endif
90 }
91
92 static int
_host1x_intr_init_host_sync(struct host1x * host,u32 cpm,void (* syncpt_thresh_work)(struct work_struct *))93 _host1x_intr_init_host_sync(struct host1x *host, u32 cpm,
94 void (*syncpt_thresh_work)(struct work_struct *))
95 {
96 unsigned int i;
97 int err;
98
99 host1x_hw_intr_disable_all_syncpt_intrs(host);
100
101 for (i = 0; i < host->info->nb_pts; i++)
102 INIT_WORK(&host->syncpt[i].intr.work, syncpt_thresh_work);
103
104 err = devm_request_irq(host->dev, host->intr_syncpt_irq,
105 syncpt_thresh_isr, IRQF_SHARED,
106 "host1x_syncpt", host);
107 if (err < 0) {
108 WARN_ON(1);
109 return err;
110 }
111
112 intr_hw_init(host, cpm);
113
114 return 0;
115 }
116
_host1x_intr_set_syncpt_threshold(struct host1x * host,unsigned int id,u32 thresh)117 static void _host1x_intr_set_syncpt_threshold(struct host1x *host,
118 unsigned int id,
119 u32 thresh)
120 {
121 host1x_sync_writel(host, thresh, HOST1X_SYNC_SYNCPT_INT_THRESH(id));
122 }
123
_host1x_intr_enable_syncpt_intr(struct host1x * host,unsigned int id)124 static void _host1x_intr_enable_syncpt_intr(struct host1x *host,
125 unsigned int id)
126 {
127 host1x_sync_writel(host, BIT(id % 32),
128 HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id / 32));
129 }
130
_host1x_intr_disable_syncpt_intr(struct host1x * host,unsigned int id)131 static void _host1x_intr_disable_syncpt_intr(struct host1x *host,
132 unsigned int id)
133 {
134 host1x_sync_writel(host, BIT(id % 32),
135 HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id / 32));
136 host1x_sync_writel(host, BIT(id % 32),
137 HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id / 32));
138 }
139
_host1x_free_syncpt_irq(struct host1x * host)140 static int _host1x_free_syncpt_irq(struct host1x *host)
141 {
142 unsigned int i;
143
144 devm_free_irq(host->dev, host->intr_syncpt_irq, host);
145
146 for (i = 0; i < host->info->nb_pts; i++)
147 cancel_work_sync(&host->syncpt[i].intr.work);
148
149 return 0;
150 }
151
152 static const struct host1x_intr_ops host1x_intr_ops = {
153 .init_host_sync = _host1x_intr_init_host_sync,
154 .set_syncpt_threshold = _host1x_intr_set_syncpt_threshold,
155 .enable_syncpt_intr = _host1x_intr_enable_syncpt_intr,
156 .disable_syncpt_intr = _host1x_intr_disable_syncpt_intr,
157 .disable_all_syncpt_intrs = _host1x_intr_disable_all_syncpt_intrs,
158 .free_syncpt_irq = _host1x_free_syncpt_irq,
159 };
160