1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18 #ifndef __linux_pxa2xx_spi_h
19 #define __linux_pxa2xx_spi_h
20
21 #include <linux/pxa2xx_ssp.h>
22
23 #define PXA2XX_CS_ASSERT (0x01)
24 #define PXA2XX_CS_DEASSERT (0x02)
25
26 /* device.platform_data for SSP controller devices */
27 struct pxa2xx_spi_master {
28 u32 clock_enable;
29 u16 num_chipselect;
30 u8 enable_dma;
31 };
32
33 /* spi_board_info.controller_data for SPI slave devices,
34 * copied to spi_device.platform_data ... mostly for dma tuning
35 */
36 struct pxa2xx_spi_chip {
37 u8 tx_threshold;
38 u8 rx_threshold;
39 u8 dma_burst_size;
40 u32 timeout;
41 u8 enable_loopback;
42 int gpio_cs;
43 void (*cs_control)(u32 command);
44 };
45
46 #ifdef CONFIG_ARCH_PXA
47
48 #include <linux/clk.h>
49 #include <mach/dma.h>
50
51 extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
52
53 #else
54 /*
55 * This is the implemtation for CE4100 on x86. ARM defines them in mach/ or
56 * plat/ include path.
57 * The CE4100 does not provide DMA support. This bits are here to let the driver
58 * compile and will never be used. Maybe we get DMA support at a later point in
59 * time.
60 */
61
62 #define DCSR(n) (n)
63 #define DSADR(n) (n)
64 #define DTADR(n) (n)
65 #define DCMD(n) (n)
66 #define DRCMR(n) (n)
67
68 #define DCSR_RUN (1 << 31) /* Run Bit */
69 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch */
70 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable */
71 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
72 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
73 #define DCSR_ENDINTR (1 << 2) /* End Interrupt */
74 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt */
75 #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt */
76
77 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable */
78 #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
79 #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
80 #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
81 #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
82 #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
83 #define DCSR_EORINTR (1 << 9) /* The end of Receive */
84
85 #define DRCMR_MAPVLD (1 << 7) /* Map Valid */
86 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number */
87
88 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor */
89 #define DDADR_STOP (1 << 0) /* Stop */
90
91 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
92 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
93 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
94 #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
95 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
96 #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
97 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
98 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
99 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
100 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
101 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
102 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
103 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
104 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
105
106 /*
107 * Descriptor structure for PXA's DMA engine
108 * Note: this structure must always be aligned to a 16-byte boundary.
109 */
110
111 typedef enum {
112 DMA_PRIO_HIGH = 0,
113 DMA_PRIO_MEDIUM = 1,
114 DMA_PRIO_LOW = 2
115 } pxa_dma_prio;
116
117 /*
118 * DMA registration
119 */
120
pxa_request_dma(char * name,pxa_dma_prio prio,void (* irq_handler)(int,void *),void * data)121 static inline int pxa_request_dma(char *name,
122 pxa_dma_prio prio,
123 void (*irq_handler)(int, void *),
124 void *data)
125 {
126 return -ENODEV;
127 }
128
pxa_free_dma(int dma_ch)129 static inline void pxa_free_dma(int dma_ch)
130 {
131 }
132
133 /*
134 * The CE4100 does not have the clk framework implemented and SPI clock can
135 * not be switched on/off or the divider changed.
136 */
clk_disable(struct clk * clk)137 static inline void clk_disable(struct clk *clk)
138 {
139 }
140
clk_enable(struct clk * clk)141 static inline int clk_enable(struct clk *clk)
142 {
143 return 0;
144 }
145
clk_get_rate(struct clk * clk)146 static inline unsigned long clk_get_rate(struct clk *clk)
147 {
148 return 3686400;
149 }
150
151 #endif
152 #endif
153