1 /* 2 * arch/ppc/kernel/mpc10x.h 3 * 4 * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem 5 * ctlr/EPIC/etc. 6 * 7 * Author: Mark A. Greer 8 * mgreer@mvista.com 9 * 10 * Copyright 2001 MontaVista Software Inc. 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License as published by the 14 * Free Software Foundation; either version 2 of the License, or (at your 15 * option) any later version. 16 */ 17 #ifndef __PPC_KERNEL_MPC10X_H 18 #define __PPC_KERNEL_MPC10X_H 19 20 #include <linux/pci_ids.h> 21 #include <asm/pci-bridge.h> 22 23 /* 24 * The values here don't completely map everything but should work in most 25 * cases. 26 * 27 * MAP A (PReP Map) 28 * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff 29 * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff 30 * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 31 * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) 32 * 33 * MAP B (CHRP Map) 34 * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff 35 * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff 36 * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 37 * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) 38 */ 39 40 /* 41 * Define the vendor/device IDs for the various bridges--should be added to 42 * <linux/pci_ids.h> 43 */ 44 #define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ 45 PCI_VENDOR_ID_MOTOROLA) 46 #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) 47 #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) 48 #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) 49 50 /* Define the type of map to use */ 51 #define MPC10X_MEM_MAP_A 1 52 #define MPC10X_MEM_MAP_B 2 53 54 /* Map A (PReP Map) Defines */ 55 #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 56 #define MPC10X_MAPA_CNFG_DATA 0x80000cfc 57 58 #define MPC10X_MAPA_ISA_IO_BASE 0x80000000 59 #define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000 60 #define MPC10X_MAPA_DRAM_OFFSET 0x80000000 61 62 #define MPC10X_MAPA_PCI_IO_START 0x00000000 63 #define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1) 64 #define MPC10X_MAPA_PCI_MEM_START 0x00000000 65 #define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1) 66 67 #define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \ 68 MPC10X_MAPA_PCI_MEM_START) 69 70 /* Map B (CHRP Map) Defines */ 71 #define MPC10X_MAPB_CNFG_ADDR 0xfec00000 72 #define MPC10X_MAPB_CNFG_DATA 0xfee00000 73 74 #define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 75 #define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 76 #define MPC10X_MAPB_DRAM_OFFSET 0x00000000 77 78 #define MPC10X_MAPB_PCI_IO_START 0x00000000 79 #define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) 80 #define MPC10X_MAPB_PCI_MEM_START 0x80000000 81 #define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) 82 83 #define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ 84 MPC10X_MAPB_PCI_MEM_START) 85 86 /* Set hose members to values appropriate for the mem map used */ 87 #define MPC10X_SETUP_HOSE(hose, map) { \ 88 (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET; \ 89 (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START; \ 90 (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END; \ 91 (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START; \ 92 (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END; \ 93 (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE; \ 94 } 95 96 97 /* Miscellaneous Configuration register offsets */ 98 #define MPC10X_CFG_PIR_REG 0x09 99 #define MPC10X_CFG_PIR_HOST_BRIDGE 0x00 100 #define MPC10X_CFG_PIR_AGENT 0x01 101 102 #define MPC10X_CFG_EUMBBAR 0x78 103 104 #define MPC10X_CFG_PICR1_REG 0xa8 105 #define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000 106 #define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000 107 #define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000 108 #define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 109 110 #define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 111 #define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ 112 #define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ 113 #define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ 114 #define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x80 /* PCI_COMPATIBILITY_HOLE */ 115 #define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x40 /* PROC_COMPATIBILITY_HOLE */ 116 117 /* Define offsets for the memory controller registers in the config space */ 118 #define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ 119 #define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ 120 #define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ 121 #define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ 122 123 #define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ 124 #define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ 125 #define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ 126 #define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ 127 128 #define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 129 130 /* Define some offset in the EUMB */ 131 #define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */ 132 133 #define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */ 134 #define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */ 135 #define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */ 136 #define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */ 137 #define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */ 138 #define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */ 139 #define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */ 140 #define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */ 141 #define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */ 142 #define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */ 143 #define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */ 144 #define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */ 145 #define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */ 146 #define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */ 147 #define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ 148 #define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ 149 150 /* 151 * Define some recommended places to put the EUMB regs. 152 * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff. 153 */ 154 extern unsigned long ioremap_base; 155 #define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE) 156 #define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE 157 158 159 int mpc10x_bridge_init(struct pci_controller *hose, 160 uint current_map, 161 uint new_map, 162 uint phys_eumb_base); 163 unsigned long mpc10x_get_mem_size(uint mem_map); 164 int mpc10x_enable_store_gathering(struct pci_controller *hose); 165 int mpc10x_disable_store_gathering(struct pci_controller *hose); 166 167 #endif /* __PPC_KERNEL_MPC10X_H */ 168