1 #ifndef _I386_PGTABLE_H
2 #define _I386_PGTABLE_H
3
4 #include <linux/config.h>
5
6 /*
7 * The Linux memory management assumes a three-level page table setup. On
8 * the i386, we use that, but "fold" the mid level into the top-level page
9 * table, so that we physically have the same two-level page table as the
10 * i386 mmu expects.
11 *
12 * This file contains the functions and defines necessary to modify and use
13 * the i386 page table tree.
14 */
15 #ifndef __ASSEMBLY__
16 #include <asm/processor.h>
17 #include <asm/fixmap.h>
18 #include <linux/threads.h>
19
20 #ifndef _I386_BITOPS_H
21 #include <asm/bitops.h>
22 #endif
23
24 extern pgd_t swapper_pg_dir[1024];
25 extern void paging_init(void);
26
27 /* Caches aren't brain-dead on the intel. */
28 #define flush_cache_all() do { } while (0)
29 #define flush_cache_mm(mm) do { } while (0)
30 #define flush_cache_range(mm, start, end) do { } while (0)
31 #define flush_cache_page(vma, vmaddr) do { } while (0)
32 #define flush_page_to_ram(page) do { } while (0)
33 #define flush_dcache_page(page) do { } while (0)
34 #define flush_icache_range(start, end) do { } while (0)
35 #define flush_icache_page(vma,pg) do { } while (0)
36 #define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
37
38 #define __flush_tlb() \
39 do { \
40 unsigned int tmpreg; \
41 \
42 __asm__ __volatile__( \
43 "movl %%cr3, %0; # flush TLB \n" \
44 "movl %0, %%cr3; \n" \
45 : "=r" (tmpreg) \
46 :: "memory"); \
47 } while (0)
48
49 /*
50 * Global pages have to be flushed a bit differently. Not a real
51 * performance problem because this does not happen often.
52 */
53 #define __flush_tlb_global() \
54 do { \
55 unsigned int tmpreg; \
56 \
57 __asm__ __volatile__( \
58 "movl %1, %%cr4; # turn off PGE \n" \
59 "movl %%cr3, %0; # flush TLB \n" \
60 "movl %0, %%cr3; \n" \
61 "movl %2, %%cr4; # turn PGE back on \n" \
62 : "=&r" (tmpreg) \
63 : "r" (mmu_cr4_features & ~X86_CR4_PGE), \
64 "r" (mmu_cr4_features) \
65 : "memory"); \
66 } while (0)
67
68 extern unsigned long pgkern_mask;
69
70 /*
71 * Do not check the PGE bit unnecesserily if this is a PPro+ kernel.
72 */
73 #ifdef CONFIG_X86_PGE
74 # define __flush_tlb_all() __flush_tlb_global()
75 #else
76 # define __flush_tlb_all() \
77 do { \
78 if (cpu_has_pge) \
79 __flush_tlb_global(); \
80 else \
81 __flush_tlb(); \
82 } while (0)
83 #endif
84
85 #define __flush_tlb_single(addr) \
86 __asm__ __volatile__("invlpg %0": :"m" (*(char *) addr))
87
88 #ifdef CONFIG_X86_INVLPG
89 # define __flush_tlb_one(addr) __flush_tlb_single(addr)
90 #else
91 # define __flush_tlb_one(addr) \
92 do { \
93 if (cpu_has_pge) \
94 __flush_tlb_single(addr); \
95 else \
96 __flush_tlb(); \
97 } while (0)
98 #endif
99
100 /*
101 * ZERO_PAGE is a global shared page that is always zero: used
102 * for zero-mapped memory areas etc..
103 */
104 extern unsigned long empty_zero_page[1024];
105 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
106
107 #endif /* !__ASSEMBLY__ */
108
109 /*
110 * The Linux x86 paging architecture is 'compile-time dual-mode', it
111 * implements both the traditional 2-level x86 page tables and the
112 * newer 3-level PAE-mode page tables.
113 */
114 #ifndef __ASSEMBLY__
115 #if CONFIG_X86_PAE
116 # include <asm/pgtable-3level.h>
117
118 /*
119 * Need to initialise the X86 PAE caches
120 */
121 extern void pgtable_cache_init(void);
122
123 #else
124 # include <asm/pgtable-2level.h>
125
126 /*
127 * No page table caches to initialise
128 */
129 #define pgtable_cache_init() do { } while (0)
130
131 #endif
132 #endif
133
134 #define __beep() asm("movb $0x3,%al; outb %al,$0x61")
135
136 #define PMD_SIZE (1UL << PMD_SHIFT)
137 #define PMD_MASK (~(PMD_SIZE-1))
138 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
139 #define PGDIR_MASK (~(PGDIR_SIZE-1))
140
141 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
142 #define FIRST_USER_PGD_NR 0
143
144 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
145 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
146
147 #define TWOLEVEL_PGDIR_SHIFT 22
148 #define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
149 #define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
150
151
152 #ifndef __ASSEMBLY__
153 /* Just any arbitrary offset to the start of the vmalloc VM area: the
154 * current 8MB value just means that there will be a 8MB "hole" after the
155 * physical memory until the kernel virtual memory starts. That means that
156 * any out-of-bounds memory accesses will hopefully be caught.
157 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
158 * area for the same reason. ;)
159 */
160 #define VMALLOC_OFFSET (8*1024*1024)
161 #define VMALLOC_START (((unsigned long) high_memory + 2*VMALLOC_OFFSET-1) & \
162 ~(VMALLOC_OFFSET-1))
163 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
164 #if CONFIG_HIGHMEM
165 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
166 #else
167 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
168 #endif
169
170 /*
171 * The 4MB page is guessing.. Detailed in the infamous "Chapter H"
172 * of the Pentium details, but assuming intel did the straightforward
173 * thing, this bit set in the page directory entry just means that
174 * the page directory entry points directly to a 4MB-aligned block of
175 * memory.
176 */
177 #define _PAGE_BIT_PRESENT 0
178 #define _PAGE_BIT_RW 1
179 #define _PAGE_BIT_USER 2
180 #define _PAGE_BIT_PWT 3
181 #define _PAGE_BIT_PCD 4
182 #define _PAGE_BIT_ACCESSED 5
183 #define _PAGE_BIT_DIRTY 6
184 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page, Pentium+, if present.. */
185 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
186
187 #define _PAGE_PRESENT 0x001
188 #define _PAGE_RW 0x002
189 #define _PAGE_USER 0x004
190 #define _PAGE_PWT 0x008
191 #define _PAGE_PCD 0x010
192 #define _PAGE_ACCESSED 0x020
193 #define _PAGE_DIRTY 0x040
194 #define _PAGE_PSE 0x080 /* 4 MB (or 2MB) page, Pentium+, if present.. */
195 #define _PAGE_GLOBAL 0x100 /* Global TLB entry PPro+ */
196
197 #define _PAGE_PROTNONE 0x080 /* If not present */
198
199 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
200 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
201 #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
202
203 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
204 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
205 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
206 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
207
208 #define __PAGE_KERNEL \
209 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
210 #define __PAGE_KERNEL_NOCACHE \
211 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_PCD | _PAGE_ACCESSED)
212 #define __PAGE_KERNEL_RO \
213 (_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED)
214
215 #ifdef CONFIG_X86_PGE
216 # define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL)
217 #else
218 # define MAKE_GLOBAL(x) \
219 ({ \
220 pgprot_t __ret; \
221 \
222 if (cpu_has_pge) \
223 __ret = __pgprot((x) | _PAGE_GLOBAL); \
224 else \
225 __ret = __pgprot(x); \
226 __ret; \
227 })
228 #endif
229
230 #define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL)
231 #define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO)
232 #define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE)
233
234 /*
235 * The i386 can't do page protection for execute, and considers that
236 * the same are read. Also, write permissions imply read permissions.
237 * This is the closest we can get..
238 */
239 #define __P000 PAGE_NONE
240 #define __P001 PAGE_READONLY
241 #define __P010 PAGE_COPY
242 #define __P011 PAGE_COPY
243 #define __P100 PAGE_READONLY
244 #define __P101 PAGE_READONLY
245 #define __P110 PAGE_COPY
246 #define __P111 PAGE_COPY
247
248 #define __S000 PAGE_NONE
249 #define __S001 PAGE_READONLY
250 #define __S010 PAGE_SHARED
251 #define __S011 PAGE_SHARED
252 #define __S100 PAGE_READONLY
253 #define __S101 PAGE_READONLY
254 #define __S110 PAGE_SHARED
255 #define __S111 PAGE_SHARED
256
257 /*
258 * Define this if things work differently on an i386 and an i486:
259 * it will (on an i486) warn about kernel memory accesses that are
260 * done without a 'verify_area(VERIFY_WRITE,..)'
261 */
262 #undef TEST_VERIFY_AREA
263
264 /* page table for 0-4MB for everybody */
265 extern unsigned long pg0[1024];
266
267 #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
268 #define pte_clear(xp) do { set_pte(xp, __pte(0)); } while (0)
269
270 #define pmd_none(x) (!pmd_val(x))
271 #define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
272 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
273 #define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
274
275
276 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
277
278 /*
279 * The following only work if pte_present() is true.
280 * Undefined behaviour if not..
281 */
pte_read(pte_t pte)282 static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
pte_exec(pte_t pte)283 static inline int pte_exec(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
pte_dirty(pte_t pte)284 static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; }
pte_young(pte_t pte)285 static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; }
pte_write(pte_t pte)286 static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; }
287
pte_rdprotect(pte_t pte)288 static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
pte_exprotect(pte_t pte)289 static inline pte_t pte_exprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
pte_mkclean(pte_t pte)290 static inline pte_t pte_mkclean(pte_t pte) { (pte).pte_low &= ~_PAGE_DIRTY; return pte; }
pte_mkold(pte_t pte)291 static inline pte_t pte_mkold(pte_t pte) { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; }
pte_wrprotect(pte_t pte)292 static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_RW; return pte; }
pte_mkread(pte_t pte)293 static inline pte_t pte_mkread(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
pte_mkexec(pte_t pte)294 static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
pte_mkdirty(pte_t pte)295 static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; }
pte_mkyoung(pte_t pte)296 static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
pte_mkwrite(pte_t pte)297 static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; }
298
ptep_test_and_clear_dirty(pte_t * ptep)299 static inline int ptep_test_and_clear_dirty(pte_t *ptep) { return test_and_clear_bit(_PAGE_BIT_DIRTY, ptep); }
ptep_test_and_clear_young(pte_t * ptep)300 static inline int ptep_test_and_clear_young(pte_t *ptep) { return test_and_clear_bit(_PAGE_BIT_ACCESSED, ptep); }
ptep_set_wrprotect(pte_t * ptep)301 static inline void ptep_set_wrprotect(pte_t *ptep) { clear_bit(_PAGE_BIT_RW, ptep); }
ptep_mkdirty(pte_t * ptep)302 static inline void ptep_mkdirty(pte_t *ptep) { set_bit(_PAGE_BIT_DIRTY, ptep); }
303
304 /*
305 * Conversion functions: convert a page and protection to a page entry,
306 * and a page entry and page directory to the page they refer to.
307 */
308
309 #define mk_pte(page, pgprot) __mk_pte((page) - mem_map, (pgprot))
310
311 /* This takes a physical page address that is used by the remapping functions */
312 #define mk_pte_phys(physpage, pgprot) __mk_pte((physpage) >> PAGE_SHIFT, pgprot)
313
pte_modify(pte_t pte,pgprot_t newprot)314 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
315 {
316 pte.pte_low &= _PAGE_CHG_MASK;
317 pte.pte_low |= pgprot_val(newprot);
318 return pte;
319 }
320
321 #define page_pte(page) page_pte_prot(page, __pgprot(0))
322
323 #define pmd_page(pmd) \
324 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
325
326 /* to find an entry in a page-table-directory. */
327 #define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
328
329 #define __pgd_offset(address) pgd_index(address)
330
331 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
332
333 /* to find an entry in a kernel page-table-directory */
334 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
335
336 #define __pmd_offset(address) \
337 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
338
339 /* Find an entry in the third-level page table.. */
340 #define __pte_offset(address) \
341 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
342 #define pte_offset(dir, address) ((pte_t *) pmd_page(*(dir)) + \
343 __pte_offset(address))
344
345 /*
346 * The i386 doesn't have any external MMU info: the kernel page
347 * tables contain all the necessary information.
348 */
349 #define update_mmu_cache(vma,address,pte) do { } while (0)
350
351 /* Encode and de-code a swap entry */
352 #define SWP_TYPE(x) (((x).val >> 1) & 0x3f)
353 #define SWP_OFFSET(x) ((x).val >> 8)
354 #define SWP_ENTRY(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
355 #define pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low })
356 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
357
358 struct page;
359 int change_page_attr(struct page *, int, pgprot_t prot);
360
361 #endif /* !__ASSEMBLY__ */
362
363 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
364 #define PageSkip(page) (0)
365 #define kern_addr_valid(addr) (1)
366
367 #define io_remap_page_range remap_page_range
368
369 #endif /* _I386_PGTABLE_H */
370