1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/interrupt-controller/irq.h>
6#include "imx6q-pinfunc.h"
7#include "imx6qdl.dtsi"
8
9/ {
10	aliases {
11		ipu1 = &ipu2;
12		spi4 = &ecspi5;
13	};
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			compatible = "arm,cortex-a9";
21			device_type = "cpu";
22			reg = <0>;
23			next-level-cache = <&L2>;
24			operating-points = <
25				/* kHz    uV */
26				1200000 1275000
27				996000  1250000
28				852000  1250000
29				792000  1175000
30				396000  975000
31			>;
32			fsl,soc-operating-points = <
33				/* ARM kHz  SOC-PU uV */
34				1200000 1275000
35				996000	1250000
36				852000	1250000
37				792000	1175000
38				396000	1175000
39			>;
40			clock-latency = <61036>; /* two CLK32 periods */
41			#cooling-cells = <2>;
42			clocks = <&clks IMX6QDL_CLK_ARM>,
43				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44				 <&clks IMX6QDL_CLK_STEP>,
45				 <&clks IMX6QDL_CLK_PLL1_SW>,
46				 <&clks IMX6QDL_CLK_PLL1_SYS>;
47			clock-names = "arm", "pll2_pfd2_396m", "step",
48				      "pll1_sw", "pll1_sys";
49			arm-supply = <&reg_arm>;
50			pu-supply = <&reg_pu>;
51			soc-supply = <&reg_soc>;
52			nvmem-cells = <&cpu_speed_grade>;
53			nvmem-cell-names = "speed_grade";
54		};
55
56		cpu1: cpu@1 {
57			compatible = "arm,cortex-a9";
58			device_type = "cpu";
59			reg = <1>;
60			next-level-cache = <&L2>;
61			operating-points = <
62				/* kHz    uV */
63				1200000 1275000
64				996000  1250000
65				852000  1250000
66				792000  1175000
67				396000  975000
68			>;
69			fsl,soc-operating-points = <
70				/* ARM kHz  SOC-PU uV */
71				1200000 1275000
72				996000	1250000
73				852000	1250000
74				792000	1175000
75				396000	1175000
76			>;
77			clock-latency = <61036>; /* two CLK32 periods */
78			#cooling-cells = <2>;
79			clocks = <&clks IMX6QDL_CLK_ARM>,
80				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
81				 <&clks IMX6QDL_CLK_STEP>,
82				 <&clks IMX6QDL_CLK_PLL1_SW>,
83				 <&clks IMX6QDL_CLK_PLL1_SYS>;
84			clock-names = "arm", "pll2_pfd2_396m", "step",
85				      "pll1_sw", "pll1_sys";
86			arm-supply = <&reg_arm>;
87			pu-supply = <&reg_pu>;
88			soc-supply = <&reg_soc>;
89		};
90
91		cpu2: cpu@2 {
92			compatible = "arm,cortex-a9";
93			device_type = "cpu";
94			reg = <2>;
95			next-level-cache = <&L2>;
96			operating-points = <
97				/* kHz    uV */
98				1200000 1275000
99				996000  1250000
100				852000  1250000
101				792000  1175000
102				396000  975000
103			>;
104			fsl,soc-operating-points = <
105				/* ARM kHz  SOC-PU uV */
106				1200000 1275000
107				996000	1250000
108				852000	1250000
109				792000	1175000
110				396000	1175000
111			>;
112			clock-latency = <61036>; /* two CLK32 periods */
113			#cooling-cells = <2>;
114			clocks = <&clks IMX6QDL_CLK_ARM>,
115				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
116				 <&clks IMX6QDL_CLK_STEP>,
117				 <&clks IMX6QDL_CLK_PLL1_SW>,
118				 <&clks IMX6QDL_CLK_PLL1_SYS>;
119			clock-names = "arm", "pll2_pfd2_396m", "step",
120				      "pll1_sw", "pll1_sys";
121			arm-supply = <&reg_arm>;
122			pu-supply = <&reg_pu>;
123			soc-supply = <&reg_soc>;
124		};
125
126		cpu3: cpu@3 {
127			compatible = "arm,cortex-a9";
128			device_type = "cpu";
129			reg = <3>;
130			next-level-cache = <&L2>;
131			operating-points = <
132				/* kHz    uV */
133				1200000 1275000
134				996000  1250000
135				852000  1250000
136				792000  1175000
137				396000  975000
138			>;
139			fsl,soc-operating-points = <
140				/* ARM kHz  SOC-PU uV */
141				1200000 1275000
142				996000	1250000
143				852000	1250000
144				792000	1175000
145				396000	1175000
146			>;
147			clock-latency = <61036>; /* two CLK32 periods */
148			#cooling-cells = <2>;
149			clocks = <&clks IMX6QDL_CLK_ARM>,
150				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
151				 <&clks IMX6QDL_CLK_STEP>,
152				 <&clks IMX6QDL_CLK_PLL1_SW>,
153				 <&clks IMX6QDL_CLK_PLL1_SYS>;
154			clock-names = "arm", "pll2_pfd2_396m", "step",
155				      "pll1_sw", "pll1_sys";
156			arm-supply = <&reg_arm>;
157			pu-supply = <&reg_pu>;
158			soc-supply = <&reg_soc>;
159		};
160	};
161
162	soc {
163		ocram: sram@900000 {
164			compatible = "mmio-sram";
165			reg = <0x00900000 0x40000>;
166			clocks = <&clks IMX6QDL_CLK_OCRAM>;
167		};
168
169		bus@2000000 { /* AIPS1 */
170			spba-bus@2000000 {
171				ecspi5: spi@2018000 {
172					#address-cells = <1>;
173					#size-cells = <0>;
174					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
175					reg = <0x02018000 0x4000>;
176					interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
177					clocks = <&clks IMX6Q_CLK_ECSPI5>,
178						 <&clks IMX6Q_CLK_ECSPI5>;
179					clock-names = "ipg", "per";
180					dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
181					dma-names = "rx", "tx";
182					status = "disabled";
183				};
184			};
185		};
186
187		sata: sata@2200000 {
188			compatible = "fsl,imx6q-ahci";
189			reg = <0x02200000 0x4000>;
190			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
191			clocks = <&clks IMX6QDL_CLK_SATA>,
192				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
193				 <&clks IMX6QDL_CLK_AHB>;
194			clock-names = "sata", "sata_ref", "ahb";
195			status = "disabled";
196		};
197
198		gpu_vg: gpu@2204000 {
199			compatible = "vivante,gc";
200			reg = <0x02204000 0x4000>;
201			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
202			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
203				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
204			clock-names = "bus", "core";
205			power-domains = <&pd_pu>;
206			#cooling-cells = <2>;
207		};
208
209		ipu2: ipu@2800000 {
210			#address-cells = <1>;
211			#size-cells = <0>;
212			compatible = "fsl,imx6q-ipu";
213			reg = <0x02800000 0x400000>;
214			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
215				     <0 7 IRQ_TYPE_LEVEL_HIGH>;
216			clocks = <&clks IMX6QDL_CLK_IPU2>,
217				 <&clks IMX6QDL_CLK_IPU2_DI0>,
218				 <&clks IMX6QDL_CLK_IPU2_DI1>;
219			clock-names = "bus", "di0", "di1";
220			resets = <&src 4>;
221
222			ipu2_csi0: port@0 {
223				reg = <0>;
224
225				ipu2_csi0_from_mipi_vc2: endpoint {
226					remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
227				};
228			};
229
230			ipu2_csi1: port@1 {
231				reg = <1>;
232
233				ipu2_csi1_from_ipu2_csi1_mux: endpoint {
234					remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
235				};
236			};
237
238			ipu2_di0: port@2 {
239				#address-cells = <1>;
240				#size-cells = <0>;
241				reg = <2>;
242
243				ipu2_di0_disp0: endpoint@0 {
244					reg = <0>;
245				};
246
247				ipu2_di0_hdmi: endpoint@1 {
248					reg = <1>;
249					remote-endpoint = <&hdmi_mux_2>;
250				};
251
252				ipu2_di0_mipi: endpoint@2 {
253					reg = <2>;
254					remote-endpoint = <&mipi_mux_2>;
255				};
256
257				ipu2_di0_lvds0: endpoint@3 {
258					reg = <3>;
259					remote-endpoint = <&lvds0_mux_2>;
260				};
261
262				ipu2_di0_lvds1: endpoint@4 {
263					reg = <4>;
264					remote-endpoint = <&lvds1_mux_2>;
265				};
266			};
267
268			ipu2_di1: port@3 {
269				#address-cells = <1>;
270				#size-cells = <0>;
271				reg = <3>;
272
273				ipu2_di1_hdmi: endpoint@1 {
274					reg = <1>;
275					remote-endpoint = <&hdmi_mux_3>;
276				};
277
278				ipu2_di1_mipi: endpoint@2 {
279					reg = <2>;
280					remote-endpoint = <&mipi_mux_3>;
281				};
282
283				ipu2_di1_lvds0: endpoint@3 {
284					reg = <3>;
285					remote-endpoint = <&lvds0_mux_3>;
286				};
287
288				ipu2_di1_lvds1: endpoint@4 {
289					reg = <4>;
290					remote-endpoint = <&lvds1_mux_3>;
291				};
292			};
293		};
294	};
295
296	capture-subsystem {
297		compatible = "fsl,imx-capture-subsystem";
298		ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
299	};
300
301	display-subsystem {
302		compatible = "fsl,imx-display-subsystem";
303		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
304	};
305};
306
307&gpio1 {
308	gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
309		      <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
310		      <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
311		      <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
312		      <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
313		      <&iomuxc 22 116 10>;
314};
315
316&gpio2 {
317	gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
318		      <&iomuxc 31  44  1>;
319};
320
321&gpio3 {
322	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
323};
324
325&gpio4 {
326	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
327};
328
329&gpio5 {
330	gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
331		      <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
332};
333
334&gpio6 {
335	gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
336		      <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
337		      <&iomuxc 31  86 1>;
338};
339
340&gpio7 {
341	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
342};
343
344&gpr {
345	ipu1_csi0_mux {
346		compatible = "video-mux";
347		mux-controls = <&mux 0>;
348		#address-cells = <1>;
349		#size-cells = <0>;
350
351		port@0 {
352			reg = <0>;
353
354			ipu1_csi0_mux_from_mipi_vc0: endpoint {
355				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
356			};
357		};
358
359		port@1 {
360			reg = <1>;
361
362			ipu1_csi0_mux_from_parallel_sensor: endpoint {
363			};
364		};
365
366		port@2 {
367			reg = <2>;
368
369			ipu1_csi0_mux_to_ipu1_csi0: endpoint {
370				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
371			};
372		};
373	};
374
375	ipu2_csi1_mux {
376		compatible = "video-mux";
377		mux-controls = <&mux 1>;
378		#address-cells = <1>;
379		#size-cells = <0>;
380
381		port@0 {
382			reg = <0>;
383
384			ipu2_csi1_mux_from_mipi_vc3: endpoint {
385				remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
386			};
387		};
388
389		port@1 {
390			reg = <1>;
391
392			ipu2_csi1_mux_from_parallel_sensor: endpoint {
393			};
394		};
395
396		port@2 {
397			reg = <2>;
398
399			ipu2_csi1_mux_to_ipu2_csi1: endpoint {
400				remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
401			};
402		};
403	};
404};
405
406&hdmi {
407	compatible = "fsl,imx6q-hdmi";
408
409	ports {
410		port@2 {
411			reg = <2>;
412
413			hdmi_mux_2: endpoint {
414				remote-endpoint = <&ipu2_di0_hdmi>;
415			};
416		};
417
418		port@3 {
419			reg = <3>;
420
421			hdmi_mux_3: endpoint {
422				remote-endpoint = <&ipu2_di1_hdmi>;
423			};
424		};
425	};
426};
427
428&iomuxc {
429	compatible = "fsl,imx6q-iomuxc";
430};
431
432&ipu1_csi1 {
433	ipu1_csi1_from_mipi_vc1: endpoint {
434		remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
435	};
436};
437
438&ldb {
439	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
440		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
441		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
442		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
443	clock-names = "di0_pll", "di1_pll",
444		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
445		      "di0", "di1";
446
447	lvds-channel@0 {
448		port@2 {
449			reg = <2>;
450
451			lvds0_mux_2: endpoint {
452				remote-endpoint = <&ipu2_di0_lvds0>;
453			};
454		};
455
456		port@3 {
457			reg = <3>;
458
459			lvds0_mux_3: endpoint {
460				remote-endpoint = <&ipu2_di1_lvds0>;
461			};
462		};
463	};
464
465	lvds-channel@1 {
466		port@2 {
467			reg = <2>;
468
469			lvds1_mux_2: endpoint {
470				remote-endpoint = <&ipu2_di0_lvds1>;
471			};
472		};
473
474		port@3 {
475			reg = <3>;
476
477			lvds1_mux_3: endpoint {
478				remote-endpoint = <&ipu2_di1_lvds1>;
479			};
480		};
481	};
482};
483
484&mipi_csi {
485	port@1 {
486		reg = <1>;
487
488		mipi_vc0_to_ipu1_csi0_mux: endpoint {
489			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
490		};
491	};
492
493	port@2 {
494		reg = <2>;
495
496		mipi_vc1_to_ipu1_csi1: endpoint {
497			remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
498		};
499	};
500
501	port@3 {
502		reg = <3>;
503
504		mipi_vc2_to_ipu2_csi0: endpoint {
505			remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
506		};
507	};
508
509	port@4 {
510		reg = <4>;
511
512		mipi_vc3_to_ipu2_csi1_mux: endpoint {
513			remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
514		};
515	};
516};
517
518&mipi_dsi {
519	ports {
520		port@2 {
521			reg = <2>;
522
523			mipi_mux_2: endpoint {
524				remote-endpoint = <&ipu2_di0_mipi>;
525			};
526		};
527
528		port@3 {
529			reg = <3>;
530
531			mipi_mux_3: endpoint {
532				remote-endpoint = <&ipu2_di1_mipi>;
533			};
534		};
535	};
536};
537
538&mux {
539	mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
540			<0x04 0x00100000>, /* MIPI_IPU2_MUX */
541			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
542			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
543			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
544			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
545			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
546};
547
548&vpu {
549	compatible = "fsl,imx6q-vpu", "cnm,coda960";
550};
551