1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_HW_H_ 5 #define _IGC_HW_H_ 6 7 #include <linux/types.h> 8 #include <linux/if_ether.h> 9 #include <linux/netdevice.h> 10 11 #include "igc_regs.h" 12 #include "igc_defines.h" 13 #include "igc_mac.h" 14 #include "igc_phy.h" 15 #include "igc_nvm.h" 16 #include "igc_i225.h" 17 #include "igc_base.h" 18 19 #define IGC_DEV_ID_I225_LM 0x15F2 20 #define IGC_DEV_ID_I225_V 0x15F3 21 #define IGC_DEV_ID_I225_I 0x15F8 22 #define IGC_DEV_ID_I220_V 0x15F7 23 #define IGC_DEV_ID_I225_K 0x3100 24 #define IGC_DEV_ID_I225_K2 0x3101 25 #define IGC_DEV_ID_I226_K 0x3102 26 #define IGC_DEV_ID_I225_LMVP 0x5502 27 #define IGC_DEV_ID_I226_LMVP 0x5503 28 #define IGC_DEV_ID_I225_IT 0x0D9F 29 #define IGC_DEV_ID_I226_LM 0x125B 30 #define IGC_DEV_ID_I226_V 0x125C 31 #define IGC_DEV_ID_I226_IT 0x125D 32 #define IGC_DEV_ID_I221_V 0x125E 33 #define IGC_DEV_ID_I226_BLANK_NVM 0x125F 34 #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD 35 36 /* Function pointers for the MAC. */ 37 struct igc_mac_operations { 38 s32 (*check_for_link)(struct igc_hw *hw); 39 s32 (*reset_hw)(struct igc_hw *hw); 40 s32 (*init_hw)(struct igc_hw *hw); 41 s32 (*setup_physical_interface)(struct igc_hw *hw); 42 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); 43 s32 (*read_mac_addr)(struct igc_hw *hw); 44 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, 45 u16 *duplex); 46 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); 47 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); 48 }; 49 50 enum igc_mac_type { 51 igc_undefined = 0, 52 igc_i225, 53 igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 54 }; 55 56 enum igc_media_type { 57 igc_media_type_unknown = 0, 58 igc_media_type_copper = 1, 59 igc_num_media_types 60 }; 61 62 enum igc_nvm_type { 63 igc_nvm_unknown = 0, 64 igc_nvm_eeprom_spi, 65 }; 66 67 struct igc_info { 68 s32 (*get_invariants)(struct igc_hw *hw); 69 struct igc_mac_operations *mac_ops; 70 const struct igc_phy_operations *phy_ops; 71 struct igc_nvm_operations *nvm_ops; 72 }; 73 74 extern const struct igc_info igc_base_info; 75 76 struct igc_mac_info { 77 struct igc_mac_operations ops; 78 79 u8 addr[ETH_ALEN]; 80 u8 perm_addr[ETH_ALEN]; 81 82 enum igc_mac_type type; 83 84 u32 mc_filter_type; 85 86 u16 mta_reg_count; 87 u16 uta_reg_count; 88 89 u32 mta_shadow[MAX_MTA_REG]; 90 u16 rar_entry_count; 91 92 u8 forced_speed_duplex; 93 94 bool asf_firmware_present; 95 bool arc_subsystem_valid; 96 97 bool autoneg; 98 bool autoneg_failed; 99 bool get_link_status; 100 }; 101 102 struct igc_nvm_operations { 103 s32 (*acquire)(struct igc_hw *hw); 104 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 105 void (*release)(struct igc_hw *hw); 106 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 107 s32 (*update)(struct igc_hw *hw); 108 s32 (*validate)(struct igc_hw *hw); 109 }; 110 111 struct igc_phy_operations { 112 s32 (*acquire)(struct igc_hw *hw); 113 s32 (*check_reset_block)(struct igc_hw *hw); 114 s32 (*force_speed_duplex)(struct igc_hw *hw); 115 s32 (*get_phy_info)(struct igc_hw *hw); 116 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); 117 void (*release)(struct igc_hw *hw); 118 s32 (*reset)(struct igc_hw *hw); 119 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); 120 }; 121 122 struct igc_nvm_info { 123 struct igc_nvm_operations ops; 124 enum igc_nvm_type type; 125 126 u16 word_size; 127 u16 delay_usec; 128 u16 address_bits; 129 u16 opcode_bits; 130 u16 page_size; 131 }; 132 133 struct igc_phy_info { 134 struct igc_phy_operations ops; 135 136 u32 addr; 137 u32 id; 138 u32 reset_delay_us; /* in usec */ 139 u32 revision; 140 141 enum igc_media_type media_type; 142 143 u16 autoneg_advertised; 144 u16 autoneg_mask; 145 146 u8 mdix; 147 148 bool is_mdix; 149 bool speed_downgraded; 150 bool autoneg_wait_to_complete; 151 }; 152 153 struct igc_bus_info { 154 u16 func; 155 u16 pci_cmd_word; 156 }; 157 158 enum igc_fc_mode { 159 igc_fc_none = 0, 160 igc_fc_rx_pause, 161 igc_fc_tx_pause, 162 igc_fc_full, 163 igc_fc_default = 0xFF 164 }; 165 166 struct igc_fc_info { 167 u32 high_water; /* Flow control high-water mark */ 168 u32 low_water; /* Flow control low-water mark */ 169 u16 pause_time; /* Flow control pause timer */ 170 bool send_xon; /* Flow control send XON */ 171 bool strict_ieee; /* Strict IEEE mode */ 172 enum igc_fc_mode current_mode; /* Type of flow control */ 173 enum igc_fc_mode requested_mode; 174 }; 175 176 struct igc_dev_spec_base { 177 bool clear_semaphore_once; 178 bool eee_enable; 179 }; 180 181 struct igc_hw { 182 void *back; 183 184 u8 __iomem *hw_addr; 185 unsigned long io_base; 186 187 struct igc_mac_info mac; 188 struct igc_fc_info fc; 189 struct igc_nvm_info nvm; 190 struct igc_phy_info phy; 191 192 struct igc_bus_info bus; 193 194 union { 195 struct igc_dev_spec_base _base; 196 } dev_spec; 197 198 u16 device_id; 199 u16 subsystem_vendor_id; 200 u16 subsystem_device_id; 201 u16 vendor_id; 202 203 u8 revision_id; 204 }; 205 206 /* Statistics counters collected by the MAC */ 207 struct igc_hw_stats { 208 u64 crcerrs; 209 u64 algnerrc; 210 u64 symerrs; 211 u64 rxerrc; 212 u64 mpc; 213 u64 scc; 214 u64 ecol; 215 u64 mcc; 216 u64 latecol; 217 u64 colc; 218 u64 dc; 219 u64 tncrs; 220 u64 sec; 221 u64 cexterr; 222 u64 rlec; 223 u64 xonrxc; 224 u64 xontxc; 225 u64 xoffrxc; 226 u64 xofftxc; 227 u64 fcruc; 228 u64 prc64; 229 u64 prc127; 230 u64 prc255; 231 u64 prc511; 232 u64 prc1023; 233 u64 prc1522; 234 u64 tlpic; 235 u64 rlpic; 236 u64 gprc; 237 u64 bprc; 238 u64 mprc; 239 u64 gptc; 240 u64 gorc; 241 u64 gotc; 242 u64 rnbc; 243 u64 ruc; 244 u64 rfc; 245 u64 roc; 246 u64 rjc; 247 u64 mgprc; 248 u64 mgpdc; 249 u64 mgptc; 250 u64 tor; 251 u64 tot; 252 u64 tpr; 253 u64 tpt; 254 u64 ptc64; 255 u64 ptc127; 256 u64 ptc255; 257 u64 ptc511; 258 u64 ptc1023; 259 u64 ptc1522; 260 u64 mptc; 261 u64 bptc; 262 u64 tsctc; 263 u64 tsctfc; 264 u64 iac; 265 u64 htdpmc; 266 u64 rpthc; 267 u64 hgptc; 268 u64 hgorc; 269 u64 hgotc; 270 u64 lenerrs; 271 u64 scvpc; 272 u64 hrmpc; 273 u64 doosync; 274 u64 o2bgptc; 275 u64 o2bspc; 276 u64 b2ospc; 277 u64 b2ogprc; 278 }; 279 280 struct net_device *igc_get_hw_dev(struct igc_hw *hw); 281 #define hw_dbg(format, arg...) \ 282 netdev_dbg(igc_get_hw_dev(hw), format, ##arg) 283 284 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 285 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 286 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 287 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 288 289 #endif /* _IGC_HW_H_ */ 290