1 /* 2 * ibmstb4.h 3 * 4 * This was dirived from the ibm405gp.h and other previus works in ppc4xx.h 5 * 6 * Current maintainer 7 * Armin Kuster akuster@mvista.com 8 * DEC, 2001 9 * 10 * 11 * Copyright 2001 MontaVista Softare Inc. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * You should have received a copy of the GNU General Public License along 30 * with this program; if not, write to the Free Software Foundation, Inc., 31 * 675 Mass Ave, Cambridge, MA 02139, USA. 32 * 33 * Version 1.0 (01/10/10) - A. Kuster 34 * Initial version 35 * 36 * Version 1.1 02/01/17 - A. Kuster 37 * moved common offsets to ibm405.h 38 * 39 * Version 1.2 02/22/02 - A. Kuster 40 * Added UIC and 41 * Added early serial boot #define support - David G. 42 * fixed __BOOTER__ 43 * 44 * Version 1.3 03/29/02 - Armin 45 * Added i2c & usb ocp support 46 * 47 * Version 1.4 04/30/02 - Armin 48 * Added IIC_PORT_DFNS macros 49 * Version 1.5 - 05/05/02 _ armin 50 * removed IIC_PORT now using core_ocp[] 51 * 52 * Version 1.6 07/22/02 - Armin 53 * added default power managment setting 54 * 55 * 56 */ 57 58 #ifdef __KERNEL__ 59 #ifndef __ASM_IBMSTB4_H__ 60 #define __ASM_IBMSTB4_H__ 61 62 #include <linux/config.h> 63 #include <platforms/ibm_ocp.h> 64 65 /* serial port defines */ 66 #define STB04xxx_IO_BASE ((uint)0xe0000000) 67 #define PPC4xx_PCI_IO_ADDR STB04xxx_IO_BASE 68 #define PPC4xx_ONB_IO_PADDR STB04xxx_IO_BASE 69 #define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000) 70 #define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024) 71 72 /* 73 * map STB04xxx internal i/o address (0x400x00xx) to an address 74 * which is below the 2GB limit... 75 * 76 * 4000 000x uart1 -> 0xe000 000x 77 * 4001 00xx ppu 78 * 4002 00xx smart card 79 * 4003 000x iic 80 * 4004 000x uart0 81 * 4005 0xxx timer 82 * 4006 00xx gpio 83 * 4007 00xx smart card 84 * 400b 000x iic 85 * 400c 000x scp 86 * 400d 000x modem 87 * 400e 000x uart2 88 */ 89 #define STB04xxx_MAP_IO_ADDR(a) (((uint)(a)) + (STB04xxx_IO_BASE - 0x40000000)) 90 91 #define RS_TABLE_SIZE 3 92 #define UART0_INT 20 93 94 #ifdef __BOOTER__ 95 #define UART0_IO_BASE 0x40040000 96 #else 97 #define UART0_IO_BASE 0xe0040000 98 #endif 99 100 #define UART1_INT 21 101 102 #ifdef __BOOTER__ 103 #define UART1_IO_BASE 0x40000000 104 #else 105 #define UART1_IO_BASE 0xe0000000 106 #endif 107 108 #define UART2_INT 31 109 #ifdef __BOOTER__ 110 #define UART2_IO_BASE 0x400e0000 111 #else 112 #define UART2_IO_BASE 0xe00e0000 113 #endif 114 115 #define IDE0_BASE 0x400F0000 116 #define IDE0_SIZE 0x200 117 #define IDE0_IRQ 25 118 #define IIC0_BASE 0x40030000 119 #define IIC1_BASE 0x400b0000 120 #define OPB0_BASE 0x40000000 121 #define GPIO0_BASE 0x40060000 122 123 #define USB0_IRQ 18 124 #define USB0_BASE STB04xxx_MAP_IO_ADDR(0x40010000) 125 #define USB0_EXTENT 4096 126 127 #define IIC_NUMS 2 128 #define UART_NUMS 3 129 #define IIC0_IRQ 9 130 #define IIC1_IRQ 10 131 #define IIC_OWN 0x55 132 #define IIC_CLOCK 50 133 134 #define BD_EMAC_ADDR(e,i) bi_enetaddr[i] 135 136 #define STD_UART_OP(num) \ 137 { 0, BASE_BAUD, 0, UART##num##_INT, \ 138 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 139 iomem_base: (u8 *)UART##num##_IO_BASE, \ 140 io_type: SERIAL_IO_MEM}, 141 142 #if defined(CONFIG_UART0_TTYS0) 143 #define SERIAL_DEBUG_IO_BASE UART0_IO_BASE 144 #define SERIAL_PORT_DFNS \ 145 STD_UART_OP(0) \ 146 STD_UART_OP(1) \ 147 STD_UART_OP(2) 148 #endif 149 150 #if defined(CONFIG_UART0_TTYS1) 151 #define SERIAL_DEBUG_IO_BASE UART2_IO_BASE 152 #define SERIAL_PORT_DFNS \ 153 STD_UART_OP(1) \ 154 STD_UART_OP(0) \ 155 STD_UART_OP(2) 156 #endif 157 158 #if defined(CONFIG_UART0_TTYS2) 159 #define SERIAL_DEBUG_IO_BASE UART2_IO_BASE 160 #define SERIAL_PORT_DFNS \ 161 STD_UART_OP(2) \ 162 STD_UART_OP(0) \ 163 STD_UART_OP(1) 164 #endif 165 166 #define DCRN_BE_BASE 0x090 167 #define DCRN_DMA0_BASE 0x0C0 168 #define DCRN_DMA1_BASE 0x0C8 169 #define DCRN_DMA2_BASE 0x0D0 170 #define DCRN_DMA3_BASE 0x0D8 171 #define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */ 172 #define DCRN_DMASR_BASE 0x0E0 173 #define DCRN_PLB0_BASE 0x054 174 #define DCRN_PLB1_BASE 0x064 175 #define DCRN_POB0_BASE 0x0B0 176 #define DCRN_SCCR_BASE 0x120 177 #define DCRN_UIC0_BASE 0x040 178 #define DCRN_BE_BASE 0x090 179 #define DCRN_DMA0_BASE 0x0C0 180 #define DCRN_DMA1_BASE 0x0C8 181 #define DCRN_DMA2_BASE 0x0D0 182 #define DCRN_DMA3_BASE 0x0D8 183 #define DCRN_CIC_BASE 0x030 184 #define DCRN_DMASR_BASE 0x0E0 185 #define DCRN_EBIMC_BASE 0x070 186 #define DCRN_DCRX_BASE 0x020 187 #define DCRN_CPMFR_BASE 0x102 188 #define DCRN_SCCR_BASE 0x120 189 #define UIC0 DCRN_UIC0_BASE 190 191 #define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */ 192 #define IBM_CPM_USB0 0x40000000 /* IEEE-1284 */ 193 #define IBM_CPM_IIC1 0x20000000 /* IIC 1 interface */ 194 #define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */ 195 #define IBM_CPM_AUD 0x08000000 /* Audio Decoder */ 196 #define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */ 197 #define IBM_CPM_SDRAM1 0x02000000 /* SDRAM 1 memory controller */ 198 #define IBM_CPM_DMA 0x01000000 /* DMA controller */ 199 #define IBM_CPM_DMA1 0x00800000 /* reserved */ 200 #define IBM_CPM_XPT1 0x00400000 /* reserved */ 201 #define IBM_CPM_XPT2 0x00200000 /* reserved */ 202 #define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */ 203 #define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */ 204 #define IBM_CPM_EPI 0x00040000 /* DCR Extension */ 205 #define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */ 206 #define IBM_CPM_VID 0x00010000 /* reserved */ 207 #define IBM_CPM_SC1 0x00008000 /* Smart Card 1 */ 208 #define IBM_CPM_USBSDRA 0x00004000 /* SDRAM 0 memory controller */ 209 #define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */ 210 #define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */ 211 #define IBM_CPM_GPT 0x00000800 /* GPTPWM */ 212 #define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */ 213 #define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */ 214 #define IBM_CPM_TMRCLK 0x00000100 /* CPU timers */ 215 #define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */ 216 #define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */ 217 #define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */ 218 #define IBM_CPM_UART2 0x00000008 /* Serial Control Port */ 219 #define IBM_CPM_DDIO 0x00000004 /* Descrambler */ 220 #define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */ 221 222 #define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \ 223 | IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \ 224 | IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \ 225 | IBM_CPM_XPT27 | IBM_CPM_UIC ) 226 227 #define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ 228 #define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */ 229 /* DCRN_BESR */ 230 #define BESR_DSES 0x80000000 /* Data-Side Error Status */ 231 #define BESR_DMES 0x40000000 /* DMA Error Status */ 232 #define BESR_RWS 0x20000000 /* Read/Write Status */ 233 #define BESR_ETMASK 0x1C000000 /* Error Type */ 234 #define ET_PROT 0 235 #define ET_PARITY 1 236 #define ET_NCFG 2 237 #define ET_BUSERR 4 238 #define ET_BUSTO 6 239 240 #define CHR1_CETE 0x00800000 /* CPU external timer enable */ 241 #define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ 242 243 #define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */ 244 #define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */ 245 #define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */ 246 #define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */ 247 #define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */ 248 #define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */ 249 #define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */ 250 #define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */ 251 #define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */ 252 253 #define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */ 254 #define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */ 255 #define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */ 256 #define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */ 257 #define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */ 258 #define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */ 259 #define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */ 260 #define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */ 261 262 #define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */ 263 #define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */ 264 #define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */ 265 #define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */ 266 #define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */ 267 #define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */ 268 #define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */ 269 #define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */ 270 #define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */ 271 #define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */ 272 #define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */ 273 #define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */ 274 #define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */ 275 #define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */ 276 #define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */ 277 #define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */ 278 #define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */ 279 #define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */ 280 #define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */ 281 282 #include <platforms/ibm405.h> 283 284 #endif /* __ASM_IBMSTB4_H__ */ 285 #endif /* __KERNEL__ */ 286