1 #ifndef __intr_vect_defs_asm_h 2 #define __intr_vect_defs_asm_h 3 4 /* 5 * This file is autogenerated from 6 * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r 7 * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp 8 * last modfied: Mon Apr 11 16:08:03 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/intr_vect_defs_asm.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r 11 * id: $Id: intr_vect_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 17 #ifndef REG_FIELD 18 #define REG_FIELD( scope, reg, field, value ) \ 19 REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) 20 #define REG_FIELD_X_( value, shift ) ((value) << shift) 21 #endif 22 23 #ifndef REG_STATE 24 #define REG_STATE( scope, reg, field, symbolic_value ) \ 25 REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) 26 #define REG_STATE_X_( k, shift ) (k << shift) 27 #endif 28 29 #ifndef REG_MASK 30 #define REG_MASK( scope, reg, field ) \ 31 REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) 32 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) 33 #endif 34 35 #ifndef REG_LSB 36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb 37 #endif 38 39 #ifndef REG_BIT 40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit 41 #endif 42 43 #ifndef REG_ADDR 44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) 45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs) 46 #endif 47 48 #ifndef REG_ADDR_VECT 49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 50 REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ 51 STRIDE_##scope##_##reg ) 52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ 53 ((inst) + offs + (index) * stride) 54 #endif 55 56 /* Register rw_mask, scope intr_vect, type rw */ 57 #define reg_intr_vect_rw_mask___memarb___lsb 0 58 #define reg_intr_vect_rw_mask___memarb___width 1 59 #define reg_intr_vect_rw_mask___memarb___bit 0 60 #define reg_intr_vect_rw_mask___gen_io___lsb 1 61 #define reg_intr_vect_rw_mask___gen_io___width 1 62 #define reg_intr_vect_rw_mask___gen_io___bit 1 63 #define reg_intr_vect_rw_mask___iop0___lsb 2 64 #define reg_intr_vect_rw_mask___iop0___width 1 65 #define reg_intr_vect_rw_mask___iop0___bit 2 66 #define reg_intr_vect_rw_mask___iop1___lsb 3 67 #define reg_intr_vect_rw_mask___iop1___width 1 68 #define reg_intr_vect_rw_mask___iop1___bit 3 69 #define reg_intr_vect_rw_mask___iop2___lsb 4 70 #define reg_intr_vect_rw_mask___iop2___width 1 71 #define reg_intr_vect_rw_mask___iop2___bit 4 72 #define reg_intr_vect_rw_mask___iop3___lsb 5 73 #define reg_intr_vect_rw_mask___iop3___width 1 74 #define reg_intr_vect_rw_mask___iop3___bit 5 75 #define reg_intr_vect_rw_mask___dma0___lsb 6 76 #define reg_intr_vect_rw_mask___dma0___width 1 77 #define reg_intr_vect_rw_mask___dma0___bit 6 78 #define reg_intr_vect_rw_mask___dma1___lsb 7 79 #define reg_intr_vect_rw_mask___dma1___width 1 80 #define reg_intr_vect_rw_mask___dma1___bit 7 81 #define reg_intr_vect_rw_mask___dma2___lsb 8 82 #define reg_intr_vect_rw_mask___dma2___width 1 83 #define reg_intr_vect_rw_mask___dma2___bit 8 84 #define reg_intr_vect_rw_mask___dma3___lsb 9 85 #define reg_intr_vect_rw_mask___dma3___width 1 86 #define reg_intr_vect_rw_mask___dma3___bit 9 87 #define reg_intr_vect_rw_mask___dma4___lsb 10 88 #define reg_intr_vect_rw_mask___dma4___width 1 89 #define reg_intr_vect_rw_mask___dma4___bit 10 90 #define reg_intr_vect_rw_mask___dma5___lsb 11 91 #define reg_intr_vect_rw_mask___dma5___width 1 92 #define reg_intr_vect_rw_mask___dma5___bit 11 93 #define reg_intr_vect_rw_mask___dma6___lsb 12 94 #define reg_intr_vect_rw_mask___dma6___width 1 95 #define reg_intr_vect_rw_mask___dma6___bit 12 96 #define reg_intr_vect_rw_mask___dma7___lsb 13 97 #define reg_intr_vect_rw_mask___dma7___width 1 98 #define reg_intr_vect_rw_mask___dma7___bit 13 99 #define reg_intr_vect_rw_mask___dma8___lsb 14 100 #define reg_intr_vect_rw_mask___dma8___width 1 101 #define reg_intr_vect_rw_mask___dma8___bit 14 102 #define reg_intr_vect_rw_mask___dma9___lsb 15 103 #define reg_intr_vect_rw_mask___dma9___width 1 104 #define reg_intr_vect_rw_mask___dma9___bit 15 105 #define reg_intr_vect_rw_mask___ata___lsb 16 106 #define reg_intr_vect_rw_mask___ata___width 1 107 #define reg_intr_vect_rw_mask___ata___bit 16 108 #define reg_intr_vect_rw_mask___sser0___lsb 17 109 #define reg_intr_vect_rw_mask___sser0___width 1 110 #define reg_intr_vect_rw_mask___sser0___bit 17 111 #define reg_intr_vect_rw_mask___sser1___lsb 18 112 #define reg_intr_vect_rw_mask___sser1___width 1 113 #define reg_intr_vect_rw_mask___sser1___bit 18 114 #define reg_intr_vect_rw_mask___ser0___lsb 19 115 #define reg_intr_vect_rw_mask___ser0___width 1 116 #define reg_intr_vect_rw_mask___ser0___bit 19 117 #define reg_intr_vect_rw_mask___ser1___lsb 20 118 #define reg_intr_vect_rw_mask___ser1___width 1 119 #define reg_intr_vect_rw_mask___ser1___bit 20 120 #define reg_intr_vect_rw_mask___ser2___lsb 21 121 #define reg_intr_vect_rw_mask___ser2___width 1 122 #define reg_intr_vect_rw_mask___ser2___bit 21 123 #define reg_intr_vect_rw_mask___ser3___lsb 22 124 #define reg_intr_vect_rw_mask___ser3___width 1 125 #define reg_intr_vect_rw_mask___ser3___bit 22 126 #define reg_intr_vect_rw_mask___p21___lsb 23 127 #define reg_intr_vect_rw_mask___p21___width 1 128 #define reg_intr_vect_rw_mask___p21___bit 23 129 #define reg_intr_vect_rw_mask___eth0___lsb 24 130 #define reg_intr_vect_rw_mask___eth0___width 1 131 #define reg_intr_vect_rw_mask___eth0___bit 24 132 #define reg_intr_vect_rw_mask___eth1___lsb 25 133 #define reg_intr_vect_rw_mask___eth1___width 1 134 #define reg_intr_vect_rw_mask___eth1___bit 25 135 #define reg_intr_vect_rw_mask___timer___lsb 26 136 #define reg_intr_vect_rw_mask___timer___width 1 137 #define reg_intr_vect_rw_mask___timer___bit 26 138 #define reg_intr_vect_rw_mask___bif_arb___lsb 27 139 #define reg_intr_vect_rw_mask___bif_arb___width 1 140 #define reg_intr_vect_rw_mask___bif_arb___bit 27 141 #define reg_intr_vect_rw_mask___bif_dma___lsb 28 142 #define reg_intr_vect_rw_mask___bif_dma___width 1 143 #define reg_intr_vect_rw_mask___bif_dma___bit 28 144 #define reg_intr_vect_rw_mask___ext___lsb 29 145 #define reg_intr_vect_rw_mask___ext___width 1 146 #define reg_intr_vect_rw_mask___ext___bit 29 147 #define reg_intr_vect_rw_mask_offset 0 148 149 /* Register r_vect, scope intr_vect, type r */ 150 #define reg_intr_vect_r_vect___memarb___lsb 0 151 #define reg_intr_vect_r_vect___memarb___width 1 152 #define reg_intr_vect_r_vect___memarb___bit 0 153 #define reg_intr_vect_r_vect___gen_io___lsb 1 154 #define reg_intr_vect_r_vect___gen_io___width 1 155 #define reg_intr_vect_r_vect___gen_io___bit 1 156 #define reg_intr_vect_r_vect___iop0___lsb 2 157 #define reg_intr_vect_r_vect___iop0___width 1 158 #define reg_intr_vect_r_vect___iop0___bit 2 159 #define reg_intr_vect_r_vect___iop1___lsb 3 160 #define reg_intr_vect_r_vect___iop1___width 1 161 #define reg_intr_vect_r_vect___iop1___bit 3 162 #define reg_intr_vect_r_vect___iop2___lsb 4 163 #define reg_intr_vect_r_vect___iop2___width 1 164 #define reg_intr_vect_r_vect___iop2___bit 4 165 #define reg_intr_vect_r_vect___iop3___lsb 5 166 #define reg_intr_vect_r_vect___iop3___width 1 167 #define reg_intr_vect_r_vect___iop3___bit 5 168 #define reg_intr_vect_r_vect___dma0___lsb 6 169 #define reg_intr_vect_r_vect___dma0___width 1 170 #define reg_intr_vect_r_vect___dma0___bit 6 171 #define reg_intr_vect_r_vect___dma1___lsb 7 172 #define reg_intr_vect_r_vect___dma1___width 1 173 #define reg_intr_vect_r_vect___dma1___bit 7 174 #define reg_intr_vect_r_vect___dma2___lsb 8 175 #define reg_intr_vect_r_vect___dma2___width 1 176 #define reg_intr_vect_r_vect___dma2___bit 8 177 #define reg_intr_vect_r_vect___dma3___lsb 9 178 #define reg_intr_vect_r_vect___dma3___width 1 179 #define reg_intr_vect_r_vect___dma3___bit 9 180 #define reg_intr_vect_r_vect___dma4___lsb 10 181 #define reg_intr_vect_r_vect___dma4___width 1 182 #define reg_intr_vect_r_vect___dma4___bit 10 183 #define reg_intr_vect_r_vect___dma5___lsb 11 184 #define reg_intr_vect_r_vect___dma5___width 1 185 #define reg_intr_vect_r_vect___dma5___bit 11 186 #define reg_intr_vect_r_vect___dma6___lsb 12 187 #define reg_intr_vect_r_vect___dma6___width 1 188 #define reg_intr_vect_r_vect___dma6___bit 12 189 #define reg_intr_vect_r_vect___dma7___lsb 13 190 #define reg_intr_vect_r_vect___dma7___width 1 191 #define reg_intr_vect_r_vect___dma7___bit 13 192 #define reg_intr_vect_r_vect___dma8___lsb 14 193 #define reg_intr_vect_r_vect___dma8___width 1 194 #define reg_intr_vect_r_vect___dma8___bit 14 195 #define reg_intr_vect_r_vect___dma9___lsb 15 196 #define reg_intr_vect_r_vect___dma9___width 1 197 #define reg_intr_vect_r_vect___dma9___bit 15 198 #define reg_intr_vect_r_vect___ata___lsb 16 199 #define reg_intr_vect_r_vect___ata___width 1 200 #define reg_intr_vect_r_vect___ata___bit 16 201 #define reg_intr_vect_r_vect___sser0___lsb 17 202 #define reg_intr_vect_r_vect___sser0___width 1 203 #define reg_intr_vect_r_vect___sser0___bit 17 204 #define reg_intr_vect_r_vect___sser1___lsb 18 205 #define reg_intr_vect_r_vect___sser1___width 1 206 #define reg_intr_vect_r_vect___sser1___bit 18 207 #define reg_intr_vect_r_vect___ser0___lsb 19 208 #define reg_intr_vect_r_vect___ser0___width 1 209 #define reg_intr_vect_r_vect___ser0___bit 19 210 #define reg_intr_vect_r_vect___ser1___lsb 20 211 #define reg_intr_vect_r_vect___ser1___width 1 212 #define reg_intr_vect_r_vect___ser1___bit 20 213 #define reg_intr_vect_r_vect___ser2___lsb 21 214 #define reg_intr_vect_r_vect___ser2___width 1 215 #define reg_intr_vect_r_vect___ser2___bit 21 216 #define reg_intr_vect_r_vect___ser3___lsb 22 217 #define reg_intr_vect_r_vect___ser3___width 1 218 #define reg_intr_vect_r_vect___ser3___bit 22 219 #define reg_intr_vect_r_vect___p21___lsb 23 220 #define reg_intr_vect_r_vect___p21___width 1 221 #define reg_intr_vect_r_vect___p21___bit 23 222 #define reg_intr_vect_r_vect___eth0___lsb 24 223 #define reg_intr_vect_r_vect___eth0___width 1 224 #define reg_intr_vect_r_vect___eth0___bit 24 225 #define reg_intr_vect_r_vect___eth1___lsb 25 226 #define reg_intr_vect_r_vect___eth1___width 1 227 #define reg_intr_vect_r_vect___eth1___bit 25 228 #define reg_intr_vect_r_vect___timer___lsb 26 229 #define reg_intr_vect_r_vect___timer___width 1 230 #define reg_intr_vect_r_vect___timer___bit 26 231 #define reg_intr_vect_r_vect___bif_arb___lsb 27 232 #define reg_intr_vect_r_vect___bif_arb___width 1 233 #define reg_intr_vect_r_vect___bif_arb___bit 27 234 #define reg_intr_vect_r_vect___bif_dma___lsb 28 235 #define reg_intr_vect_r_vect___bif_dma___width 1 236 #define reg_intr_vect_r_vect___bif_dma___bit 28 237 #define reg_intr_vect_r_vect___ext___lsb 29 238 #define reg_intr_vect_r_vect___ext___width 1 239 #define reg_intr_vect_r_vect___ext___bit 29 240 #define reg_intr_vect_r_vect_offset 4 241 242 /* Register r_masked_vect, scope intr_vect, type r */ 243 #define reg_intr_vect_r_masked_vect___memarb___lsb 0 244 #define reg_intr_vect_r_masked_vect___memarb___width 1 245 #define reg_intr_vect_r_masked_vect___memarb___bit 0 246 #define reg_intr_vect_r_masked_vect___gen_io___lsb 1 247 #define reg_intr_vect_r_masked_vect___gen_io___width 1 248 #define reg_intr_vect_r_masked_vect___gen_io___bit 1 249 #define reg_intr_vect_r_masked_vect___iop0___lsb 2 250 #define reg_intr_vect_r_masked_vect___iop0___width 1 251 #define reg_intr_vect_r_masked_vect___iop0___bit 2 252 #define reg_intr_vect_r_masked_vect___iop1___lsb 3 253 #define reg_intr_vect_r_masked_vect___iop1___width 1 254 #define reg_intr_vect_r_masked_vect___iop1___bit 3 255 #define reg_intr_vect_r_masked_vect___iop2___lsb 4 256 #define reg_intr_vect_r_masked_vect___iop2___width 1 257 #define reg_intr_vect_r_masked_vect___iop2___bit 4 258 #define reg_intr_vect_r_masked_vect___iop3___lsb 5 259 #define reg_intr_vect_r_masked_vect___iop3___width 1 260 #define reg_intr_vect_r_masked_vect___iop3___bit 5 261 #define reg_intr_vect_r_masked_vect___dma0___lsb 6 262 #define reg_intr_vect_r_masked_vect___dma0___width 1 263 #define reg_intr_vect_r_masked_vect___dma0___bit 6 264 #define reg_intr_vect_r_masked_vect___dma1___lsb 7 265 #define reg_intr_vect_r_masked_vect___dma1___width 1 266 #define reg_intr_vect_r_masked_vect___dma1___bit 7 267 #define reg_intr_vect_r_masked_vect___dma2___lsb 8 268 #define reg_intr_vect_r_masked_vect___dma2___width 1 269 #define reg_intr_vect_r_masked_vect___dma2___bit 8 270 #define reg_intr_vect_r_masked_vect___dma3___lsb 9 271 #define reg_intr_vect_r_masked_vect___dma3___width 1 272 #define reg_intr_vect_r_masked_vect___dma3___bit 9 273 #define reg_intr_vect_r_masked_vect___dma4___lsb 10 274 #define reg_intr_vect_r_masked_vect___dma4___width 1 275 #define reg_intr_vect_r_masked_vect___dma4___bit 10 276 #define reg_intr_vect_r_masked_vect___dma5___lsb 11 277 #define reg_intr_vect_r_masked_vect___dma5___width 1 278 #define reg_intr_vect_r_masked_vect___dma5___bit 11 279 #define reg_intr_vect_r_masked_vect___dma6___lsb 12 280 #define reg_intr_vect_r_masked_vect___dma6___width 1 281 #define reg_intr_vect_r_masked_vect___dma6___bit 12 282 #define reg_intr_vect_r_masked_vect___dma7___lsb 13 283 #define reg_intr_vect_r_masked_vect___dma7___width 1 284 #define reg_intr_vect_r_masked_vect___dma7___bit 13 285 #define reg_intr_vect_r_masked_vect___dma8___lsb 14 286 #define reg_intr_vect_r_masked_vect___dma8___width 1 287 #define reg_intr_vect_r_masked_vect___dma8___bit 14 288 #define reg_intr_vect_r_masked_vect___dma9___lsb 15 289 #define reg_intr_vect_r_masked_vect___dma9___width 1 290 #define reg_intr_vect_r_masked_vect___dma9___bit 15 291 #define reg_intr_vect_r_masked_vect___ata___lsb 16 292 #define reg_intr_vect_r_masked_vect___ata___width 1 293 #define reg_intr_vect_r_masked_vect___ata___bit 16 294 #define reg_intr_vect_r_masked_vect___sser0___lsb 17 295 #define reg_intr_vect_r_masked_vect___sser0___width 1 296 #define reg_intr_vect_r_masked_vect___sser0___bit 17 297 #define reg_intr_vect_r_masked_vect___sser1___lsb 18 298 #define reg_intr_vect_r_masked_vect___sser1___width 1 299 #define reg_intr_vect_r_masked_vect___sser1___bit 18 300 #define reg_intr_vect_r_masked_vect___ser0___lsb 19 301 #define reg_intr_vect_r_masked_vect___ser0___width 1 302 #define reg_intr_vect_r_masked_vect___ser0___bit 19 303 #define reg_intr_vect_r_masked_vect___ser1___lsb 20 304 #define reg_intr_vect_r_masked_vect___ser1___width 1 305 #define reg_intr_vect_r_masked_vect___ser1___bit 20 306 #define reg_intr_vect_r_masked_vect___ser2___lsb 21 307 #define reg_intr_vect_r_masked_vect___ser2___width 1 308 #define reg_intr_vect_r_masked_vect___ser2___bit 21 309 #define reg_intr_vect_r_masked_vect___ser3___lsb 22 310 #define reg_intr_vect_r_masked_vect___ser3___width 1 311 #define reg_intr_vect_r_masked_vect___ser3___bit 22 312 #define reg_intr_vect_r_masked_vect___p21___lsb 23 313 #define reg_intr_vect_r_masked_vect___p21___width 1 314 #define reg_intr_vect_r_masked_vect___p21___bit 23 315 #define reg_intr_vect_r_masked_vect___eth0___lsb 24 316 #define reg_intr_vect_r_masked_vect___eth0___width 1 317 #define reg_intr_vect_r_masked_vect___eth0___bit 24 318 #define reg_intr_vect_r_masked_vect___eth1___lsb 25 319 #define reg_intr_vect_r_masked_vect___eth1___width 1 320 #define reg_intr_vect_r_masked_vect___eth1___bit 25 321 #define reg_intr_vect_r_masked_vect___timer___lsb 26 322 #define reg_intr_vect_r_masked_vect___timer___width 1 323 #define reg_intr_vect_r_masked_vect___timer___bit 26 324 #define reg_intr_vect_r_masked_vect___bif_arb___lsb 27 325 #define reg_intr_vect_r_masked_vect___bif_arb___width 1 326 #define reg_intr_vect_r_masked_vect___bif_arb___bit 27 327 #define reg_intr_vect_r_masked_vect___bif_dma___lsb 28 328 #define reg_intr_vect_r_masked_vect___bif_dma___width 1 329 #define reg_intr_vect_r_masked_vect___bif_dma___bit 28 330 #define reg_intr_vect_r_masked_vect___ext___lsb 29 331 #define reg_intr_vect_r_masked_vect___ext___width 1 332 #define reg_intr_vect_r_masked_vect___ext___bit 29 333 #define reg_intr_vect_r_masked_vect_offset 8 334 335 /* Register r_nmi, scope intr_vect, type r */ 336 #define reg_intr_vect_r_nmi___ext___lsb 0 337 #define reg_intr_vect_r_nmi___ext___width 1 338 #define reg_intr_vect_r_nmi___ext___bit 0 339 #define reg_intr_vect_r_nmi___watchdog___lsb 1 340 #define reg_intr_vect_r_nmi___watchdog___width 1 341 #define reg_intr_vect_r_nmi___watchdog___bit 1 342 #define reg_intr_vect_r_nmi_offset 12 343 344 /* Register r_guru, scope intr_vect, type r */ 345 #define reg_intr_vect_r_guru___jtag___lsb 0 346 #define reg_intr_vect_r_guru___jtag___width 1 347 #define reg_intr_vect_r_guru___jtag___bit 0 348 #define reg_intr_vect_r_guru_offset 16 349 350 351 /* Constants */ 352 #define regk_intr_vect_off 0x00000000 353 #define regk_intr_vect_on 0x00000001 354 #define regk_intr_vect_rw_mask_default 0x00000000 355 #endif /* __intr_vect_defs_asm_h */ 356