1 /* $Id: hfc_sx.c,v 1.1.4.1 2001/11/20 14:19:35 kai Exp $
2 *
3 * level driver for CCD�s hfc-s+/sp based cards
4 *
5 * Author Werner Cornelius
6 * based on existing driver for CCD HFC PCI cards
7 * Copyright by Werner Cornelius <werner@isdn4linux.de>
8 *
9 * This software may be used and distributed according to the terms
10 * of the GNU General Public License, incorporated herein by reference.
11 *
12 */
13
14 #define __NO_VERSION__
15 #include <linux/init.h>
16 #include "hisax.h"
17 #include "hfc_sx.h"
18 #include "isdnl1.h"
19 #include <linux/interrupt.h>
20 #include <linux/isapnp.h>
21
22 extern const char *CardType[];
23
24 static const char *hfcsx_revision = "$Revision: 1.1.4.1 $";
25
26 /***************************************/
27 /* IRQ-table for CCDs demo board */
28 /* IRQs 6,5,10,11,12,15 are supported */
29 /***************************************/
30
31 /* Teles 16.3c Vendor Id TAG2620, Version 1.0, Vendor version 2.1
32 *
33 * Thanks to Uwe Wisniewski
34 *
35 * ISA-SLOT Signal PIN
36 * B25 IRQ3 92 IRQ_G
37 * B23 IRQ5 94 IRQ_A
38 * B4 IRQ2/9 95 IRQ_B
39 * D3 IRQ10 96 IRQ_C
40 * D4 IRQ11 97 IRQ_D
41 * D5 IRQ12 98 IRQ_E
42 * D6 IRQ15 99 IRQ_F
43 */
44
45 #undef CCD_DEMO_BOARD
46 #ifdef CCD_DEMO_BOARD
47 static u_char ccd_sp_irqtab[16] = {
48 0,0,0,0,0,2,1,0,0,0,3,4,5,0,0,6
49 };
50 #else /* Teles 16.3c */
51 static u_char ccd_sp_irqtab[16] = {
52 0,0,0,7,0,1,0,0,0,2,3,4,5,0,0,6
53 };
54 #endif
55 #define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */
56
57 #define byteout(addr,val) outb(val,addr)
58 #define bytein(addr) inb(addr)
59
60 /******************************/
61 /* In/Out access to registers */
62 /******************************/
63 static inline void
Write_hfc(struct IsdnCardState * cs,u_char regnum,u_char val)64 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val)
65 { unsigned long flags;
66
67 save_flags(flags);
68 cli();
69 byteout(cs->hw.hfcsx.base+1, regnum);
70 byteout(cs->hw.hfcsx.base, val);
71 restore_flags(flags);
72 }
73
74 static inline u_char
Read_hfc(struct IsdnCardState * cs,u_char regnum)75 Read_hfc(struct IsdnCardState *cs, u_char regnum)
76 { unsigned long flags;
77 u_char ret;
78
79 save_flags(flags);
80 cli();
81 byteout(cs->hw.hfcsx.base+1, regnum);
82 ret = bytein(cs->hw.hfcsx.base);
83 restore_flags(flags);
84 return(ret);
85 }
86
87
88 /**************************************************/
89 /* select a fifo and remember which one for reuse */
90 /**************************************************/
91 static void
fifo_select(struct IsdnCardState * cs,u_char fifo)92 fifo_select(struct IsdnCardState *cs, u_char fifo)
93 { unsigned long flags;
94
95 if (fifo == cs->hw.hfcsx.last_fifo)
96 return; /* still valid */
97
98 save_flags(flags);
99 cli();
100 byteout(cs->hw.hfcsx.base+1, HFCSX_FIF_SEL);
101 byteout(cs->hw.hfcsx.base, fifo);
102 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
103 udelay(4);
104 byteout(cs->hw.hfcsx.base, fifo);
105 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
106 restore_flags(flags);
107 }
108
109 /******************************************/
110 /* reset the specified fifo to defaults. */
111 /* If its a send fifo init needed markers */
112 /******************************************/
113 static void
reset_fifo(struct IsdnCardState * cs,u_char fifo)114 reset_fifo(struct IsdnCardState *cs, u_char fifo)
115 { unsigned long flags;
116
117 save_flags(flags);
118 cli();
119 fifo_select(cs, fifo); /* first select the fifo */
120 byteout(cs->hw.hfcsx.base+1, HFCSX_CIRM);
121 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */
122 udelay(1);
123 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
124 restore_flags(flags);
125 }
126
127
128 /*************************************************************/
129 /* write_fifo writes the skb contents to the desired fifo */
130 /* if no space is available or an error occurs 0 is returned */
131 /* the skb is not released in any way. */
132 /*************************************************************/
133 static int
write_fifo(struct IsdnCardState * cs,struct sk_buff * skb,u_char fifo,int trans_max)134 write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max)
135 { unsigned short *msp;
136 int fifo_size, count, z1, z2;
137 u_char f_msk, f1, f2, *src;
138
139 if (skb->len <= 0) return(0);
140 if (fifo & 1) return(0); /* no write fifo */
141
142 fifo_select(cs, fifo);
143 if (fifo & 4) {
144 fifo_size = D_FIFO_SIZE; /* D-channel */
145 f_msk = MAX_D_FRAMES;
146 if (trans_max) return(0); /* only HDLC */
147 }
148 else {
149 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
150 f_msk = MAX_B_FRAMES;
151 }
152
153 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
154 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
155
156 /* Check for transparent mode */
157 if (trans_max) {
158 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
159 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
160 count = z2 - z1;
161 if (count <= 0)
162 count += fifo_size; /* free bytes */
163 if (count < skb->len+1) return(0); /* no room */
164 count = fifo_size - count; /* bytes still not send */
165 if (count > 2 * trans_max) return(0); /* delay to long */
166 count = skb->len;
167 src = skb->data;
168 while (count--)
169 Write_hfc(cs, HFCSX_FIF_DWR, *src++);
170 return(1); /* success */
171 }
172
173 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker;
174 msp += (((fifo >> 1) & 3) * (MAX_B_FRAMES+1));
175 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
176 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
177
178 count = f1 - f2; /* frame count actually buffered */
179 if (count < 0)
180 count += (f_msk + 1); /* if wrap around */
181 if (count > f_msk-1) {
182 if (cs->debug & L1_DEB_ISAC_FIFO)
183 debugl1(cs, "hfcsx_write_fifo %d more as %d frames",fifo,f_msk-1);
184 return(0);
185 }
186
187 *(msp + f1) = z1; /* remember marker */
188
189 if (cs->debug & L1_DEB_ISAC_FIFO)
190 debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)",
191 fifo, f1, f2, z1);
192 /* now determine free bytes in FIFO buffer */
193 count = *(msp + f2) - z1;
194 if (count <= 0)
195 count += fifo_size; /* count now contains available bytes */
196
197 if (cs->debug & L1_DEB_ISAC_FIFO)
198 debugl1(cs, "hfcsx_write_fifo %d count(%ld/%d)",
199 fifo, skb->len, count);
200 if (count < skb->len) {
201 if (cs->debug & L1_DEB_ISAC_FIFO)
202 debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo);
203 return(0);
204 }
205
206 count = skb->len; /* get frame len */
207 src = skb->data; /* source pointer */
208 while (count--)
209 Write_hfc(cs, HFCSX_FIF_DWR, *src++);
210
211 Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */
212 udelay(1);
213 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
214 return(1);
215 }
216
217 /***************************************************************/
218 /* read_fifo reads data to an skb from the desired fifo */
219 /* if no data is available or an error occurs NULL is returned */
220 /* the skb is not released in any way. */
221 /***************************************************************/
222 static struct sk_buff *
read_fifo(struct IsdnCardState * cs,u_char fifo,int trans_max)223 read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max)
224 { int fifo_size, count, z1, z2;
225 u_char f_msk, f1, f2, *dst;
226 struct sk_buff *skb;
227
228 if (!(fifo & 1)) return(NULL); /* no read fifo */
229 fifo_select(cs, fifo);
230 if (fifo & 4) {
231 fifo_size = D_FIFO_SIZE; /* D-channel */
232 f_msk = MAX_D_FRAMES;
233 if (trans_max) return(NULL); /* only hdlc */
234 }
235 else {
236 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
237 f_msk = MAX_B_FRAMES;
238 }
239
240 /* transparent mode */
241 if (trans_max) {
242 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
243 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
244 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
245 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
246 /* now determine bytes in actual FIFO buffer */
247 count = z1 - z2;
248 if (count <= 0)
249 count += fifo_size; /* count now contains buffered bytes */
250 count++;
251 if (count > trans_max)
252 count = trans_max; /* limit length */
253 if ((skb = dev_alloc_skb(count))) {
254 dst = skb_put(skb, count);
255 while (count--)
256 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
257 return(skb);
258 }
259 else return(NULL); /* no memory */
260 }
261
262 do {
263 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
264 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
265
266 if (f1 == f2) return(NULL); /* no frame available */
267
268 z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
269 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
270 z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
271 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
272
273 if (cs->debug & L1_DEB_ISAC_FIFO)
274 debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)",
275 fifo, f1, f2, z1, z2);
276 /* now determine bytes in actual FIFO buffer */
277 count = z1 - z2;
278 if (count <= 0)
279 count += fifo_size; /* count now contains buffered bytes */
280 count++;
281
282 if (cs->debug & L1_DEB_ISAC_FIFO)
283 debugl1(cs, "hfcsx_read_fifo %d count %ld)",
284 fifo, count);
285
286 if ((count > fifo_size) || (count < 4)) {
287 if (cs->debug & L1_DEB_WARN)
288 debugl1(cs, "hfcsx_read_fifo %d paket inv. len %d ", fifo , count);
289 while (count) {
290 count--; /* empty fifo */
291 Read_hfc(cs, HFCSX_FIF_DRD);
292 }
293 skb = NULL;
294 } else
295 if ((skb = dev_alloc_skb(count - 3))) {
296 count -= 3;
297 dst = skb_put(skb, count);
298
299 while (count--)
300 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
301
302 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */
303 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */
304 if (Read_hfc(cs, HFCSX_FIF_DRD)) {
305 dev_kfree_skb_irq(skb);
306 if (cs->debug & L1_DEB_ISAC_FIFO)
307 debugl1(cs, "hfcsx_read_fifo %d crc error", fifo);
308 skb = NULL;
309 }
310 } else {
311 printk(KERN_WARNING "HFC-SX: receive out of memory\n");
312 return(NULL);
313 }
314
315 Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */
316 udelay(1);
317 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
318 udelay(1);
319 } while (!skb); /* retry in case of crc error */
320 return(skb);
321 }
322
323 /******************************************/
324 /* free hardware resources used by driver */
325 /******************************************/
326 void
release_io_hfcsx(struct IsdnCardState * cs)327 release_io_hfcsx(struct IsdnCardState *cs)
328 {
329 unsigned long flags;
330
331 save_flags(flags);
332 cli();
333 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */
334 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
335 restore_flags(flags);
336 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */
337 sti();
338 set_current_state(TASK_UNINTERRUPTIBLE);
339 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
340 Write_hfc(cs, HFCSX_CIRM, 0); /* Reset Off */
341 del_timer(&cs->hw.hfcsx.timer);
342 release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */
343 kfree(cs->hw.hfcsx.extra);
344 cs->hw.hfcsx.extra = NULL;
345 }
346
347 /**********************************************************/
348 /* set_fifo_size determines the size of the RAM and FIFOs */
349 /* returning 0 -> need to reset the chip again. */
350 /**********************************************************/
set_fifo_size(struct IsdnCardState * cs)351 static int set_fifo_size(struct IsdnCardState *cs)
352 {
353
354 if (cs->hw.hfcsx.b_fifo_size) return(1); /* already determined */
355
356 if ((cs->hw.hfcsx.chip >> 4) == 9) {
357 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K;
358 return(1);
359 }
360
361 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K;
362 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */
363 return(0);
364
365 }
366
367 /********************************************************************************/
368 /* function called to reset the HFC SX chip. A complete software reset of chip */
369 /* and fifos is done. */
370 /********************************************************************************/
371 static void
reset_hfcsx(struct IsdnCardState * cs)372 reset_hfcsx(struct IsdnCardState *cs)
373 {
374 long flags;
375
376 save_flags(flags);
377 cli();
378 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */
379 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
380
381 printk(KERN_INFO "HFC_SX: resetting card\n");
382 while (1) {
383 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm ); /* Reset */
384 sti();
385 set_current_state(TASK_UNINTERRUPTIBLE);
386 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
387 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */
388 set_current_state(TASK_UNINTERRUPTIBLE);
389 schedule_timeout((20 * HZ) / 1000); /* Timeout 20ms */
390 if (Read_hfc(cs, HFCSX_STATUS) & 2)
391 printk(KERN_WARNING "HFC-SX init bit busy\n");
392 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */
393 if (!set_fifo_size(cs)) continue;
394 break;
395 }
396
397 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */
398 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
399
400 Write_hfc(cs, HFCSX_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */
401 cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE;
402 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */
403 cs->hw.hfcsx.bswapped = 0; /* no exchange */
404 cs->hw.hfcsx.nt_mode = 0; /* we are in TE mode */
405 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER;
406 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
407
408 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC |
409 HFCSX_INTS_L1STATE | HFCSX_INTS_TIMER;
410 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
411
412 /* Clear already pending ints */
413 if (Read_hfc(cs, HFCSX_INT_S1));
414
415 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2); /* HFC ST 2 */
416 udelay(10);
417 Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */
418 cs->hw.hfcsx.mst_m = HFCSX_MASTER; /* HFC Master Mode */
419
420 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
421 cs->hw.hfcsx.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
422 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
423 cs->hw.hfcsx.sctrl_r = 0;
424 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
425
426 /* Init GCI/IOM2 in master mode */
427 /* Slots 0 and 1 are set for B-chan 1 and 2 */
428 /* D- and monitor/CI channel are not enabled */
429 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
430 /* STIO2 is used as data input, B1+B2 from IOM->ST */
431 /* ST B-channel send disabled -> continous 1s */
432 /* The IOM slots are always enabled */
433 cs->hw.hfcsx.conn = 0x36; /* set data flow directions */
434 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
435 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */
436 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */
437 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */
438 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */
439
440 /* Finally enable IRQ output */
441 cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE;
442 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
443 if (Read_hfc(cs, HFCSX_INT_S2));
444 restore_flags(flags);
445 }
446
447 /***************************************************/
448 /* Timer function called when kernel timer expires */
449 /***************************************************/
450 static void
hfcsx_Timer(struct IsdnCardState * cs)451 hfcsx_Timer(struct IsdnCardState *cs)
452 {
453 cs->hw.hfcsx.timer.expires = jiffies + 75;
454 /* WD RESET */
455 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80);
456 add_timer(&cs->hw.hfcsx.timer);
457 */
458 }
459
460
461 /*********************************/
462 /* schedule a new D-channel task */
463 /*********************************/
464 static void
sched_event_D_sx(struct IsdnCardState * cs,int event)465 sched_event_D_sx(struct IsdnCardState *cs, int event)
466 {
467 test_and_set_bit(event, &cs->event);
468 queue_task(&cs->tqueue, &tq_immediate);
469 mark_bh(IMMEDIATE_BH);
470 }
471
472 /*********************************/
473 /* schedule a new b_channel task */
474 /*********************************/
475 static void
hfcsx_sched_event(struct BCState * bcs,int event)476 hfcsx_sched_event(struct BCState *bcs, int event)
477 {
478 bcs->event |= 1 << event;
479 queue_task(&bcs->tqueue, &tq_immediate);
480 mark_bh(IMMEDIATE_BH);
481 }
482
483 /************************************************/
484 /* select a b-channel entry matching and active */
485 /************************************************/
486 static
487 struct BCState *
Sel_BCS(struct IsdnCardState * cs,int channel)488 Sel_BCS(struct IsdnCardState *cs, int channel)
489 {
490 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
491 return (&cs->bcs[0]);
492 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
493 return (&cs->bcs[1]);
494 else
495 return (NULL);
496 }
497
498 /*******************************/
499 /* D-channel receive procedure */
500 /*******************************/
501 static
502 int
receive_dmsg(struct IsdnCardState * cs)503 receive_dmsg(struct IsdnCardState *cs)
504 {
505 struct sk_buff *skb;
506 int count = 5;
507
508 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
509 debugl1(cs, "rec_dmsg blocked");
510 return (1);
511 }
512
513 do {
514 skb = read_fifo(cs, HFCSX_SEL_D_RX, 0);
515 if (skb) {
516 skb_queue_tail(&cs->rq, skb);
517 sched_event_D_sx(cs, D_RCVBUFREADY);
518 }
519 } while (--count && skb);
520
521 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
522 return (1);
523 }
524
525 /**********************************/
526 /* B-channel main receive routine */
527 /**********************************/
528 void
main_rec_hfcsx(struct BCState * bcs)529 main_rec_hfcsx(struct BCState *bcs)
530 {
531 long flags;
532 struct IsdnCardState *cs = bcs->cs;
533 int count = 5;
534 struct sk_buff *skb;
535
536 save_flags(flags);
537
538 Begin:
539 count--;
540 cli();
541 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
542 debugl1(cs, "rec_data %d blocked", bcs->channel);
543 restore_flags(flags);
544 return;
545 }
546 sti();
547 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
548 HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX,
549 (bcs->mode == L1_MODE_TRANS) ?
550 HFCSX_BTRANS_THRESHOLD : 0);
551
552 if (skb) {
553 cli();
554 skb_queue_tail(&bcs->rqueue, skb);
555 sti();
556 hfcsx_sched_event(bcs, B_RCVBUFREADY);
557 }
558
559 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
560 if (count && skb)
561 goto Begin;
562 restore_flags(flags);
563 return;
564 }
565
566 /**************************/
567 /* D-channel send routine */
568 /**************************/
569 static void
hfcsx_fill_dfifo(struct IsdnCardState * cs)570 hfcsx_fill_dfifo(struct IsdnCardState *cs)
571 {
572 if (!cs->tx_skb)
573 return;
574 if (cs->tx_skb->len <= 0)
575 return;
576
577 if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) {
578 dev_kfree_skb_any(cs->tx_skb);
579 cs->tx_skb = NULL;
580 }
581 return;
582 }
583
584 /**************************/
585 /* B-channel send routine */
586 /**************************/
587 static void
hfcsx_fill_fifo(struct BCState * bcs)588 hfcsx_fill_fifo(struct BCState *bcs)
589 {
590 struct IsdnCardState *cs = bcs->cs;
591 unsigned long flags;
592
593 if (!bcs->tx_skb)
594 return;
595 if (bcs->tx_skb->len <= 0)
596 return;
597
598 save_flags(flags);
599 sti();
600
601 if (write_fifo(cs, bcs->tx_skb,
602 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
603 HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX,
604 (bcs->mode == L1_MODE_TRANS) ?
605 HFCSX_BTRANS_THRESHOLD : 0)) {
606
607 bcs->tx_cnt -= bcs->tx_skb->len;
608 if (bcs->st->lli.l1writewakeup &&
609 (PACKET_NOACK != bcs->tx_skb->pkt_type))
610 bcs->st->lli.l1writewakeup(bcs->st, bcs->tx_skb->len);
611 dev_kfree_skb_any(bcs->tx_skb);
612 bcs->tx_skb = NULL;
613 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
614 }
615
616 cli();
617 restore_flags(flags);
618 return;
619 }
620
621 /**********************************************/
622 /* D-channel l1 state call for leased NT-mode */
623 /**********************************************/
624 static void
dch_nt_l2l1(struct PStack * st,int pr,void * arg)625 dch_nt_l2l1(struct PStack *st, int pr, void *arg)
626 {
627 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
628
629 switch (pr) {
630 case (PH_DATA | REQUEST):
631 case (PH_PULL | REQUEST):
632 case (PH_PULL | INDICATION):
633 st->l1.l1hw(st, pr, arg);
634 break;
635 case (PH_ACTIVATE | REQUEST):
636 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
637 break;
638 case (PH_TESTLOOP | REQUEST):
639 if (1 & (long) arg)
640 debugl1(cs, "PH_TEST_LOOP B1");
641 if (2 & (long) arg)
642 debugl1(cs, "PH_TEST_LOOP B2");
643 if (!(3 & (long) arg))
644 debugl1(cs, "PH_TEST_LOOP DISABLED");
645 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
646 break;
647 default:
648 if (cs->debug)
649 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
650 break;
651 }
652 }
653
654
655
656 /***********************/
657 /* set/reset echo mode */
658 /***********************/
659 static int
hfcsx_auxcmd(struct IsdnCardState * cs,isdn_ctrl * ic)660 hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
661 {
662 unsigned long flags;
663 int i = *(unsigned int *) ic->parm.num;
664
665 if ((ic->arg == 98) &&
666 (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) {
667 save_flags(flags);
668 cli();
669 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */
670 udelay(10);
671 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT;
672 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */
673 udelay(10);
674 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1); /* HFC ST G1 */
675 udelay(10);
676 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION);
677 cs->dc.hfcsx.ph_state = 1;
678 cs->hw.hfcsx.nt_mode = 1;
679 cs->hw.hfcsx.nt_timer = 0;
680 cs->stlist->l2.l2l1 = dch_nt_l2l1;
681 restore_flags(flags);
682 debugl1(cs, "NT mode activated");
683 return (0);
684 }
685 if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) ||
686 (cs->hw.hfcsx.nt_mode) || (ic->arg != 12))
687 return (-EINVAL);
688
689 save_flags(flags);
690 cli();
691 if (i) {
692 cs->logecho = 1;
693 cs->hw.hfcsx.trm |= 0x20; /* enable echo chan */
694 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC;
695 /* reset Channel !!!!! */
696 } else {
697 cs->logecho = 0;
698 cs->hw.hfcsx.trm &= ~0x20; /* disable echo chan */
699 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC;
700 }
701 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
702 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
703 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */
704 cs->hw.hfcsx.ctmt &= ~2;
705 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
706 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
707 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
708 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
709 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
710 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
711 restore_flags(flags);
712 return (0);
713 } /* hfcsx_auxcmd */
714
715 /*****************************/
716 /* E-channel receive routine */
717 /*****************************/
718 static void
receive_emsg(struct IsdnCardState * cs)719 receive_emsg(struct IsdnCardState *cs)
720 {
721 unsigned long flags;
722 int count = 5;
723 u_char *ptr;
724 struct sk_buff *skb;
725
726
727 save_flags(flags);
728 cli();
729 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
730 debugl1(cs, "echo_rec_data blocked");
731 restore_flags(flags);
732 return;
733 }
734 sti();
735
736 do {
737 skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0);
738 if (skb) {
739 if (cs->debug & DEB_DLOG_HEX) {
740 ptr = cs->dlog;
741 if ((skb->len) < MAX_DLOG_SPACE / 3 - 10) {
742 *ptr++ = 'E';
743 *ptr++ = 'C';
744 *ptr++ = 'H';
745 *ptr++ = 'O';
746 *ptr++ = ':';
747 ptr += QuickHex(ptr, skb->data, skb->len);
748 ptr--;
749 *ptr++ = '\n';
750 *ptr = 0;
751 HiSax_putstatus(cs, NULL, cs->dlog);
752 } else
753 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len);
754 }
755 dev_kfree_skb_any(skb);
756 }
757 } while (--count && skb);
758
759 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
760 restore_flags(flags);
761 return;
762 } /* receive_emsg */
763
764
765 /*********************/
766 /* Interrupt handler */
767 /*********************/
768 static void
hfcsx_interrupt(int intno,void * dev_id,struct pt_regs * regs)769 hfcsx_interrupt(int intno, void *dev_id, struct pt_regs *regs)
770 {
771 struct IsdnCardState *cs = dev_id;
772 u_char exval;
773 struct BCState *bcs;
774 int count = 15;
775 long flags;
776 u_char val, stat;
777
778 if (!cs) {
779 printk(KERN_WARNING "HFC-SX: Spurious interrupt!\n");
780 return;
781 }
782 if (!(cs->hw.hfcsx.int_m2 & 0x08))
783 return; /* not initialised */
784
785 if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) {
786 val = Read_hfc(cs, HFCSX_INT_S1);
787 if (cs->debug & L1_DEB_ISAC)
788 debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val);
789 } else
790 return;
791
792 if (cs->debug & L1_DEB_ISAC)
793 debugl1(cs, "HFC-SX irq %x %s", val,
794 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
795 "locked" : "unlocked");
796 val &= cs->hw.hfcsx.int_m1;
797 if (val & 0x40) { /* state machine irq */
798 exval = Read_hfc(cs, HFCSX_STATES) & 0xf;
799 if (cs->debug & L1_DEB_ISAC)
800 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state,
801 exval);
802 cs->dc.hfcsx.ph_state = exval;
803 sched_event_D_sx(cs, D_L1STATECHANGE);
804 val &= ~0x40;
805 }
806 if (val & 0x80) { /* timer irq */
807 if (cs->hw.hfcsx.nt_mode) {
808 if ((--cs->hw.hfcsx.nt_timer) < 0)
809 sched_event_D_sx(cs, D_L1STATECHANGE);
810 }
811 val &= ~0x80;
812 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
813 }
814 while (val) {
815 save_flags(flags);
816 cli();
817 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
818 cs->hw.hfcsx.int_s1 |= val;
819 restore_flags(flags);
820 return;
821 }
822 if (cs->hw.hfcsx.int_s1 & 0x18) {
823 exval = val;
824 val = cs->hw.hfcsx.int_s1;
825 cs->hw.hfcsx.int_s1 = exval;
826 }
827 if (val & 0x08) {
828 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
829 if (cs->debug)
830 debugl1(cs, "hfcsx spurious 0x08 IRQ");
831 } else
832 main_rec_hfcsx(bcs);
833 }
834 if (val & 0x10) {
835 if (cs->logecho)
836 receive_emsg(cs);
837 else if (!(bcs = Sel_BCS(cs, 1))) {
838 if (cs->debug)
839 debugl1(cs, "hfcsx spurious 0x10 IRQ");
840 } else
841 main_rec_hfcsx(bcs);
842 }
843 if (val & 0x01) {
844 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
845 if (cs->debug)
846 debugl1(cs, "hfcsx spurious 0x01 IRQ");
847 } else {
848 if (bcs->tx_skb) {
849 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
850 hfcsx_fill_fifo(bcs);
851 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
852 } else
853 debugl1(cs, "fill_data %d blocked", bcs->channel);
854 } else {
855 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
856 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
857 hfcsx_fill_fifo(bcs);
858 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
859 } else
860 debugl1(cs, "fill_data %d blocked", bcs->channel);
861 } else {
862 hfcsx_sched_event(bcs, B_XMTBUFREADY);
863 }
864 }
865 }
866 }
867 if (val & 0x02) {
868 if (!(bcs = Sel_BCS(cs, 1))) {
869 if (cs->debug)
870 debugl1(cs, "hfcsx spurious 0x02 IRQ");
871 } else {
872 if (bcs->tx_skb) {
873 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
874 hfcsx_fill_fifo(bcs);
875 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
876 } else
877 debugl1(cs, "fill_data %d blocked", bcs->channel);
878 } else {
879 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
880 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
881 hfcsx_fill_fifo(bcs);
882 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
883 } else
884 debugl1(cs, "fill_data %d blocked", bcs->channel);
885 } else {
886 hfcsx_sched_event(bcs, B_XMTBUFREADY);
887 }
888 }
889 }
890 }
891 if (val & 0x20) { /* receive dframe */
892 receive_dmsg(cs);
893 }
894 if (val & 0x04) { /* dframe transmitted */
895 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
896 del_timer(&cs->dbusytimer);
897 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
898 sched_event_D_sx(cs, D_CLEARBUSY);
899 if (cs->tx_skb) {
900 if (cs->tx_skb->len) {
901 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
902 hfcsx_fill_dfifo(cs);
903 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
904 } else {
905 debugl1(cs, "hfcsx_fill_dfifo irq blocked");
906 }
907 goto afterXPR;
908 } else {
909 dev_kfree_skb_irq(cs->tx_skb);
910 cs->tx_cnt = 0;
911 cs->tx_skb = NULL;
912 }
913 }
914 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
915 cs->tx_cnt = 0;
916 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
917 hfcsx_fill_dfifo(cs);
918 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
919 } else {
920 debugl1(cs, "hfcsx_fill_dfifo irq blocked");
921 }
922 } else
923 sched_event_D_sx(cs, D_XMTBUFREADY);
924 }
925 afterXPR:
926 if (cs->hw.hfcsx.int_s1 && count--) {
927 val = cs->hw.hfcsx.int_s1;
928 cs->hw.hfcsx.int_s1 = 0;
929 if (cs->debug & L1_DEB_ISAC)
930 debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count);
931 } else
932 val = 0;
933 restore_flags(flags);
934 }
935 }
936
937 /********************************************************************/
938 /* timer callback for D-chan busy resolution. Currently no function */
939 /********************************************************************/
940 static void
hfcsx_dbusy_timer(struct IsdnCardState * cs)941 hfcsx_dbusy_timer(struct IsdnCardState *cs)
942 {
943 }
944
945 /*************************************/
946 /* Layer 1 D-channel hardware access */
947 /*************************************/
948 static void
HFCSX_l1hw(struct PStack * st,int pr,void * arg)949 HFCSX_l1hw(struct PStack *st, int pr, void *arg)
950 {
951 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
952 struct sk_buff *skb = arg;
953 unsigned long flags;
954
955 switch (pr) {
956 case (PH_DATA | REQUEST):
957 if (cs->debug & DEB_DLOG_HEX)
958 LogFrame(cs, skb->data, skb->len);
959 if (cs->debug & DEB_DLOG_VERBOSE)
960 dlogframe(cs, skb, 0);
961 if (cs->tx_skb) {
962 skb_queue_tail(&cs->sq, skb);
963 #ifdef L2FRAME_DEBUG /* psa */
964 if (cs->debug & L1_DEB_LAPD)
965 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
966 #endif
967 } else {
968 cs->tx_skb = skb;
969 cs->tx_cnt = 0;
970 #ifdef L2FRAME_DEBUG /* psa */
971 if (cs->debug & L1_DEB_LAPD)
972 Logl2Frame(cs, skb, "PH_DATA", 0);
973 #endif
974 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
975 hfcsx_fill_dfifo(cs);
976 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
977 } else
978 debugl1(cs, "hfcsx_fill_dfifo blocked");
979
980 }
981 break;
982 case (PH_PULL | INDICATION):
983 if (cs->tx_skb) {
984 if (cs->debug & L1_DEB_WARN)
985 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
986 skb_queue_tail(&cs->sq, skb);
987 break;
988 }
989 if (cs->debug & DEB_DLOG_HEX)
990 LogFrame(cs, skb->data, skb->len);
991 if (cs->debug & DEB_DLOG_VERBOSE)
992 dlogframe(cs, skb, 0);
993 cs->tx_skb = skb;
994 cs->tx_cnt = 0;
995 #ifdef L2FRAME_DEBUG /* psa */
996 if (cs->debug & L1_DEB_LAPD)
997 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
998 #endif
999 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1000 hfcsx_fill_dfifo(cs);
1001 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1002 } else
1003 debugl1(cs, "hfcsx_fill_dfifo blocked");
1004 break;
1005 case (PH_PULL | REQUEST):
1006 #ifdef L2FRAME_DEBUG /* psa */
1007 if (cs->debug & L1_DEB_LAPD)
1008 debugl1(cs, "-> PH_REQUEST_PULL");
1009 #endif
1010 if (!cs->tx_skb) {
1011 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1012 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1013 } else
1014 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1015 break;
1016 case (HW_RESET | REQUEST):
1017 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */
1018 udelay(6);
1019 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */
1020 cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
1021 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1022 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
1023 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
1024 break;
1025 case (HW_ENABLE | REQUEST):
1026 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
1027 break;
1028 case (HW_DEACTIVATE | REQUEST):
1029 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER;
1030 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1031 break;
1032 case (HW_INFO3 | REQUEST):
1033 cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
1034 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1035 break;
1036 case (HW_TESTLOOP | REQUEST):
1037 switch ((int) arg) {
1038 case (1):
1039 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */
1040 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */
1041 save_flags(flags);
1042 cli();
1043 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1;
1044 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1045 restore_flags(flags);
1046 break;
1047
1048 case (2):
1049 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */
1050 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */
1051 save_flags(flags);
1052 cli();
1053 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08;
1054 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1055 restore_flags(flags);
1056 break;
1057
1058 default:
1059 if (cs->debug & L1_DEB_WARN)
1060 debugl1(cs, "hfcsx_l1hw loop invalid %4x", (int) arg);
1061 return;
1062 }
1063 save_flags(flags);
1064 cli();
1065 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */
1066 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
1067 restore_flags(flags);
1068 break;
1069 default:
1070 if (cs->debug & L1_DEB_WARN)
1071 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr);
1072 break;
1073 }
1074 }
1075
1076 /***********************************************/
1077 /* called during init setting l1 stack pointer */
1078 /***********************************************/
1079 void
setstack_hfcsx(struct PStack * st,struct IsdnCardState * cs)1080 setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs)
1081 {
1082 st->l1.l1hw = HFCSX_l1hw;
1083 }
1084
1085 /**************************************/
1086 /* send B-channel data if not blocked */
1087 /**************************************/
1088 static void
hfcsx_send_data(struct BCState * bcs)1089 hfcsx_send_data(struct BCState *bcs)
1090 {
1091 struct IsdnCardState *cs = bcs->cs;
1092
1093 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1094 hfcsx_fill_fifo(bcs);
1095 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1096 } else
1097 debugl1(cs, "send_data %d blocked", bcs->channel);
1098 }
1099
1100 /***************************************************************/
1101 /* activate/deactivate hardware for selected channels and mode */
1102 /***************************************************************/
1103 void
mode_hfcsx(struct BCState * bcs,int mode,int bc)1104 mode_hfcsx(struct BCState *bcs, int mode, int bc)
1105 {
1106 struct IsdnCardState *cs = bcs->cs;
1107 unsigned long flags;
1108 int fifo2;
1109
1110 if (cs->debug & L1_DEB_HSCX)
1111 debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d",
1112 mode, bc, bcs->channel);
1113 bcs->mode = mode;
1114 bcs->channel = bc;
1115 fifo2 = bc;
1116 save_flags(flags);
1117 cli();
1118 if (cs->chanlimit > 1) {
1119 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */
1120 cs->hw.hfcsx.sctrl_e &= ~0x80;
1121 } else {
1122 if (bc) {
1123 if (mode != L1_MODE_NULL) {
1124 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */
1125 cs->hw.hfcsx.sctrl_e |= 0x80;
1126 } else {
1127 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */
1128 cs->hw.hfcsx.sctrl_e &= ~0x80;
1129 }
1130 fifo2 = 0;
1131 } else {
1132 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */
1133 cs->hw.hfcsx.sctrl_e &= ~0x80;
1134 }
1135 }
1136 switch (mode) {
1137 case (L1_MODE_NULL):
1138 if (bc) {
1139 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
1140 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
1141 } else {
1142 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA;
1143 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA;
1144 }
1145 if (fifo2) {
1146 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1147 } else {
1148 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1149 }
1150 break;
1151 case (L1_MODE_TRANS):
1152 if (bc) {
1153 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1154 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1155 } else {
1156 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1157 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1158 }
1159 if (fifo2) {
1160 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1161 cs->hw.hfcsx.ctmt |= 2;
1162 cs->hw.hfcsx.conn &= ~0x18;
1163 } else {
1164 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1165 cs->hw.hfcsx.ctmt |= 1;
1166 cs->hw.hfcsx.conn &= ~0x03;
1167 }
1168 break;
1169 case (L1_MODE_HDLC):
1170 if (bc) {
1171 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1172 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1173 } else {
1174 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1175 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1176 }
1177 if (fifo2) {
1178 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1179 cs->hw.hfcsx.ctmt &= ~2;
1180 cs->hw.hfcsx.conn &= ~0x18;
1181 } else {
1182 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1183 cs->hw.hfcsx.ctmt &= ~1;
1184 cs->hw.hfcsx.conn &= ~0x03;
1185 }
1186 break;
1187 case (L1_MODE_EXTRN):
1188 if (bc) {
1189 cs->hw.hfcsx.conn |= 0x10;
1190 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1191 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1192 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1193 } else {
1194 cs->hw.hfcsx.conn |= 0x02;
1195 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1196 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1197 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1198 }
1199 break;
1200 }
1201 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);
1202 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1203 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
1204 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
1205 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
1206 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1207 if (mode != L1_MODE_EXTRN) {
1208 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX);
1209 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX);
1210 }
1211 restore_flags(flags);
1212 }
1213
1214 /******************************/
1215 /* Layer2 -> Layer 1 Transfer */
1216 /******************************/
1217 static void
hfcsx_l2l1(struct PStack * st,int pr,void * arg)1218 hfcsx_l2l1(struct PStack *st, int pr, void *arg)
1219 {
1220 struct sk_buff *skb = arg;
1221 long flags;
1222
1223 switch (pr) {
1224 case (PH_DATA | REQUEST):
1225 save_flags(flags);
1226 cli();
1227 if (st->l1.bcs->tx_skb) {
1228 skb_queue_tail(&st->l1.bcs->squeue, skb);
1229 restore_flags(flags);
1230 } else {
1231 st->l1.bcs->tx_skb = skb;
1232 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1233 */ st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1234 restore_flags(flags);
1235 }
1236 break;
1237 case (PH_PULL | INDICATION):
1238 if (st->l1.bcs->tx_skb) {
1239 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1240 break;
1241 }
1242 save_flags(flags);
1243 cli();
1244 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1245 */ st->l1.bcs->tx_skb = skb;
1246 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1247 restore_flags(flags);
1248 break;
1249 case (PH_PULL | REQUEST):
1250 if (!st->l1.bcs->tx_skb) {
1251 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1252 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1253 } else
1254 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1255 break;
1256 case (PH_ACTIVATE | REQUEST):
1257 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1258 mode_hfcsx(st->l1.bcs, st->l1.mode, st->l1.bc);
1259 l1_msg_b(st, pr, arg);
1260 break;
1261 case (PH_DEACTIVATE | REQUEST):
1262 l1_msg_b(st, pr, arg);
1263 break;
1264 case (PH_DEACTIVATE | CONFIRM):
1265 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1266 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1267 mode_hfcsx(st->l1.bcs, 0, st->l1.bc);
1268 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1269 break;
1270 }
1271 }
1272
1273 /******************************************/
1274 /* deactivate B-channel access and queues */
1275 /******************************************/
1276 static void
close_hfcsx(struct BCState * bcs)1277 close_hfcsx(struct BCState *bcs)
1278 {
1279 mode_hfcsx(bcs, 0, bcs->channel);
1280 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1281 skb_queue_purge(&bcs->rqueue);
1282 skb_queue_purge(&bcs->squeue);
1283 if (bcs->tx_skb) {
1284 dev_kfree_skb_any(bcs->tx_skb);
1285 bcs->tx_skb = NULL;
1286 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1287 }
1288 }
1289 }
1290
1291 /*************************************/
1292 /* init B-channel queues and control */
1293 /*************************************/
1294 static int
open_hfcsxstate(struct IsdnCardState * cs,struct BCState * bcs)1295 open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs)
1296 {
1297 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1298 skb_queue_head_init(&bcs->rqueue);
1299 skb_queue_head_init(&bcs->squeue);
1300 }
1301 bcs->tx_skb = NULL;
1302 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1303 bcs->event = 0;
1304 bcs->tx_cnt = 0;
1305 return (0);
1306 }
1307
1308 /*********************************/
1309 /* inits the stack for B-channel */
1310 /*********************************/
1311 static int
setstack_2b(struct PStack * st,struct BCState * bcs)1312 setstack_2b(struct PStack *st, struct BCState *bcs)
1313 {
1314 bcs->channel = st->l1.bc;
1315 if (open_hfcsxstate(st->l1.hardware, bcs))
1316 return (-1);
1317 st->l1.bcs = bcs;
1318 st->l2.l2l1 = hfcsx_l2l1;
1319 setstack_manager(st);
1320 bcs->st = st;
1321 setstack_l1_B(st);
1322 return (0);
1323 }
1324
1325 /***************************/
1326 /* handle L1 state changes */
1327 /***************************/
1328 static void
hfcsx_bh(struct IsdnCardState * cs)1329 hfcsx_bh(struct IsdnCardState *cs)
1330 {
1331 unsigned long flags;
1332 /* struct PStack *stptr;
1333 */
1334 if (!cs)
1335 return;
1336 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1337 if (!cs->hw.hfcsx.nt_mode)
1338 switch (cs->dc.hfcsx.ph_state) {
1339 case (0):
1340 l1_msg(cs, HW_RESET | INDICATION, NULL);
1341 break;
1342 case (3):
1343 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1344 break;
1345 case (8):
1346 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1347 break;
1348 case (6):
1349 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1350 break;
1351 case (7):
1352 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1353 break;
1354 default:
1355 break;
1356 } else {
1357 switch (cs->dc.hfcsx.ph_state) {
1358 case (2):
1359 save_flags(flags);
1360 cli();
1361 if (cs->hw.hfcsx.nt_timer < 0) {
1362 cs->hw.hfcsx.nt_timer = 0;
1363 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1364 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1365 /* Clear already pending ints */
1366 if (Read_hfc(cs, HFCSX_INT_S1));
1367
1368 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE);
1369 udelay(10);
1370 Write_hfc(cs, HFCSX_STATES, 4);
1371 cs->dc.hfcsx.ph_state = 4;
1372 } else {
1373 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER;
1374 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1375 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER;
1376 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125;
1377 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1378 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1379 cs->hw.hfcsx.nt_timer = NT_T1_COUNT;
1380 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */
1381 }
1382 restore_flags(flags);
1383 break;
1384 case (1):
1385 case (3):
1386 case (4):
1387 save_flags(flags);
1388 cli();
1389 cs->hw.hfcsx.nt_timer = 0;
1390 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1391 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1392 restore_flags(flags);
1393 break;
1394 default:
1395 break;
1396 }
1397 }
1398 }
1399 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1400 DChannel_proc_rcv(cs);
1401 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1402 DChannel_proc_xmt(cs);
1403 }
1404
1405
1406 /********************************/
1407 /* called for card init message */
1408 /********************************/
1409 void __devinit
inithfcsx(struct IsdnCardState * cs)1410 inithfcsx(struct IsdnCardState *cs)
1411 {
1412 cs->setstack_d = setstack_hfcsx;
1413 cs->dbusytimer.function = (void *) hfcsx_dbusy_timer;
1414 cs->dbusytimer.data = (long) cs;
1415 init_timer(&cs->dbusytimer);
1416 cs->tqueue.routine = (void *) (void *) hfcsx_bh;
1417 cs->BC_Send_Data = &hfcsx_send_data;
1418 cs->bcs[0].BC_SetStack = setstack_2b;
1419 cs->bcs[1].BC_SetStack = setstack_2b;
1420 cs->bcs[0].BC_Close = close_hfcsx;
1421 cs->bcs[1].BC_Close = close_hfcsx;
1422 mode_hfcsx(cs->bcs, 0, 0);
1423 mode_hfcsx(cs->bcs + 1, 0, 1);
1424 }
1425
1426
1427
1428 /*******************************************/
1429 /* handle card messages from control layer */
1430 /*******************************************/
1431 static int
hfcsx_card_msg(struct IsdnCardState * cs,int mt,void * arg)1432 hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1433 {
1434 long flags;
1435
1436 if (cs->debug & L1_DEB_ISAC)
1437 debugl1(cs, "HFCSX: card_msg %x", mt);
1438 switch (mt) {
1439 case CARD_RESET:
1440 reset_hfcsx(cs);
1441 return (0);
1442 case CARD_RELEASE:
1443 release_io_hfcsx(cs);
1444 return (0);
1445 case CARD_INIT:
1446 inithfcsx(cs);
1447 save_flags(flags);
1448 sti();
1449 set_current_state(TASK_UNINTERRUPTIBLE);
1450 schedule_timeout((80 * HZ) / 1000); /* Timeout 80ms */
1451 /* now switch timer interrupt off */
1452 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1453 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1454 /* reinit mode reg */
1455 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1456 restore_flags(flags);
1457 return (0);
1458 case CARD_TEST:
1459 return (0);
1460 }
1461 return (0);
1462 }
1463
1464 #ifdef __ISAPNP__
1465 static struct isapnp_device_id hfc_ids[] __initdata = {
1466 { ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1467 ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1468 (unsigned long) "Teles 16.3c2" },
1469 { 0, }
1470 };
1471
1472 static struct isapnp_device_id *hdev = &hfc_ids[0];
1473 static struct pci_bus *pnp_c __devinitdata = NULL;
1474 #endif
1475
1476 int __devinit
setup_hfcsx(struct IsdnCard * card)1477 setup_hfcsx(struct IsdnCard *card)
1478 {
1479 struct IsdnCardState *cs = card->cs;
1480 char tmp[64];
1481 unsigned long flags;
1482
1483 strcpy(tmp, hfcsx_revision);
1484 printk(KERN_INFO "HiSax: HFC-SX driver Rev. %s\n", HiSax_getrev(tmp));
1485 #ifdef __ISAPNP__
1486 if (!card->para[1] && isapnp_present()) {
1487 struct pci_bus *pb;
1488 struct pci_dev *pd;
1489
1490 while(hdev->card_vendor) {
1491 if ((pb = isapnp_find_card(hdev->card_vendor,
1492 hdev->card_device, pnp_c))) {
1493 pnp_c = pb;
1494 pd = NULL;
1495 if ((pd = isapnp_find_dev(pnp_c,
1496 hdev->vendor, hdev->function, pd))) {
1497 printk(KERN_INFO "HiSax: %s detected\n",
1498 (char *)hdev->driver_data);
1499 pd->prepare(pd);
1500 pd->deactivate(pd);
1501 pd->activate(pd);
1502 card->para[1] = pd->resource[0].start;
1503 card->para[0] = pd->irq_resource[0].start;
1504 if (!card->para[0] || !card->para[1]) {
1505 printk(KERN_ERR "HFC PnP:some resources are missing %ld/%lx\n",
1506 card->para[0], card->para[1]);
1507 pd->deactivate(pd);
1508 return(0);
1509 }
1510 break;
1511 } else {
1512 printk(KERN_ERR "HFC PnP: PnP error card found, no device\n");
1513 }
1514 }
1515 hdev++;
1516 pnp_c=NULL;
1517 }
1518 if (!hdev->card_vendor) {
1519 printk(KERN_INFO "HFC PnP: no ISAPnP card found\n");
1520 return(0);
1521 }
1522 }
1523 #endif
1524 cs->hw.hfcsx.base = card->para[1] & 0xfffe;
1525 cs->irq = card->para[0];
1526 cs->hw.hfcsx.int_s1 = 0;
1527 cs->dc.hfcsx.ph_state = 0;
1528 cs->hw.hfcsx.fifo = 255;
1529 if ((cs->typ == ISDN_CTYPE_HFC_SX) ||
1530 (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) {
1531 if ((!cs->hw.hfcsx.base) ||
1532 check_region((cs->hw.hfcsx.base), 2)) {
1533 printk(KERN_WARNING
1534 "HiSax: HFC-SX io-base %#lx already in use\n",
1535 cs->hw.hfcsx.base);
1536 return(0);
1537 } else {
1538 request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn");
1539 }
1540 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF);
1541 byteout(cs->hw.hfcsx.base + 1,
1542 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54);
1543 udelay(10);
1544 cs->hw.hfcsx.chip = Read_hfc(cs,HFCSX_CHIP_ID);
1545 switch (cs->hw.hfcsx.chip >> 4) {
1546 case 1:
1547 tmp[0] ='+';
1548 break;
1549 case 9:
1550 tmp[0] ='P';
1551 break;
1552 default:
1553 printk(KERN_WARNING
1554 "HFC-SX: invalid chip id 0x%x\n",
1555 cs->hw.hfcsx.chip >> 4);
1556 release_region(cs->hw.hfcsx.base, 2);
1557 return(0);
1558 }
1559 if (!ccd_sp_irqtab[cs->irq & 0xF]) {
1560 printk(KERN_WARNING
1561 "HFC_SX: invalid irq %d specified\n",cs->irq & 0xF);
1562 release_region(cs->hw.hfcsx.base, 2);
1563 return(0);
1564 }
1565 save_flags(flags);
1566 cli();
1567 if (!(cs->hw.hfcsx.extra = (void *)
1568 kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) {
1569 restore_flags(flags);
1570 release_region(cs->hw.hfcsx.base, 2);
1571 printk(KERN_WARNING "HFC-SX: unable to allocate memory\n");
1572 return(0);
1573 }
1574 restore_flags(flags);
1575
1576 printk(KERN_INFO
1577 "HFC-S%c chip detected at base 0x%x IRQ %d HZ %d\n",
1578 tmp[0], (u_int) cs->hw.hfcsx.base,
1579 cs->irq, HZ);
1580 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */
1581 cs->hw.hfcsx.int_m1 = 0;
1582 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1583 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
1584 } else
1585 return (0); /* no valid card type */
1586
1587 cs->readisac = NULL;
1588 cs->writeisac = NULL;
1589 cs->readisacfifo = NULL;
1590 cs->writeisacfifo = NULL;
1591 cs->BC_Read_Reg = NULL;
1592 cs->BC_Write_Reg = NULL;
1593 cs->irq_func = &hfcsx_interrupt;
1594
1595 cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer;
1596 cs->hw.hfcsx.timer.data = (long) cs;
1597 cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */
1598 cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */
1599 init_timer(&cs->hw.hfcsx.timer);
1600
1601 reset_hfcsx(cs);
1602 cs->cardmsg = &hfcsx_card_msg;
1603 cs->auxcmd = &hfcsx_auxcmd;
1604 return (1);
1605 }
1606