1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * hda_intel.c - Implementation of primary alsa driver code base
5 * for Intel HD Audio.
6 *
7 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 *
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 *
12 * CONTACTS:
13 *
14 * Matt Jared matt.jared@intel.com
15 * Andy Kopp andy.kopp@intel.com
16 * Dan Kogan dan.d.kogan@intel.com
17 *
18 * CHANGES:
19 *
20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
21 */
22
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/mutex.h>
33 #include <linux/io.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clocksource.h>
36 #include <linux/time.h>
37 #include <linux/completion.h>
38 #include <linux/acpi.h>
39 #include <linux/pgtable.h>
40
41 #ifdef CONFIG_X86
42 /* for snoop control */
43 #include <asm/set_memory.h>
44 #include <asm/cpufeature.h>
45 #endif
46 #include <sound/core.h>
47 #include <sound/initval.h>
48 #include <sound/hdaudio.h>
49 #include <sound/hda_i915.h>
50 #include <sound/intel-dsp-config.h>
51 #include <linux/vgaarb.h>
52 #include <linux/vga_switcheroo.h>
53 #include <linux/firmware.h>
54 #include <sound/hda_codec.h>
55 #include "hda_controller.h"
56 #include "hda_intel.h"
57
58 #define CREATE_TRACE_POINTS
59 #include "hda_intel_trace.h"
60
61 /* position fix mode */
62 enum {
63 POS_FIX_AUTO,
64 POS_FIX_LPIB,
65 POS_FIX_POSBUF,
66 POS_FIX_VIACOMBO,
67 POS_FIX_COMBO,
68 POS_FIX_SKL,
69 POS_FIX_FIFO,
70 };
71
72 /* Defines for ATI HD Audio support in SB450 south bridge */
73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
75
76 /* Defines for Nvidia HDA support */
77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
79 #define NVIDIA_HDA_ISTRM_COH 0x4d
80 #define NVIDIA_HDA_OSTRM_COH 0x4c
81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
82
83 /* Defines for Intel SCH HDA snoop control */
84 #define INTEL_HDA_CGCTL 0x48
85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
86 #define INTEL_SCH_HDA_DEVC 0x78
87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
88
89 /* Define VIA HD Audio Device ID*/
90 #define VIA_HDAC_DEVICE_ID 0x3288
91
92 /* max number of SDs */
93 /* ICH, ATI and VIA have 4 playback and 4 capture */
94 #define ICH6_NUM_CAPTURE 4
95 #define ICH6_NUM_PLAYBACK 4
96
97 /* ULI has 6 playback and 5 capture */
98 #define ULI_NUM_CAPTURE 5
99 #define ULI_NUM_PLAYBACK 6
100
101 /* ATI HDMI may have up to 8 playbacks and 0 capture */
102 #define ATIHDMI_NUM_CAPTURE 0
103 #define ATIHDMI_NUM_PLAYBACK 8
104
105 /* TERA has 4 playback and 3 capture */
106 #define TERA_NUM_CAPTURE 3
107 #define TERA_NUM_PLAYBACK 4
108
109
110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
113 static char *model[SNDRV_CARDS];
114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
117 static int probe_only[SNDRV_CARDS];
118 static int jackpoll_ms[SNDRV_CARDS];
119 static int single_cmd = -1;
120 static int enable_msi = -1;
121 #ifdef CONFIG_SND_HDA_PATCH_LOADER
122 static char *patch[SNDRV_CARDS];
123 #endif
124 #ifdef CONFIG_SND_HDA_INPUT_BEEP
125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
126 CONFIG_SND_HDA_INPUT_BEEP_MODE};
127 #endif
128 static bool dmic_detect = 1;
129
130 module_param_array(index, int, NULL, 0444);
131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
132 module_param_array(id, charp, NULL, 0444);
133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
134 module_param_array(enable, bool, NULL, 0444);
135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
136 module_param_array(model, charp, NULL, 0444);
137 MODULE_PARM_DESC(model, "Use the given board model.");
138 module_param_array(position_fix, int, NULL, 0444);
139 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO).");
141 module_param_array(bdl_pos_adj, int, NULL, 0644);
142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
143 module_param_array(probe_mask, int, NULL, 0444);
144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
145 module_param_array(probe_only, int, NULL, 0444);
146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
147 module_param_array(jackpoll_ms, int, NULL, 0444);
148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
149 module_param(single_cmd, bint, 0444);
150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
151 "(for debugging only).");
152 module_param(enable_msi, bint, 0444);
153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
154 #ifdef CONFIG_SND_HDA_PATCH_LOADER
155 module_param_array(patch, charp, NULL, 0444);
156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
157 #endif
158 #ifdef CONFIG_SND_HDA_INPUT_BEEP
159 module_param_array(beep_mode, bool, NULL, 0444);
160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
161 "(0=off, 1=on) (default=1).");
162 #endif
163 module_param(dmic_detect, bool, 0444);
164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) "
165 "(0=off, 1=on) (default=1); "
166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead");
167
168 #ifdef CONFIG_PM
169 static int param_set_xint(const char *val, const struct kernel_param *kp);
170 static const struct kernel_param_ops param_ops_xint = {
171 .set = param_set_xint,
172 .get = param_get_int,
173 };
174 #define param_check_xint param_check_int
175
176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
177 module_param(power_save, xint, 0644);
178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
179 "(in second, 0 = disable).");
180
181 static bool pm_blacklist = true;
182 module_param(pm_blacklist, bool, 0644);
183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist");
184
185 /* reset the HD-audio controller in power save mode.
186 * this may give more power-saving, but will take longer time to
187 * wake up.
188 */
189 static bool power_save_controller = 1;
190 module_param(power_save_controller, bool, 0644);
191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
192 #else
193 #define power_save 0
194 #endif /* CONFIG_PM */
195
196 static int align_buffer_size = -1;
197 module_param(align_buffer_size, bint, 0644);
198 MODULE_PARM_DESC(align_buffer_size,
199 "Force buffer and period sizes to be multiple of 128 bytes.");
200
201 #ifdef CONFIG_X86
202 static int hda_snoop = -1;
203 module_param_named(snoop, hda_snoop, bint, 0444);
204 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
205 #else
206 #define hda_snoop true
207 #endif
208
209
210 MODULE_LICENSE("GPL");
211 MODULE_DESCRIPTION("Intel HDA driver");
212
213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
215 #define SUPPORT_VGA_SWITCHEROO
216 #endif
217 #endif
218
219
220 /*
221 */
222
223 /* driver types */
224 enum {
225 AZX_DRIVER_ICH,
226 AZX_DRIVER_PCH,
227 AZX_DRIVER_SCH,
228 AZX_DRIVER_SKL,
229 AZX_DRIVER_HDMI,
230 AZX_DRIVER_ATI,
231 AZX_DRIVER_ATIHDMI,
232 AZX_DRIVER_ATIHDMI_NS,
233 AZX_DRIVER_VIA,
234 AZX_DRIVER_SIS,
235 AZX_DRIVER_ULI,
236 AZX_DRIVER_NVIDIA,
237 AZX_DRIVER_TERA,
238 AZX_DRIVER_CTX,
239 AZX_DRIVER_CTHDA,
240 AZX_DRIVER_CMEDIA,
241 AZX_DRIVER_ZHAOXIN,
242 AZX_DRIVER_GENERIC,
243 AZX_NUM_DRIVERS, /* keep this as last entry */
244 };
245
246 #define azx_get_snoop_type(chip) \
247 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
248 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
249
250 /* quirks for old Intel chipsets */
251 #define AZX_DCAPS_INTEL_ICH \
252 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
253
254 /* quirks for Intel PCH */
255 #define AZX_DCAPS_INTEL_PCH_BASE \
256 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
257 AZX_DCAPS_SNOOP_TYPE(SCH))
258
259 /* PCH up to IVB; no runtime PM; bind with i915 gfx */
260 #define AZX_DCAPS_INTEL_PCH_NOPM \
261 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
262
263 /* PCH for HSW/BDW; with runtime PM */
264 /* no i915 binding for this as HSW/BDW has another controller for HDMI */
265 #define AZX_DCAPS_INTEL_PCH \
266 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
267
268 /* HSW HDMI */
269 #define AZX_DCAPS_INTEL_HASWELL \
270 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
271 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
272 AZX_DCAPS_SNOOP_TYPE(SCH))
273
274 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
275 #define AZX_DCAPS_INTEL_BROADWELL \
276 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
277 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\
278 AZX_DCAPS_SNOOP_TYPE(SCH))
279
280 #define AZX_DCAPS_INTEL_BAYTRAIL \
281 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)
282
283 #define AZX_DCAPS_INTEL_BRASWELL \
284 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
285 AZX_DCAPS_I915_COMPONENT)
286
287 #define AZX_DCAPS_INTEL_SKYLAKE \
288 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\
289 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)
290
291 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE
292
293 /* quirks for ATI SB / AMD Hudson */
294 #define AZX_DCAPS_PRESET_ATI_SB \
295 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\
296 AZX_DCAPS_SNOOP_TYPE(ATI))
297
298 /* quirks for ATI/AMD HDMI */
299 #define AZX_DCAPS_PRESET_ATI_HDMI \
300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\
301 AZX_DCAPS_NO_MSI64)
302
303 /* quirks for ATI HDMI with snoop off */
304 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
305 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
306
307 /* quirks for AMD SB */
308 #define AZX_DCAPS_PRESET_AMD_SB \
309 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\
310 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\
311 AZX_DCAPS_RETRY_PROBE)
312
313 /* quirks for Nvidia */
314 #define AZX_DCAPS_PRESET_NVIDIA \
315 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
316 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
317
318 #define AZX_DCAPS_PRESET_CTHDA \
319 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
320 AZX_DCAPS_NO_64BIT |\
321 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
322
323 /*
324 * vga_switcheroo support
325 */
326 #ifdef SUPPORT_VGA_SWITCHEROO
327 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
328 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power)
329 #else
330 #define use_vga_switcheroo(chip) 0
331 #define needs_eld_notify_link(chip) false
332 #endif
333
334 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
335 ((pci)->device == 0x0c0c) || \
336 ((pci)->device == 0x0d0c) || \
337 ((pci)->device == 0x160c) || \
338 ((pci)->device == 0x490d) || \
339 ((pci)->device == 0x4f90) || \
340 ((pci)->device == 0x4f91) || \
341 ((pci)->device == 0x4f92))
342
343 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
344
345 static const char * const driver_short_names[] = {
346 [AZX_DRIVER_ICH] = "HDA Intel",
347 [AZX_DRIVER_PCH] = "HDA Intel PCH",
348 [AZX_DRIVER_SCH] = "HDA Intel MID",
349 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */
350 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
351 [AZX_DRIVER_ATI] = "HDA ATI SB",
352 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
353 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
354 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
355 [AZX_DRIVER_SIS] = "HDA SIS966",
356 [AZX_DRIVER_ULI] = "HDA ULI M5461",
357 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
358 [AZX_DRIVER_TERA] = "HDA Teradici",
359 [AZX_DRIVER_CTX] = "HDA Creative",
360 [AZX_DRIVER_CTHDA] = "HDA Creative",
361 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
362 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin",
363 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
364 };
365
366 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
367 static void set_default_power_save(struct azx *chip);
368
369 /*
370 * initialize the PCI registers
371 */
372 /* update bits in a PCI register byte */
update_pci_byte(struct pci_dev * pci,unsigned int reg,unsigned char mask,unsigned char val)373 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
374 unsigned char mask, unsigned char val)
375 {
376 unsigned char data;
377
378 pci_read_config_byte(pci, reg, &data);
379 data &= ~mask;
380 data |= (val & mask);
381 pci_write_config_byte(pci, reg, data);
382 }
383
azx_init_pci(struct azx * chip)384 static void azx_init_pci(struct azx *chip)
385 {
386 int snoop_type = azx_get_snoop_type(chip);
387
388 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
389 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
390 * Ensuring these bits are 0 clears playback static on some HD Audio
391 * codecs.
392 * The PCI register TCSEL is defined in the Intel manuals.
393 */
394 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
395 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
396 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
397 }
398
399 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
400 * we need to enable snoop.
401 */
402 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
403 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
404 azx_snoop(chip));
405 update_pci_byte(chip->pci,
406 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
407 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
408 }
409
410 /* For NVIDIA HDA, enable snoop */
411 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
412 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
413 azx_snoop(chip));
414 update_pci_byte(chip->pci,
415 NVIDIA_HDA_TRANSREG_ADDR,
416 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
417 update_pci_byte(chip->pci,
418 NVIDIA_HDA_ISTRM_COH,
419 0x01, NVIDIA_HDA_ENABLE_COHBIT);
420 update_pci_byte(chip->pci,
421 NVIDIA_HDA_OSTRM_COH,
422 0x01, NVIDIA_HDA_ENABLE_COHBIT);
423 }
424
425 /* Enable SCH/PCH snoop if needed */
426 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
427 unsigned short snoop;
428 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
429 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
430 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
431 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
432 if (!azx_snoop(chip))
433 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
434 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
435 pci_read_config_word(chip->pci,
436 INTEL_SCH_HDA_DEVC, &snoop);
437 }
438 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
439 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
440 "Disabled" : "Enabled");
441 }
442 }
443
444 /*
445 * In BXT-P A0, HD-Audio DMA requests is later than expected,
446 * and makes an audio stream sensitive to system latencies when
447 * 24/32 bits are playing.
448 * Adjusting threshold of DMA fifo to force the DMA request
449 * sooner to improve latency tolerance at the expense of power.
450 */
bxt_reduce_dma_latency(struct azx * chip)451 static void bxt_reduce_dma_latency(struct azx *chip)
452 {
453 u32 val;
454
455 val = azx_readl(chip, VS_EM4L);
456 val &= (0x3 << 20);
457 azx_writel(chip, VS_EM4L, val);
458 }
459
460 /*
461 * ML_LCAP bits:
462 * bit 0: 6 MHz Supported
463 * bit 1: 12 MHz Supported
464 * bit 2: 24 MHz Supported
465 * bit 3: 48 MHz Supported
466 * bit 4: 96 MHz Supported
467 * bit 5: 192 MHz Supported
468 */
intel_get_lctl_scf(struct azx * chip)469 static int intel_get_lctl_scf(struct azx *chip)
470 {
471 struct hdac_bus *bus = azx_bus(chip);
472 static const int preferred_bits[] = { 2, 3, 1, 4, 5 };
473 u32 val, t;
474 int i;
475
476 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
477
478 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
479 t = preferred_bits[i];
480 if (val & (1 << t))
481 return t;
482 }
483
484 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
485 return 0;
486 }
487
intel_ml_lctl_set_power(struct azx * chip,int state)488 static int intel_ml_lctl_set_power(struct azx *chip, int state)
489 {
490 struct hdac_bus *bus = azx_bus(chip);
491 u32 val;
492 int timeout;
493
494 /*
495 * the codecs are sharing the first link setting by default
496 * If other links are enabled for stream, they need similar fix
497 */
498 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
499 val &= ~AZX_MLCTL_SPA;
500 val |= state << AZX_MLCTL_SPA_SHIFT;
501 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
502 /* wait for CPA */
503 timeout = 50;
504 while (timeout) {
505 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
506 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
507 return 0;
508 timeout--;
509 udelay(10);
510 }
511
512 return -1;
513 }
514
intel_init_lctl(struct azx * chip)515 static void intel_init_lctl(struct azx *chip)
516 {
517 struct hdac_bus *bus = azx_bus(chip);
518 u32 val;
519 int ret;
520
521 /* 0. check lctl register value is correct or not */
522 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
523 /* if SCF is already set, let's use it */
524 if ((val & ML_LCTL_SCF_MASK) != 0)
525 return;
526
527 /*
528 * Before operating on SPA, CPA must match SPA.
529 * Any deviation may result in undefined behavior.
530 */
531 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
532 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
533 return;
534
535 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
536 ret = intel_ml_lctl_set_power(chip, 0);
537 udelay(100);
538 if (ret)
539 goto set_spa;
540
541 /* 2. update SCF to select a properly audio clock*/
542 val &= ~ML_LCTL_SCF_MASK;
543 val |= intel_get_lctl_scf(chip);
544 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
545
546 set_spa:
547 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
548 intel_ml_lctl_set_power(chip, 1);
549 udelay(100);
550 }
551
hda_intel_init_chip(struct azx * chip,bool full_reset)552 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
553 {
554 struct hdac_bus *bus = azx_bus(chip);
555 struct pci_dev *pci = chip->pci;
556 u32 val;
557
558 snd_hdac_set_codec_wakeup(bus, true);
559 if (chip->driver_type == AZX_DRIVER_SKL) {
560 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
561 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
562 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
563 }
564 azx_init_chip(chip, full_reset);
565 if (chip->driver_type == AZX_DRIVER_SKL) {
566 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
567 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
568 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
569 }
570
571 snd_hdac_set_codec_wakeup(bus, false);
572
573 /* reduce dma latency to avoid noise */
574 if (IS_BXT(pci))
575 bxt_reduce_dma_latency(chip);
576
577 if (bus->mlcap != NULL)
578 intel_init_lctl(chip);
579 }
580
581 /* calculate runtime delay from LPIB */
azx_get_delay_from_lpib(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)582 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
583 unsigned int pos)
584 {
585 struct snd_pcm_substream *substream = azx_dev->core.substream;
586 int stream = substream->stream;
587 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
588 int delay;
589
590 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
591 delay = pos - lpib_pos;
592 else
593 delay = lpib_pos - pos;
594 if (delay < 0) {
595 if (delay >= azx_dev->core.delay_negative_threshold)
596 delay = 0;
597 else
598 delay += azx_dev->core.bufsize;
599 }
600
601 if (delay >= azx_dev->core.period_bytes) {
602 dev_info(chip->card->dev,
603 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
604 delay, azx_dev->core.period_bytes);
605 delay = 0;
606 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
607 chip->get_delay[stream] = NULL;
608 }
609
610 return bytes_to_frames(substream->runtime, delay);
611 }
612
613 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
614
615 /* called from IRQ */
azx_position_check(struct azx * chip,struct azx_dev * azx_dev)616 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
617 {
618 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
619 int ok;
620
621 ok = azx_position_ok(chip, azx_dev);
622 if (ok == 1) {
623 azx_dev->irq_pending = 0;
624 return ok;
625 } else if (ok == 0) {
626 /* bogus IRQ, process it later */
627 azx_dev->irq_pending = 1;
628 schedule_work(&hda->irq_pending_work);
629 }
630 return 0;
631 }
632
633 #define display_power(chip, enable) \
634 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable)
635
636 /*
637 * Check whether the current DMA position is acceptable for updating
638 * periods. Returns non-zero if it's OK.
639 *
640 * Many HD-audio controllers appear pretty inaccurate about
641 * the update-IRQ timing. The IRQ is issued before actually the
642 * data is processed. So, we need to process it afterwords in a
643 * workqueue.
644 *
645 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update
646 */
azx_position_ok(struct azx * chip,struct azx_dev * azx_dev)647 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
648 {
649 struct snd_pcm_substream *substream = azx_dev->core.substream;
650 struct snd_pcm_runtime *runtime = substream->runtime;
651 int stream = substream->stream;
652 u32 wallclk;
653 unsigned int pos;
654 snd_pcm_uframes_t hwptr, target;
655
656 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
657 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
658 return -1; /* bogus (too early) interrupt */
659
660 if (chip->get_position[stream])
661 pos = chip->get_position[stream](chip, azx_dev);
662 else { /* use the position buffer as default */
663 pos = azx_get_pos_posbuf(chip, azx_dev);
664 if (!pos || pos == (u32)-1) {
665 dev_info(chip->card->dev,
666 "Invalid position buffer, using LPIB read method instead.\n");
667 chip->get_position[stream] = azx_get_pos_lpib;
668 if (chip->get_position[0] == azx_get_pos_lpib &&
669 chip->get_position[1] == azx_get_pos_lpib)
670 azx_bus(chip)->use_posbuf = false;
671 pos = azx_get_pos_lpib(chip, azx_dev);
672 chip->get_delay[stream] = NULL;
673 } else {
674 chip->get_position[stream] = azx_get_pos_posbuf;
675 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
676 chip->get_delay[stream] = azx_get_delay_from_lpib;
677 }
678 }
679
680 if (pos >= azx_dev->core.bufsize)
681 pos = 0;
682
683 if (WARN_ONCE(!azx_dev->core.period_bytes,
684 "hda-intel: zero azx_dev->period_bytes"))
685 return -1; /* this shouldn't happen! */
686 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
687 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
688 /* NG - it's below the first next period boundary */
689 return chip->bdl_pos_adj ? 0 : -1;
690 azx_dev->core.start_wallclk += wallclk;
691
692 if (azx_dev->core.no_period_wakeup)
693 return 1; /* OK, no need to check period boundary */
694
695 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt)
696 return 1; /* OK, already in hwptr updating process */
697
698 /* check whether the period gets really elapsed */
699 pos = bytes_to_frames(runtime, pos);
700 hwptr = runtime->hw_ptr_base + pos;
701 if (hwptr < runtime->status->hw_ptr)
702 hwptr += runtime->buffer_size;
703 target = runtime->hw_ptr_interrupt + runtime->period_size;
704 if (hwptr < target) {
705 /* too early wakeup, process it later */
706 return chip->bdl_pos_adj ? 0 : -1;
707 }
708
709 return 1; /* OK, it's fine */
710 }
711
712 /*
713 * The work for pending PCM period updates.
714 */
azx_irq_pending_work(struct work_struct * work)715 static void azx_irq_pending_work(struct work_struct *work)
716 {
717 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
718 struct azx *chip = &hda->chip;
719 struct hdac_bus *bus = azx_bus(chip);
720 struct hdac_stream *s;
721 int pending, ok;
722
723 if (!hda->irq_pending_warned) {
724 dev_info(chip->card->dev,
725 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
726 chip->card->number);
727 hda->irq_pending_warned = 1;
728 }
729
730 for (;;) {
731 pending = 0;
732 spin_lock_irq(&bus->reg_lock);
733 list_for_each_entry(s, &bus->stream_list, list) {
734 struct azx_dev *azx_dev = stream_to_azx_dev(s);
735 if (!azx_dev->irq_pending ||
736 !s->substream ||
737 !s->running)
738 continue;
739 ok = azx_position_ok(chip, azx_dev);
740 if (ok > 0) {
741 azx_dev->irq_pending = 0;
742 spin_unlock(&bus->reg_lock);
743 snd_pcm_period_elapsed(s->substream);
744 spin_lock(&bus->reg_lock);
745 } else if (ok < 0) {
746 pending = 0; /* too early */
747 } else
748 pending++;
749 }
750 spin_unlock_irq(&bus->reg_lock);
751 if (!pending)
752 return;
753 msleep(1);
754 }
755 }
756
757 /* clear irq_pending flags and assure no on-going workq */
azx_clear_irq_pending(struct azx * chip)758 static void azx_clear_irq_pending(struct azx *chip)
759 {
760 struct hdac_bus *bus = azx_bus(chip);
761 struct hdac_stream *s;
762
763 spin_lock_irq(&bus->reg_lock);
764 list_for_each_entry(s, &bus->stream_list, list) {
765 struct azx_dev *azx_dev = stream_to_azx_dev(s);
766 azx_dev->irq_pending = 0;
767 }
768 spin_unlock_irq(&bus->reg_lock);
769 }
770
azx_acquire_irq(struct azx * chip,int do_disconnect)771 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
772 {
773 struct hdac_bus *bus = azx_bus(chip);
774
775 if (request_irq(chip->pci->irq, azx_interrupt,
776 chip->msi ? 0 : IRQF_SHARED,
777 chip->card->irq_descr, chip)) {
778 dev_err(chip->card->dev,
779 "unable to grab IRQ %d, disabling device\n",
780 chip->pci->irq);
781 if (do_disconnect)
782 snd_card_disconnect(chip->card);
783 return -1;
784 }
785 bus->irq = chip->pci->irq;
786 chip->card->sync_irq = bus->irq;
787 pci_intx(chip->pci, !chip->msi);
788 return 0;
789 }
790
791 /* get the current DMA position with correction on VIA chips */
azx_via_get_position(struct azx * chip,struct azx_dev * azx_dev)792 static unsigned int azx_via_get_position(struct azx *chip,
793 struct azx_dev *azx_dev)
794 {
795 unsigned int link_pos, mini_pos, bound_pos;
796 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
797 unsigned int fifo_size;
798
799 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
800 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
801 /* Playback, no problem using link position */
802 return link_pos;
803 }
804
805 /* Capture */
806 /* For new chipset,
807 * use mod to get the DMA position just like old chipset
808 */
809 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
810 mod_dma_pos %= azx_dev->core.period_bytes;
811
812 fifo_size = azx_stream(azx_dev)->fifo_size - 1;
813
814 if (azx_dev->insufficient) {
815 /* Link position never gather than FIFO size */
816 if (link_pos <= fifo_size)
817 return 0;
818
819 azx_dev->insufficient = 0;
820 }
821
822 if (link_pos <= fifo_size)
823 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
824 else
825 mini_pos = link_pos - fifo_size;
826
827 /* Find nearest previous boudary */
828 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
829 mod_link_pos = link_pos % azx_dev->core.period_bytes;
830 if (mod_link_pos >= fifo_size)
831 bound_pos = link_pos - mod_link_pos;
832 else if (mod_dma_pos >= mod_mini_pos)
833 bound_pos = mini_pos - mod_mini_pos;
834 else {
835 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
836 if (bound_pos >= azx_dev->core.bufsize)
837 bound_pos = 0;
838 }
839
840 /* Calculate real DMA position we want */
841 return bound_pos + mod_dma_pos;
842 }
843
844 #define AMD_FIFO_SIZE 32
845
846 /* get the current DMA position with FIFO size correction */
azx_get_pos_fifo(struct azx * chip,struct azx_dev * azx_dev)847 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev)
848 {
849 struct snd_pcm_substream *substream = azx_dev->core.substream;
850 struct snd_pcm_runtime *runtime = substream->runtime;
851 unsigned int pos, delay;
852
853 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
854 if (!runtime)
855 return pos;
856
857 runtime->delay = AMD_FIFO_SIZE;
858 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE);
859 if (azx_dev->insufficient) {
860 if (pos < delay) {
861 delay = pos;
862 runtime->delay = bytes_to_frames(runtime, pos);
863 } else {
864 azx_dev->insufficient = 0;
865 }
866 }
867
868 /* correct the DMA position for capture stream */
869 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
870 if (pos < delay)
871 pos += azx_dev->core.bufsize;
872 pos -= delay;
873 }
874
875 return pos;
876 }
877
azx_get_delay_from_fifo(struct azx * chip,struct azx_dev * azx_dev,unsigned int pos)878 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev,
879 unsigned int pos)
880 {
881 struct snd_pcm_substream *substream = azx_dev->core.substream;
882
883 /* just read back the calculated value in the above */
884 return substream->runtime->delay;
885 }
886
__azx_shutdown_chip(struct azx * chip,bool skip_link_reset)887 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset)
888 {
889 azx_stop_chip(chip);
890 if (!skip_link_reset)
891 azx_enter_link_reset(chip);
892 azx_clear_irq_pending(chip);
893 display_power(chip, false);
894 }
895
896 #ifdef CONFIG_PM
897 static DEFINE_MUTEX(card_list_lock);
898 static LIST_HEAD(card_list);
899
azx_shutdown_chip(struct azx * chip)900 static void azx_shutdown_chip(struct azx *chip)
901 {
902 __azx_shutdown_chip(chip, false);
903 }
904
azx_add_card_list(struct azx * chip)905 static void azx_add_card_list(struct azx *chip)
906 {
907 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
908 mutex_lock(&card_list_lock);
909 list_add(&hda->list, &card_list);
910 mutex_unlock(&card_list_lock);
911 }
912
azx_del_card_list(struct azx * chip)913 static void azx_del_card_list(struct azx *chip)
914 {
915 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
916 mutex_lock(&card_list_lock);
917 list_del_init(&hda->list);
918 mutex_unlock(&card_list_lock);
919 }
920
921 /* trigger power-save check at writing parameter */
param_set_xint(const char * val,const struct kernel_param * kp)922 static int param_set_xint(const char *val, const struct kernel_param *kp)
923 {
924 struct hda_intel *hda;
925 struct azx *chip;
926 int prev = power_save;
927 int ret = param_set_int(val, kp);
928
929 if (ret || prev == power_save)
930 return ret;
931
932 mutex_lock(&card_list_lock);
933 list_for_each_entry(hda, &card_list, list) {
934 chip = &hda->chip;
935 if (!hda->probe_continued || chip->disabled)
936 continue;
937 snd_hda_set_power_save(&chip->bus, power_save * 1000);
938 }
939 mutex_unlock(&card_list_lock);
940 return 0;
941 }
942
943 /*
944 * power management
945 */
azx_is_pm_ready(struct snd_card * card)946 static bool azx_is_pm_ready(struct snd_card *card)
947 {
948 struct azx *chip;
949 struct hda_intel *hda;
950
951 if (!card)
952 return false;
953 chip = card->private_data;
954 hda = container_of(chip, struct hda_intel, chip);
955 if (chip->disabled || hda->init_failed || !chip->running)
956 return false;
957 return true;
958 }
959
__azx_runtime_resume(struct azx * chip)960 static void __azx_runtime_resume(struct azx *chip)
961 {
962 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
963 struct hdac_bus *bus = azx_bus(chip);
964 struct hda_codec *codec;
965 int status;
966
967 display_power(chip, true);
968 if (hda->need_i915_power)
969 snd_hdac_i915_set_bclk(bus);
970
971 /* Read STATESTS before controller reset */
972 status = azx_readw(chip, STATESTS);
973
974 azx_init_pci(chip);
975 hda_intel_init_chip(chip, true);
976
977 /* Avoid codec resume if runtime resume is for system suspend */
978 if (!chip->pm_prepared) {
979 list_for_each_codec(codec, &chip->bus) {
980 if (codec->relaxed_resume)
981 continue;
982
983 if (codec->forced_resume || (status & (1 << codec->addr)))
984 pm_request_resume(hda_codec_dev(codec));
985 }
986 }
987
988 /* power down again for link-controlled chips */
989 if (!hda->need_i915_power)
990 display_power(chip, false);
991 }
992
993 #ifdef CONFIG_PM_SLEEP
azx_prepare(struct device * dev)994 static int azx_prepare(struct device *dev)
995 {
996 struct snd_card *card = dev_get_drvdata(dev);
997 struct azx *chip;
998
999 if (!azx_is_pm_ready(card))
1000 return 0;
1001
1002 chip = card->private_data;
1003 chip->pm_prepared = 1;
1004 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1005
1006 flush_work(&azx_bus(chip)->unsol_work);
1007
1008 /* HDA controller always requires different WAKEEN for runtime suspend
1009 * and system suspend, so don't use direct-complete here.
1010 */
1011 return 0;
1012 }
1013
azx_complete(struct device * dev)1014 static void azx_complete(struct device *dev)
1015 {
1016 struct snd_card *card = dev_get_drvdata(dev);
1017 struct azx *chip;
1018
1019 if (!azx_is_pm_ready(card))
1020 return;
1021
1022 chip = card->private_data;
1023 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1024 chip->pm_prepared = 0;
1025 }
1026
azx_suspend(struct device * dev)1027 static int azx_suspend(struct device *dev)
1028 {
1029 struct snd_card *card = dev_get_drvdata(dev);
1030 struct azx *chip;
1031 struct hdac_bus *bus;
1032
1033 if (!azx_is_pm_ready(card))
1034 return 0;
1035
1036 chip = card->private_data;
1037 bus = azx_bus(chip);
1038 azx_shutdown_chip(chip);
1039 if (bus->irq >= 0) {
1040 free_irq(bus->irq, chip);
1041 bus->irq = -1;
1042 chip->card->sync_irq = -1;
1043 }
1044
1045 if (chip->msi)
1046 pci_disable_msi(chip->pci);
1047
1048 trace_azx_suspend(chip);
1049 return 0;
1050 }
1051
azx_resume(struct device * dev)1052 static int azx_resume(struct device *dev)
1053 {
1054 struct snd_card *card = dev_get_drvdata(dev);
1055 struct azx *chip;
1056
1057 if (!azx_is_pm_ready(card))
1058 return 0;
1059
1060 chip = card->private_data;
1061 if (chip->msi)
1062 if (pci_enable_msi(chip->pci) < 0)
1063 chip->msi = 0;
1064 if (azx_acquire_irq(chip, 1) < 0)
1065 return -EIO;
1066
1067 __azx_runtime_resume(chip);
1068
1069 trace_azx_resume(chip);
1070 return 0;
1071 }
1072
1073 /* put codec down to D3 at hibernation for Intel SKL+;
1074 * otherwise BIOS may still access the codec and screw up the driver
1075 */
azx_freeze_noirq(struct device * dev)1076 static int azx_freeze_noirq(struct device *dev)
1077 {
1078 struct snd_card *card = dev_get_drvdata(dev);
1079 struct azx *chip = card->private_data;
1080 struct pci_dev *pci = to_pci_dev(dev);
1081
1082 if (!azx_is_pm_ready(card))
1083 return 0;
1084 if (chip->driver_type == AZX_DRIVER_SKL)
1085 pci_set_power_state(pci, PCI_D3hot);
1086
1087 return 0;
1088 }
1089
azx_thaw_noirq(struct device * dev)1090 static int azx_thaw_noirq(struct device *dev)
1091 {
1092 struct snd_card *card = dev_get_drvdata(dev);
1093 struct azx *chip = card->private_data;
1094 struct pci_dev *pci = to_pci_dev(dev);
1095
1096 if (!azx_is_pm_ready(card))
1097 return 0;
1098 if (chip->driver_type == AZX_DRIVER_SKL)
1099 pci_set_power_state(pci, PCI_D0);
1100
1101 return 0;
1102 }
1103 #endif /* CONFIG_PM_SLEEP */
1104
azx_runtime_suspend(struct device * dev)1105 static int azx_runtime_suspend(struct device *dev)
1106 {
1107 struct snd_card *card = dev_get_drvdata(dev);
1108 struct azx *chip;
1109
1110 if (!azx_is_pm_ready(card))
1111 return 0;
1112 chip = card->private_data;
1113
1114 /* enable controller wake up event */
1115 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK);
1116
1117 azx_shutdown_chip(chip);
1118 trace_azx_runtime_suspend(chip);
1119 return 0;
1120 }
1121
azx_runtime_resume(struct device * dev)1122 static int azx_runtime_resume(struct device *dev)
1123 {
1124 struct snd_card *card = dev_get_drvdata(dev);
1125 struct azx *chip;
1126
1127 if (!azx_is_pm_ready(card))
1128 return 0;
1129 chip = card->private_data;
1130 __azx_runtime_resume(chip);
1131
1132 /* disable controller Wake Up event*/
1133 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK);
1134
1135 trace_azx_runtime_resume(chip);
1136 return 0;
1137 }
1138
azx_runtime_idle(struct device * dev)1139 static int azx_runtime_idle(struct device *dev)
1140 {
1141 struct snd_card *card = dev_get_drvdata(dev);
1142 struct azx *chip;
1143 struct hda_intel *hda;
1144
1145 if (!card)
1146 return 0;
1147
1148 chip = card->private_data;
1149 hda = container_of(chip, struct hda_intel, chip);
1150 if (chip->disabled || hda->init_failed)
1151 return 0;
1152
1153 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1154 azx_bus(chip)->codec_powered || !chip->running)
1155 return -EBUSY;
1156
1157 /* ELD notification gets broken when HD-audio bus is off */
1158 if (needs_eld_notify_link(chip))
1159 return -EBUSY;
1160
1161 return 0;
1162 }
1163
1164 static const struct dev_pm_ops azx_pm = {
1165 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1166 #ifdef CONFIG_PM_SLEEP
1167 .prepare = azx_prepare,
1168 .complete = azx_complete,
1169 .freeze_noirq = azx_freeze_noirq,
1170 .thaw_noirq = azx_thaw_noirq,
1171 #endif
1172 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1173 };
1174
1175 #define AZX_PM_OPS &azx_pm
1176 #else
1177 #define azx_add_card_list(chip) /* NOP */
1178 #define azx_del_card_list(chip) /* NOP */
1179 #define AZX_PM_OPS NULL
1180 #endif /* CONFIG_PM */
1181
1182
1183 static int azx_probe_continue(struct azx *chip);
1184
1185 #ifdef SUPPORT_VGA_SWITCHEROO
1186 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1187
azx_vs_set_state(struct pci_dev * pci,enum vga_switcheroo_state state)1188 static void azx_vs_set_state(struct pci_dev *pci,
1189 enum vga_switcheroo_state state)
1190 {
1191 struct snd_card *card = pci_get_drvdata(pci);
1192 struct azx *chip = card->private_data;
1193 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1194 struct hda_codec *codec;
1195 bool disabled;
1196
1197 wait_for_completion(&hda->probe_wait);
1198 if (hda->init_failed)
1199 return;
1200
1201 disabled = (state == VGA_SWITCHEROO_OFF);
1202 if (chip->disabled == disabled)
1203 return;
1204
1205 if (!hda->probe_continued) {
1206 chip->disabled = disabled;
1207 if (!disabled) {
1208 dev_info(chip->card->dev,
1209 "Start delayed initialization\n");
1210 if (azx_probe_continue(chip) < 0)
1211 dev_err(chip->card->dev, "initialization error\n");
1212 }
1213 } else {
1214 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1215 disabled ? "Disabling" : "Enabling");
1216 if (disabled) {
1217 list_for_each_codec(codec, &chip->bus) {
1218 pm_runtime_suspend(hda_codec_dev(codec));
1219 pm_runtime_disable(hda_codec_dev(codec));
1220 }
1221 pm_runtime_suspend(card->dev);
1222 pm_runtime_disable(card->dev);
1223 /* when we get suspended by vga_switcheroo we end up in D3cold,
1224 * however we have no ACPI handle, so pci/acpi can't put us there,
1225 * put ourselves there */
1226 pci->current_state = PCI_D3cold;
1227 chip->disabled = true;
1228 if (snd_hda_lock_devices(&chip->bus))
1229 dev_warn(chip->card->dev,
1230 "Cannot lock devices!\n");
1231 } else {
1232 snd_hda_unlock_devices(&chip->bus);
1233 chip->disabled = false;
1234 pm_runtime_enable(card->dev);
1235 list_for_each_codec(codec, &chip->bus) {
1236 pm_runtime_enable(hda_codec_dev(codec));
1237 pm_runtime_resume(hda_codec_dev(codec));
1238 }
1239 }
1240 }
1241 }
1242
azx_vs_can_switch(struct pci_dev * pci)1243 static bool azx_vs_can_switch(struct pci_dev *pci)
1244 {
1245 struct snd_card *card = pci_get_drvdata(pci);
1246 struct azx *chip = card->private_data;
1247 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1248
1249 wait_for_completion(&hda->probe_wait);
1250 if (hda->init_failed)
1251 return false;
1252 if (chip->disabled || !hda->probe_continued)
1253 return true;
1254 if (snd_hda_lock_devices(&chip->bus))
1255 return false;
1256 snd_hda_unlock_devices(&chip->bus);
1257 return true;
1258 }
1259
1260 /*
1261 * The discrete GPU cannot power down unless the HDA controller runtime
1262 * suspends, so activate runtime PM on codecs even if power_save == 0.
1263 */
setup_vga_switcheroo_runtime_pm(struct azx * chip)1264 static void setup_vga_switcheroo_runtime_pm(struct azx *chip)
1265 {
1266 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1267 struct hda_codec *codec;
1268
1269 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) {
1270 list_for_each_codec(codec, &chip->bus)
1271 codec->auto_runtime_pm = 1;
1272 /* reset the power save setup */
1273 if (chip->running)
1274 set_default_power_save(chip);
1275 }
1276 }
1277
azx_vs_gpu_bound(struct pci_dev * pci,enum vga_switcheroo_client_id client_id)1278 static void azx_vs_gpu_bound(struct pci_dev *pci,
1279 enum vga_switcheroo_client_id client_id)
1280 {
1281 struct snd_card *card = pci_get_drvdata(pci);
1282 struct azx *chip = card->private_data;
1283
1284 if (client_id == VGA_SWITCHEROO_DIS)
1285 chip->bus.keep_power = 0;
1286 setup_vga_switcheroo_runtime_pm(chip);
1287 }
1288
init_vga_switcheroo(struct azx * chip)1289 static void init_vga_switcheroo(struct azx *chip)
1290 {
1291 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1292 struct pci_dev *p = get_bound_vga(chip->pci);
1293 struct pci_dev *parent;
1294 if (p) {
1295 dev_info(chip->card->dev,
1296 "Handle vga_switcheroo audio client\n");
1297 hda->use_vga_switcheroo = 1;
1298
1299 /* cleared in either gpu_bound op or codec probe, or when its
1300 * upstream port has _PR3 (i.e. dGPU).
1301 */
1302 parent = pci_upstream_bridge(p);
1303 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1;
1304 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME;
1305 pci_dev_put(p);
1306 }
1307 }
1308
1309 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1310 .set_gpu_state = azx_vs_set_state,
1311 .can_switch = azx_vs_can_switch,
1312 .gpu_bound = azx_vs_gpu_bound,
1313 };
1314
register_vga_switcheroo(struct azx * chip)1315 static int register_vga_switcheroo(struct azx *chip)
1316 {
1317 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1318 struct pci_dev *p;
1319 int err;
1320
1321 if (!hda->use_vga_switcheroo)
1322 return 0;
1323
1324 p = get_bound_vga(chip->pci);
1325 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p);
1326 pci_dev_put(p);
1327
1328 if (err < 0)
1329 return err;
1330 hda->vga_switcheroo_registered = 1;
1331
1332 return 0;
1333 }
1334 #else
1335 #define init_vga_switcheroo(chip) /* NOP */
1336 #define register_vga_switcheroo(chip) 0
1337 #define check_hdmi_disabled(pci) false
1338 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */
1339 #endif /* SUPPORT_VGA_SWITCHER */
1340
1341 /*
1342 * destructor
1343 */
azx_free(struct azx * chip)1344 static void azx_free(struct azx *chip)
1345 {
1346 struct pci_dev *pci = chip->pci;
1347 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1348 struct hdac_bus *bus = azx_bus(chip);
1349
1350 if (hda->freed)
1351 return;
1352
1353 if (azx_has_pm_runtime(chip) && chip->running) {
1354 pm_runtime_get_noresume(&pci->dev);
1355 pm_runtime_forbid(&pci->dev);
1356 pm_runtime_dont_use_autosuspend(&pci->dev);
1357 }
1358
1359 chip->running = 0;
1360
1361 azx_del_card_list(chip);
1362
1363 hda->init_failed = 1; /* to be sure */
1364 complete_all(&hda->probe_wait);
1365
1366 if (use_vga_switcheroo(hda)) {
1367 if (chip->disabled && hda->probe_continued)
1368 snd_hda_unlock_devices(&chip->bus);
1369 if (hda->vga_switcheroo_registered)
1370 vga_switcheroo_unregister_client(chip->pci);
1371 }
1372
1373 if (bus->chip_init) {
1374 azx_clear_irq_pending(chip);
1375 azx_stop_all_streams(chip);
1376 azx_stop_chip(chip);
1377 }
1378
1379 if (bus->irq >= 0)
1380 free_irq(bus->irq, (void*)chip);
1381
1382 azx_free_stream_pages(chip);
1383 azx_free_streams(chip);
1384 snd_hdac_bus_exit(bus);
1385
1386 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1387 release_firmware(chip->fw);
1388 #endif
1389 display_power(chip, false);
1390
1391 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)
1392 snd_hdac_i915_exit(bus);
1393
1394 hda->freed = 1;
1395 }
1396
azx_dev_disconnect(struct snd_device * device)1397 static int azx_dev_disconnect(struct snd_device *device)
1398 {
1399 struct azx *chip = device->device_data;
1400 struct hdac_bus *bus = azx_bus(chip);
1401
1402 chip->bus.shutdown = 1;
1403 cancel_work_sync(&bus->unsol_work);
1404
1405 return 0;
1406 }
1407
azx_dev_free(struct snd_device * device)1408 static int azx_dev_free(struct snd_device *device)
1409 {
1410 azx_free(device->device_data);
1411 return 0;
1412 }
1413
1414 #ifdef SUPPORT_VGA_SWITCHEROO
1415 #ifdef CONFIG_ACPI
1416 /* ATPX is in the integrated GPU's namespace */
atpx_present(void)1417 static bool atpx_present(void)
1418 {
1419 struct pci_dev *pdev = NULL;
1420 acpi_handle dhandle, atpx_handle;
1421 acpi_status status;
1422
1423 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
1424 dhandle = ACPI_HANDLE(&pdev->dev);
1425 if (dhandle) {
1426 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1427 if (ACPI_SUCCESS(status)) {
1428 pci_dev_put(pdev);
1429 return true;
1430 }
1431 }
1432 }
1433 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
1434 dhandle = ACPI_HANDLE(&pdev->dev);
1435 if (dhandle) {
1436 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
1437 if (ACPI_SUCCESS(status)) {
1438 pci_dev_put(pdev);
1439 return true;
1440 }
1441 }
1442 }
1443 return false;
1444 }
1445 #else
atpx_present(void)1446 static bool atpx_present(void)
1447 {
1448 return false;
1449 }
1450 #endif
1451
1452 /*
1453 * Check of disabled HDMI controller by vga_switcheroo
1454 */
get_bound_vga(struct pci_dev * pci)1455 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1456 {
1457 struct pci_dev *p;
1458
1459 /* check only discrete GPU */
1460 switch (pci->vendor) {
1461 case PCI_VENDOR_ID_ATI:
1462 case PCI_VENDOR_ID_AMD:
1463 if (pci->devfn == 1) {
1464 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1465 pci->bus->number, 0);
1466 if (p) {
1467 /* ATPX is in the integrated GPU's ACPI namespace
1468 * rather than the dGPU's namespace. However,
1469 * the dGPU is the one who is involved in
1470 * vgaswitcheroo.
1471 */
1472 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
1473 atpx_present())
1474 return p;
1475 pci_dev_put(p);
1476 }
1477 }
1478 break;
1479 case PCI_VENDOR_ID_NVIDIA:
1480 if (pci->devfn == 1) {
1481 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1482 pci->bus->number, 0);
1483 if (p) {
1484 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1485 return p;
1486 pci_dev_put(p);
1487 }
1488 }
1489 break;
1490 }
1491 return NULL;
1492 }
1493
check_hdmi_disabled(struct pci_dev * pci)1494 static bool check_hdmi_disabled(struct pci_dev *pci)
1495 {
1496 bool vga_inactive = false;
1497 struct pci_dev *p = get_bound_vga(pci);
1498
1499 if (p) {
1500 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1501 vga_inactive = true;
1502 pci_dev_put(p);
1503 }
1504 return vga_inactive;
1505 }
1506 #endif /* SUPPORT_VGA_SWITCHEROO */
1507
1508 /*
1509 * allow/deny-listing for position_fix
1510 */
1511 static const struct snd_pci_quirk position_fix_list[] = {
1512 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1513 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1514 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1515 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1516 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1517 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1518 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1519 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1520 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1521 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1522 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1523 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1524 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1525 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1526 {}
1527 };
1528
check_position_fix(struct azx * chip,int fix)1529 static int check_position_fix(struct azx *chip, int fix)
1530 {
1531 const struct snd_pci_quirk *q;
1532
1533 switch (fix) {
1534 case POS_FIX_AUTO:
1535 case POS_FIX_LPIB:
1536 case POS_FIX_POSBUF:
1537 case POS_FIX_VIACOMBO:
1538 case POS_FIX_COMBO:
1539 case POS_FIX_SKL:
1540 case POS_FIX_FIFO:
1541 return fix;
1542 }
1543
1544 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1545 if (q) {
1546 dev_info(chip->card->dev,
1547 "position_fix set to %d for device %04x:%04x\n",
1548 q->value, q->subvendor, q->subdevice);
1549 return q->value;
1550 }
1551
1552 /* Check VIA/ATI HD Audio Controller exist */
1553 if (chip->driver_type == AZX_DRIVER_VIA) {
1554 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1555 return POS_FIX_VIACOMBO;
1556 }
1557 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) {
1558 dev_dbg(chip->card->dev, "Using FIFO position fix\n");
1559 return POS_FIX_FIFO;
1560 }
1561 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1562 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1563 return POS_FIX_LPIB;
1564 }
1565 if (chip->driver_type == AZX_DRIVER_SKL) {
1566 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1567 return POS_FIX_SKL;
1568 }
1569 return POS_FIX_AUTO;
1570 }
1571
assign_position_fix(struct azx * chip,int fix)1572 static void assign_position_fix(struct azx *chip, int fix)
1573 {
1574 static const azx_get_pos_callback_t callbacks[] = {
1575 [POS_FIX_AUTO] = NULL,
1576 [POS_FIX_LPIB] = azx_get_pos_lpib,
1577 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1578 [POS_FIX_VIACOMBO] = azx_via_get_position,
1579 [POS_FIX_COMBO] = azx_get_pos_lpib,
1580 [POS_FIX_SKL] = azx_get_pos_posbuf,
1581 [POS_FIX_FIFO] = azx_get_pos_fifo,
1582 };
1583
1584 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1585
1586 /* combo mode uses LPIB only for playback */
1587 if (fix == POS_FIX_COMBO)
1588 chip->get_position[1] = NULL;
1589
1590 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1591 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1592 chip->get_delay[0] = chip->get_delay[1] =
1593 azx_get_delay_from_lpib;
1594 }
1595
1596 if (fix == POS_FIX_FIFO)
1597 chip->get_delay[0] = chip->get_delay[1] =
1598 azx_get_delay_from_fifo;
1599 }
1600
1601 /*
1602 * deny-lists for probe_mask
1603 */
1604 static const struct snd_pci_quirk probe_mask_list[] = {
1605 /* Thinkpad often breaks the controller communication when accessing
1606 * to the non-working (or non-existing) modem codec slot.
1607 */
1608 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1609 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1610 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1611 /* broken BIOS */
1612 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1613 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1614 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1615 /* forced codec slots */
1616 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1617 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1618 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105),
1619 /* WinFast VP200 H (Teradici) user reported broken communication */
1620 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1621 {}
1622 };
1623
1624 #define AZX_FORCE_CODEC_MASK 0x100
1625
check_probe_mask(struct azx * chip,int dev)1626 static void check_probe_mask(struct azx *chip, int dev)
1627 {
1628 const struct snd_pci_quirk *q;
1629
1630 chip->codec_probe_mask = probe_mask[dev];
1631 if (chip->codec_probe_mask == -1) {
1632 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1633 if (q) {
1634 dev_info(chip->card->dev,
1635 "probe_mask set to 0x%x for device %04x:%04x\n",
1636 q->value, q->subvendor, q->subdevice);
1637 chip->codec_probe_mask = q->value;
1638 }
1639 }
1640
1641 /* check forced option */
1642 if (chip->codec_probe_mask != -1 &&
1643 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1644 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1645 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1646 (int)azx_bus(chip)->codec_mask);
1647 }
1648 }
1649
1650 /*
1651 * allow/deny-list for enable_msi
1652 */
1653 static const struct snd_pci_quirk msi_deny_list[] = {
1654 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1655 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1656 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1657 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1658 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1659 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1660 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1661 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1662 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1663 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1664 {}
1665 };
1666
check_msi(struct azx * chip)1667 static void check_msi(struct azx *chip)
1668 {
1669 const struct snd_pci_quirk *q;
1670
1671 if (enable_msi >= 0) {
1672 chip->msi = !!enable_msi;
1673 return;
1674 }
1675 chip->msi = 1; /* enable MSI as default */
1676 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list);
1677 if (q) {
1678 dev_info(chip->card->dev,
1679 "msi for device %04x:%04x set to %d\n",
1680 q->subvendor, q->subdevice, q->value);
1681 chip->msi = q->value;
1682 return;
1683 }
1684
1685 /* NVidia chipsets seem to cause troubles with MSI */
1686 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1687 dev_info(chip->card->dev, "Disabling MSI\n");
1688 chip->msi = 0;
1689 }
1690 }
1691
1692 /* check the snoop mode availability */
azx_check_snoop_available(struct azx * chip)1693 static void azx_check_snoop_available(struct azx *chip)
1694 {
1695 int snoop = hda_snoop;
1696
1697 if (snoop >= 0) {
1698 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1699 snoop ? "snoop" : "non-snoop");
1700 chip->snoop = snoop;
1701 chip->uc_buffer = !snoop;
1702 return;
1703 }
1704
1705 snoop = true;
1706 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1707 chip->driver_type == AZX_DRIVER_VIA) {
1708 /* force to non-snoop mode for a new VIA controller
1709 * when BIOS is set
1710 */
1711 u8 val;
1712 pci_read_config_byte(chip->pci, 0x42, &val);
1713 if (!(val & 0x80) && (chip->pci->revision == 0x30 ||
1714 chip->pci->revision == 0x20))
1715 snoop = false;
1716 }
1717
1718 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1719 snoop = false;
1720
1721 chip->snoop = snoop;
1722 if (!snoop) {
1723 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1724 /* C-Media requires non-cached pages only for CORB/RIRB */
1725 if (chip->driver_type != AZX_DRIVER_CMEDIA)
1726 chip->uc_buffer = true;
1727 }
1728 }
1729
azx_probe_work(struct work_struct * work)1730 static void azx_probe_work(struct work_struct *work)
1731 {
1732 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work);
1733 azx_probe_continue(&hda->chip);
1734 }
1735
default_bdl_pos_adj(struct azx * chip)1736 static int default_bdl_pos_adj(struct azx *chip)
1737 {
1738 /* some exceptions: Atoms seem problematic with value 1 */
1739 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1740 switch (chip->pci->device) {
1741 case 0x0f04: /* Baytrail */
1742 case 0x2284: /* Braswell */
1743 return 32;
1744 }
1745 }
1746
1747 switch (chip->driver_type) {
1748 case AZX_DRIVER_ICH:
1749 case AZX_DRIVER_PCH:
1750 return 1;
1751 default:
1752 return 32;
1753 }
1754 }
1755
1756 /*
1757 * constructor
1758 */
1759 static const struct hda_controller_ops pci_hda_ops;
1760
azx_create(struct snd_card * card,struct pci_dev * pci,int dev,unsigned int driver_caps,struct azx ** rchip)1761 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1762 int dev, unsigned int driver_caps,
1763 struct azx **rchip)
1764 {
1765 static const struct snd_device_ops ops = {
1766 .dev_disconnect = azx_dev_disconnect,
1767 .dev_free = azx_dev_free,
1768 };
1769 struct hda_intel *hda;
1770 struct azx *chip;
1771 int err;
1772
1773 *rchip = NULL;
1774
1775 err = pcim_enable_device(pci);
1776 if (err < 0)
1777 return err;
1778
1779 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL);
1780 if (!hda)
1781 return -ENOMEM;
1782
1783 chip = &hda->chip;
1784 mutex_init(&chip->open_mutex);
1785 chip->card = card;
1786 chip->pci = pci;
1787 chip->ops = &pci_hda_ops;
1788 chip->driver_caps = driver_caps;
1789 chip->driver_type = driver_caps & 0xff;
1790 check_msi(chip);
1791 chip->dev_index = dev;
1792 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000)
1793 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]);
1794 INIT_LIST_HEAD(&chip->pcm_list);
1795 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1796 INIT_LIST_HEAD(&hda->list);
1797 init_vga_switcheroo(chip);
1798 init_completion(&hda->probe_wait);
1799
1800 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1801
1802 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1803 chip->fallback_to_single_cmd = 1;
1804 else /* explicitly set to single_cmd or not */
1805 chip->single_cmd = single_cmd;
1806
1807 azx_check_snoop_available(chip);
1808
1809 if (bdl_pos_adj[dev] < 0)
1810 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1811 else
1812 chip->bdl_pos_adj = bdl_pos_adj[dev];
1813
1814 err = azx_bus_init(chip, model[dev]);
1815 if (err < 0)
1816 return err;
1817
1818 /* use the non-cached pages in non-snoop mode */
1819 if (!azx_snoop(chip))
1820 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG;
1821
1822 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1823 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1824 chip->bus.core.needs_damn_long_delay = 1;
1825 }
1826
1827 check_probe_mask(chip, dev);
1828
1829 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1830 if (err < 0) {
1831 dev_err(card->dev, "Error creating device [card]!\n");
1832 azx_free(chip);
1833 return err;
1834 }
1835
1836 /* continue probing in work context as may trigger request module */
1837 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work);
1838
1839 *rchip = chip;
1840
1841 return 0;
1842 }
1843
azx_first_init(struct azx * chip)1844 static int azx_first_init(struct azx *chip)
1845 {
1846 int dev = chip->dev_index;
1847 struct pci_dev *pci = chip->pci;
1848 struct snd_card *card = chip->card;
1849 struct hdac_bus *bus = azx_bus(chip);
1850 int err;
1851 unsigned short gcap;
1852 unsigned int dma_bits = 64;
1853
1854 #if BITS_PER_LONG != 64
1855 /* Fix up base address on ULI M5461 */
1856 if (chip->driver_type == AZX_DRIVER_ULI) {
1857 u16 tmp3;
1858 pci_read_config_word(pci, 0x40, &tmp3);
1859 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1860 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1861 }
1862 #endif
1863
1864 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio");
1865 if (err < 0)
1866 return err;
1867
1868 bus->addr = pci_resource_start(pci, 0);
1869 bus->remap_addr = pcim_iomap_table(pci)[0];
1870
1871 if (chip->driver_type == AZX_DRIVER_SKL)
1872 snd_hdac_bus_parse_capabilities(bus);
1873
1874 /*
1875 * Some Intel CPUs has always running timer (ART) feature and
1876 * controller may have Global time sync reporting capability, so
1877 * check both of these before declaring synchronized time reporting
1878 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1879 */
1880 chip->gts_present = false;
1881
1882 #ifdef CONFIG_X86
1883 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1884 chip->gts_present = true;
1885 #endif
1886
1887 if (chip->msi) {
1888 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1889 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1890 pci->no_64bit_msi = true;
1891 }
1892 if (pci_enable_msi(pci) < 0)
1893 chip->msi = 0;
1894 }
1895
1896 pci_set_master(pci);
1897
1898 gcap = azx_readw(chip, GCAP);
1899 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1900
1901 /* AMD devices support 40 or 48bit DMA, take the safe one */
1902 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1903 dma_bits = 40;
1904
1905 /* disable SB600 64bit support for safety */
1906 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1907 struct pci_dev *p_smbus;
1908 dma_bits = 40;
1909 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1910 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1911 NULL);
1912 if (p_smbus) {
1913 if (p_smbus->revision < 0x30)
1914 gcap &= ~AZX_GCAP_64OK;
1915 pci_dev_put(p_smbus);
1916 }
1917 }
1918
1919 /* NVidia hardware normally only supports up to 40 bits of DMA */
1920 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1921 dma_bits = 40;
1922
1923 /* disable 64bit DMA address on some devices */
1924 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1925 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1926 gcap &= ~AZX_GCAP_64OK;
1927 }
1928
1929 /* disable buffer size rounding to 128-byte multiples if supported */
1930 if (align_buffer_size >= 0)
1931 chip->align_buffer_size = !!align_buffer_size;
1932 else {
1933 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1934 chip->align_buffer_size = 0;
1935 else
1936 chip->align_buffer_size = 1;
1937 }
1938
1939 /* allow 64bit DMA address if supported by H/W */
1940 if (!(gcap & AZX_GCAP_64OK))
1941 dma_bits = 32;
1942 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
1943 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
1944 dma_set_max_seg_size(&pci->dev, UINT_MAX);
1945
1946 /* read number of streams from GCAP register instead of using
1947 * hardcoded value
1948 */
1949 chip->capture_streams = (gcap >> 8) & 0x0f;
1950 chip->playback_streams = (gcap >> 12) & 0x0f;
1951 if (!chip->playback_streams && !chip->capture_streams) {
1952 /* gcap didn't give any info, switching to old method */
1953
1954 switch (chip->driver_type) {
1955 case AZX_DRIVER_ULI:
1956 chip->playback_streams = ULI_NUM_PLAYBACK;
1957 chip->capture_streams = ULI_NUM_CAPTURE;
1958 break;
1959 case AZX_DRIVER_ATIHDMI:
1960 case AZX_DRIVER_ATIHDMI_NS:
1961 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1962 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1963 break;
1964 case AZX_DRIVER_GENERIC:
1965 default:
1966 chip->playback_streams = ICH6_NUM_PLAYBACK;
1967 chip->capture_streams = ICH6_NUM_CAPTURE;
1968 break;
1969 }
1970 }
1971 chip->capture_index_offset = 0;
1972 chip->playback_index_offset = chip->capture_streams;
1973 chip->num_streams = chip->playback_streams + chip->capture_streams;
1974
1975 /* sanity check for the SDxCTL.STRM field overflow */
1976 if (chip->num_streams > 15 &&
1977 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1978 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1979 "forcing separate stream tags", chip->num_streams);
1980 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1981 }
1982
1983 /* initialize streams */
1984 err = azx_init_streams(chip);
1985 if (err < 0)
1986 return err;
1987
1988 err = azx_alloc_stream_pages(chip);
1989 if (err < 0)
1990 return err;
1991
1992 /* initialize chip */
1993 azx_init_pci(chip);
1994
1995 snd_hdac_i915_set_bclk(bus);
1996
1997 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1998
1999 /* codec detection */
2000 if (!azx_bus(chip)->codec_mask) {
2001 dev_err(card->dev, "no codecs found!\n");
2002 /* keep running the rest for the runtime PM */
2003 }
2004
2005 if (azx_acquire_irq(chip, 0) < 0)
2006 return -EBUSY;
2007
2008 strcpy(card->driver, "HDA-Intel");
2009 strscpy(card->shortname, driver_short_names[chip->driver_type],
2010 sizeof(card->shortname));
2011 snprintf(card->longname, sizeof(card->longname),
2012 "%s at 0x%lx irq %i",
2013 card->shortname, bus->addr, bus->irq);
2014
2015 return 0;
2016 }
2017
2018 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2019 /* callback from request_firmware_nowait() */
azx_firmware_cb(const struct firmware * fw,void * context)2020 static void azx_firmware_cb(const struct firmware *fw, void *context)
2021 {
2022 struct snd_card *card = context;
2023 struct azx *chip = card->private_data;
2024
2025 if (fw)
2026 chip->fw = fw;
2027 else
2028 dev_err(card->dev, "Cannot load firmware, continue without patching\n");
2029 if (!chip->disabled) {
2030 /* continue probing */
2031 azx_probe_continue(chip);
2032 }
2033 }
2034 #endif
2035
disable_msi_reset_irq(struct azx * chip)2036 static int disable_msi_reset_irq(struct azx *chip)
2037 {
2038 struct hdac_bus *bus = azx_bus(chip);
2039 int err;
2040
2041 free_irq(bus->irq, chip);
2042 bus->irq = -1;
2043 chip->card->sync_irq = -1;
2044 pci_disable_msi(chip->pci);
2045 chip->msi = 0;
2046 err = azx_acquire_irq(chip, 1);
2047 if (err < 0)
2048 return err;
2049
2050 return 0;
2051 }
2052
2053 /* Denylist for skipping the whole probe:
2054 * some HD-audio PCI entries are exposed without any codecs, and such devices
2055 * should be ignored from the beginning.
2056 */
2057 static const struct pci_device_id driver_denylist[] = {
2058 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */
2059 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */
2060 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */
2061 {}
2062 };
2063
2064 static const struct hda_controller_ops pci_hda_ops = {
2065 .disable_msi_reset_irq = disable_msi_reset_irq,
2066 .position_check = azx_position_check,
2067 };
2068
2069 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS);
2070
azx_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2071 static int azx_probe(struct pci_dev *pci,
2072 const struct pci_device_id *pci_id)
2073 {
2074 struct snd_card *card;
2075 struct hda_intel *hda;
2076 struct azx *chip;
2077 bool schedule_probe;
2078 int dev;
2079 int err;
2080
2081 if (pci_match_id(driver_denylist, pci)) {
2082 dev_info(&pci->dev, "Skipping the device on the denylist\n");
2083 return -ENODEV;
2084 }
2085
2086 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS);
2087 if (dev >= SNDRV_CARDS)
2088 return -ENODEV;
2089 if (!enable[dev]) {
2090 set_bit(dev, probed_devs);
2091 return -ENOENT;
2092 }
2093
2094 /*
2095 * stop probe if another Intel's DSP driver should be activated
2096 */
2097 if (dmic_detect) {
2098 err = snd_intel_dsp_driver_probe(pci);
2099 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) {
2100 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n");
2101 return -ENODEV;
2102 }
2103 } else {
2104 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n");
2105 }
2106
2107 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2108 0, &card);
2109 if (err < 0) {
2110 dev_err(&pci->dev, "Error creating card!\n");
2111 return err;
2112 }
2113
2114 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2115 if (err < 0)
2116 goto out_free;
2117 card->private_data = chip;
2118 hda = container_of(chip, struct hda_intel, chip);
2119
2120 pci_set_drvdata(pci, card);
2121
2122 err = register_vga_switcheroo(chip);
2123 if (err < 0) {
2124 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2125 goto out_free;
2126 }
2127
2128 if (check_hdmi_disabled(pci)) {
2129 dev_info(card->dev, "VGA controller is disabled\n");
2130 dev_info(card->dev, "Delaying initialization\n");
2131 chip->disabled = true;
2132 }
2133
2134 schedule_probe = !chip->disabled;
2135
2136 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2137 if (patch[dev] && *patch[dev]) {
2138 dev_info(card->dev, "Applying patch firmware '%s'\n",
2139 patch[dev]);
2140 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2141 &pci->dev, GFP_KERNEL, card,
2142 azx_firmware_cb);
2143 if (err < 0)
2144 goto out_free;
2145 schedule_probe = false; /* continued in azx_firmware_cb() */
2146 }
2147 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2148
2149 #ifndef CONFIG_SND_HDA_I915
2150 if (CONTROLLER_IN_GPU(pci))
2151 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2152 #endif
2153
2154 if (schedule_probe)
2155 schedule_delayed_work(&hda->probe_work, 0);
2156
2157 set_bit(dev, probed_devs);
2158 if (chip->disabled)
2159 complete_all(&hda->probe_wait);
2160 return 0;
2161
2162 out_free:
2163 snd_card_free(card);
2164 return err;
2165 }
2166
2167 #ifdef CONFIG_PM
2168 /* On some boards setting power_save to a non 0 value leads to clicking /
2169 * popping sounds when ever we enter/leave powersaving mode. Ideally we would
2170 * figure out how to avoid these sounds, but that is not always feasible.
2171 * So we keep a list of devices where we disable powersaving as its known
2172 * to causes problems on these devices.
2173 */
2174 static const struct snd_pci_quirk power_save_denylist[] = {
2175 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2176 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0),
2177 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2178 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0),
2179 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2180 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0),
2181 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2182 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0),
2183 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2184 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0),
2185 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2186 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */
2187 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0),
2188 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */
2189 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0),
2190 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */
2191 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0),
2192 /* https://bugs.launchpad.net/bugs/1821663 */
2193 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0),
2194 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */
2195 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
2196 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
2197 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
2198 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
2199 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
2200 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
2201 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0),
2202 /* https://bugs.launchpad.net/bugs/1821663 */
2203 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0),
2204 {}
2205 };
2206 #endif /* CONFIG_PM */
2207
set_default_power_save(struct azx * chip)2208 static void set_default_power_save(struct azx *chip)
2209 {
2210 int val = power_save;
2211
2212 #ifdef CONFIG_PM
2213 if (pm_blacklist) {
2214 const struct snd_pci_quirk *q;
2215
2216 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist);
2217 if (q && val) {
2218 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n",
2219 q->subvendor, q->subdevice);
2220 val = 0;
2221 }
2222 }
2223 #endif /* CONFIG_PM */
2224 snd_hda_set_power_save(&chip->bus, val * 1000);
2225 }
2226
2227 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2228 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2229 [AZX_DRIVER_NVIDIA] = 8,
2230 [AZX_DRIVER_TERA] = 1,
2231 };
2232
azx_probe_continue(struct azx * chip)2233 static int azx_probe_continue(struct azx *chip)
2234 {
2235 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2236 struct hdac_bus *bus = azx_bus(chip);
2237 struct pci_dev *pci = chip->pci;
2238 int dev = chip->dev_index;
2239 int err;
2240
2241 if (chip->disabled || hda->init_failed)
2242 return -EIO;
2243 if (hda->probe_retry)
2244 goto probe_retry;
2245
2246 to_hda_bus(bus)->bus_probing = 1;
2247 hda->probe_continued = 1;
2248
2249 /* bind with i915 if needed */
2250 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) {
2251 err = snd_hdac_i915_init(bus);
2252 if (err < 0) {
2253 /* if the controller is bound only with HDMI/DP
2254 * (for HSW and BDW), we need to abort the probe;
2255 * for other chips, still continue probing as other
2256 * codecs can be on the same link.
2257 */
2258 if (CONTROLLER_IN_GPU(pci)) {
2259 dev_err(chip->card->dev,
2260 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2261 goto out_free;
2262 } else {
2263 /* don't bother any longer */
2264 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;
2265 }
2266 }
2267
2268 /* HSW/BDW controllers need this power */
2269 if (CONTROLLER_IN_GPU(pci))
2270 hda->need_i915_power = true;
2271 }
2272
2273 /* Request display power well for the HDA controller or codec. For
2274 * Haswell/Broadwell, both the display HDA controller and codec need
2275 * this power. For other platforms, like Baytrail/Braswell, only the
2276 * display codec needs the power and it can be released after probe.
2277 */
2278 display_power(chip, true);
2279
2280 err = azx_first_init(chip);
2281 if (err < 0)
2282 goto out_free;
2283
2284 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2285 chip->beep_mode = beep_mode[dev];
2286 #endif
2287
2288 /* create codec instances */
2289 if (bus->codec_mask) {
2290 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2291 if (err < 0)
2292 goto out_free;
2293 }
2294
2295 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2296 if (chip->fw) {
2297 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2298 chip->fw->data);
2299 if (err < 0)
2300 goto out_free;
2301 #ifndef CONFIG_PM
2302 release_firmware(chip->fw); /* no longer needed */
2303 chip->fw = NULL;
2304 #endif
2305 }
2306 #endif
2307
2308 probe_retry:
2309 if (bus->codec_mask && !(probe_only[dev] & 1)) {
2310 err = azx_codec_configure(chip);
2311 if (err) {
2312 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) &&
2313 ++hda->probe_retry < 60) {
2314 schedule_delayed_work(&hda->probe_work,
2315 msecs_to_jiffies(1000));
2316 return 0; /* keep things up */
2317 }
2318 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n");
2319 goto out_free;
2320 }
2321 }
2322
2323 err = snd_card_register(chip->card);
2324 if (err < 0)
2325 goto out_free;
2326
2327 setup_vga_switcheroo_runtime_pm(chip);
2328
2329 chip->running = 1;
2330 azx_add_card_list(chip);
2331
2332 set_default_power_save(chip);
2333
2334 if (azx_has_pm_runtime(chip)) {
2335 pm_runtime_use_autosuspend(&pci->dev);
2336 pm_runtime_allow(&pci->dev);
2337 pm_runtime_put_autosuspend(&pci->dev);
2338 }
2339
2340 out_free:
2341 if (err < 0) {
2342 pci_set_drvdata(pci, NULL);
2343 snd_card_free(chip->card);
2344 return err;
2345 }
2346
2347 if (!hda->need_i915_power)
2348 display_power(chip, false);
2349 complete_all(&hda->probe_wait);
2350 to_hda_bus(bus)->bus_probing = 0;
2351 hda->probe_retry = 0;
2352 return 0;
2353 }
2354
azx_remove(struct pci_dev * pci)2355 static void azx_remove(struct pci_dev *pci)
2356 {
2357 struct snd_card *card = pci_get_drvdata(pci);
2358 struct azx *chip;
2359 struct hda_intel *hda;
2360
2361 if (card) {
2362 /* cancel the pending probing work */
2363 chip = card->private_data;
2364 hda = container_of(chip, struct hda_intel, chip);
2365 /* FIXME: below is an ugly workaround.
2366 * Both device_release_driver() and driver_probe_device()
2367 * take *both* the device's and its parent's lock before
2368 * calling the remove() and probe() callbacks. The codec
2369 * probe takes the locks of both the codec itself and its
2370 * parent, i.e. the PCI controller dev. Meanwhile, when
2371 * the PCI controller is unbound, it takes its lock, too
2372 * ==> ouch, a deadlock!
2373 * As a workaround, we unlock temporarily here the controller
2374 * device during cancel_work_sync() call.
2375 */
2376 device_unlock(&pci->dev);
2377 cancel_delayed_work_sync(&hda->probe_work);
2378 device_lock(&pci->dev);
2379
2380 clear_bit(chip->dev_index, probed_devs);
2381 pci_set_drvdata(pci, NULL);
2382 snd_card_free(card);
2383 }
2384 }
2385
azx_shutdown(struct pci_dev * pci)2386 static void azx_shutdown(struct pci_dev *pci)
2387 {
2388 struct snd_card *card = pci_get_drvdata(pci);
2389 struct azx *chip;
2390
2391 if (!card)
2392 return;
2393 chip = card->private_data;
2394 if (chip && chip->running)
2395 __azx_shutdown_chip(chip, true);
2396 }
2397
2398 /* PCI IDs */
2399 static const struct pci_device_id azx_ids[] = {
2400 /* CPT */
2401 { PCI_DEVICE(0x8086, 0x1c20),
2402 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2403 /* PBG */
2404 { PCI_DEVICE(0x8086, 0x1d20),
2405 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2406 /* Panther Point */
2407 { PCI_DEVICE(0x8086, 0x1e20),
2408 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2409 /* Lynx Point */
2410 { PCI_DEVICE(0x8086, 0x8c20),
2411 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2412 /* 9 Series */
2413 { PCI_DEVICE(0x8086, 0x8ca0),
2414 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2415 /* Wellsburg */
2416 { PCI_DEVICE(0x8086, 0x8d20),
2417 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2418 { PCI_DEVICE(0x8086, 0x8d21),
2419 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2420 /* Lewisburg */
2421 { PCI_DEVICE(0x8086, 0xa1f0),
2422 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2423 { PCI_DEVICE(0x8086, 0xa270),
2424 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2425 /* Lynx Point-LP */
2426 { PCI_DEVICE(0x8086, 0x9c20),
2427 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2428 /* Lynx Point-LP */
2429 { PCI_DEVICE(0x8086, 0x9c21),
2430 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2431 /* Wildcat Point-LP */
2432 { PCI_DEVICE(0x8086, 0x9ca0),
2433 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2434 /* Sunrise Point */
2435 { PCI_DEVICE(0x8086, 0xa170),
2436 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2437 /* Sunrise Point-LP */
2438 { PCI_DEVICE(0x8086, 0x9d70),
2439 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2440 /* Kabylake */
2441 { PCI_DEVICE(0x8086, 0xa171),
2442 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2443 /* Kabylake-LP */
2444 { PCI_DEVICE(0x8086, 0x9d71),
2445 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2446 /* Kabylake-H */
2447 { PCI_DEVICE(0x8086, 0xa2f0),
2448 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE },
2449 /* Coffelake */
2450 { PCI_DEVICE(0x8086, 0xa348),
2451 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2452 /* Cannonlake */
2453 { PCI_DEVICE(0x8086, 0x9dc8),
2454 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2455 /* CometLake-LP */
2456 { PCI_DEVICE(0x8086, 0x02C8),
2457 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2458 /* CometLake-H */
2459 { PCI_DEVICE(0x8086, 0x06C8),
2460 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2461 { PCI_DEVICE(0x8086, 0xf1c8),
2462 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2463 /* CometLake-S */
2464 { PCI_DEVICE(0x8086, 0xa3f0),
2465 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2466 /* CometLake-R */
2467 { PCI_DEVICE(0x8086, 0xf0c8),
2468 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2469 /* Icelake */
2470 { PCI_DEVICE(0x8086, 0x34c8),
2471 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2472 /* Icelake-H */
2473 { PCI_DEVICE(0x8086, 0x3dc8),
2474 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2475 /* Jasperlake */
2476 { PCI_DEVICE(0x8086, 0x38c8),
2477 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2478 { PCI_DEVICE(0x8086, 0x4dc8),
2479 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2480 /* Tigerlake */
2481 { PCI_DEVICE(0x8086, 0xa0c8),
2482 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2483 /* Tigerlake-H */
2484 { PCI_DEVICE(0x8086, 0x43c8),
2485 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2486 /* DG1 */
2487 { PCI_DEVICE(0x8086, 0x490d),
2488 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2489 /* DG2 */
2490 { PCI_DEVICE(0x8086, 0x4f90),
2491 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2492 { PCI_DEVICE(0x8086, 0x4f91),
2493 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2494 { PCI_DEVICE(0x8086, 0x4f92),
2495 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2496 /* Alderlake-S */
2497 { PCI_DEVICE(0x8086, 0x7ad0),
2498 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2499 /* Alderlake-P */
2500 { PCI_DEVICE(0x8086, 0x51c8),
2501 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2502 { PCI_DEVICE(0x8086, 0x51c9),
2503 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2504 { PCI_DEVICE(0x8086, 0x51cd),
2505 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2506 /* Alderlake-M */
2507 { PCI_DEVICE(0x8086, 0x51cc),
2508 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2509 /* Alderlake-N */
2510 { PCI_DEVICE(0x8086, 0x54c8),
2511 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2512 /* Elkhart Lake */
2513 { PCI_DEVICE(0x8086, 0x4b55),
2514 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2515 { PCI_DEVICE(0x8086, 0x4b58),
2516 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2517 /* Raptor Lake */
2518 { PCI_DEVICE(0x8086, 0x7a50),
2519 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2520 { PCI_DEVICE(0x8086, 0x51ca),
2521 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2522 { PCI_DEVICE(0x8086, 0x51cb),
2523 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2524 { PCI_DEVICE(0x8086, 0x51ce),
2525 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2526 { PCI_DEVICE(0x8086, 0x51cf),
2527 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2528 /* Meteorlake-P */
2529 { PCI_DEVICE(0x8086, 0x7e28),
2530 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE},
2531 /* Broxton-P(Apollolake) */
2532 { PCI_DEVICE(0x8086, 0x5a98),
2533 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2534 /* Broxton-T */
2535 { PCI_DEVICE(0x8086, 0x1a98),
2536 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2537 /* Gemini-Lake */
2538 { PCI_DEVICE(0x8086, 0x3198),
2539 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON },
2540 /* Haswell */
2541 { PCI_DEVICE(0x8086, 0x0a0c),
2542 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2543 { PCI_DEVICE(0x8086, 0x0c0c),
2544 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2545 { PCI_DEVICE(0x8086, 0x0d0c),
2546 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2547 /* Broadwell */
2548 { PCI_DEVICE(0x8086, 0x160c),
2549 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2550 /* 5 Series/3400 */
2551 { PCI_DEVICE(0x8086, 0x3b56),
2552 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2553 /* Poulsbo */
2554 { PCI_DEVICE(0x8086, 0x811b),
2555 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2556 /* Oaktrail */
2557 { PCI_DEVICE(0x8086, 0x080a),
2558 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2559 /* BayTrail */
2560 { PCI_DEVICE(0x8086, 0x0f04),
2561 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2562 /* Braswell */
2563 { PCI_DEVICE(0x8086, 0x2284),
2564 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2565 /* ICH6 */
2566 { PCI_DEVICE(0x8086, 0x2668),
2567 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2568 /* ICH7 */
2569 { PCI_DEVICE(0x8086, 0x27d8),
2570 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2571 /* ESB2 */
2572 { PCI_DEVICE(0x8086, 0x269a),
2573 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2574 /* ICH8 */
2575 { PCI_DEVICE(0x8086, 0x284b),
2576 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2577 /* ICH9 */
2578 { PCI_DEVICE(0x8086, 0x293e),
2579 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2580 /* ICH9 */
2581 { PCI_DEVICE(0x8086, 0x293f),
2582 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2583 /* ICH10 */
2584 { PCI_DEVICE(0x8086, 0x3a3e),
2585 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2586 /* ICH10 */
2587 { PCI_DEVICE(0x8086, 0x3a6e),
2588 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2589 /* Generic Intel */
2590 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2591 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2592 .class_mask = 0xffffff,
2593 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2594 /* ATI SB 450/600/700/800/900 */
2595 { PCI_DEVICE(0x1002, 0x437b),
2596 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2597 { PCI_DEVICE(0x1002, 0x4383),
2598 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2599 /* AMD Hudson */
2600 { PCI_DEVICE(0x1022, 0x780d),
2601 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2602 /* AMD, X370 & co */
2603 { PCI_DEVICE(0x1022, 0x1457),
2604 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2605 /* AMD, X570 & co */
2606 { PCI_DEVICE(0x1022, 0x1487),
2607 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2608 /* AMD Stoney */
2609 { PCI_DEVICE(0x1022, 0x157a),
2610 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB |
2611 AZX_DCAPS_PM_RUNTIME },
2612 /* AMD Raven */
2613 { PCI_DEVICE(0x1022, 0x15e3),
2614 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB },
2615 /* ATI HDMI */
2616 { PCI_DEVICE(0x1002, 0x0002),
2617 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2618 AZX_DCAPS_PM_RUNTIME },
2619 { PCI_DEVICE(0x1002, 0x1308),
2620 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2621 { PCI_DEVICE(0x1002, 0x157a),
2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2623 { PCI_DEVICE(0x1002, 0x15b3),
2624 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2625 { PCI_DEVICE(0x1002, 0x793b),
2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2627 { PCI_DEVICE(0x1002, 0x7919),
2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2629 { PCI_DEVICE(0x1002, 0x960f),
2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2631 { PCI_DEVICE(0x1002, 0x970f),
2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2633 { PCI_DEVICE(0x1002, 0x9840),
2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2635 { PCI_DEVICE(0x1002, 0xaa00),
2636 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2637 { PCI_DEVICE(0x1002, 0xaa08),
2638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2639 { PCI_DEVICE(0x1002, 0xaa10),
2640 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2641 { PCI_DEVICE(0x1002, 0xaa18),
2642 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2643 { PCI_DEVICE(0x1002, 0xaa20),
2644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2645 { PCI_DEVICE(0x1002, 0xaa28),
2646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2647 { PCI_DEVICE(0x1002, 0xaa30),
2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2649 { PCI_DEVICE(0x1002, 0xaa38),
2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2651 { PCI_DEVICE(0x1002, 0xaa40),
2652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2653 { PCI_DEVICE(0x1002, 0xaa48),
2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2655 { PCI_DEVICE(0x1002, 0xaa50),
2656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2657 { PCI_DEVICE(0x1002, 0xaa58),
2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2659 { PCI_DEVICE(0x1002, 0xaa60),
2660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2661 { PCI_DEVICE(0x1002, 0xaa68),
2662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2663 { PCI_DEVICE(0x1002, 0xaa80),
2664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2665 { PCI_DEVICE(0x1002, 0xaa88),
2666 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2667 { PCI_DEVICE(0x1002, 0xaa90),
2668 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2669 { PCI_DEVICE(0x1002, 0xaa98),
2670 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2671 { PCI_DEVICE(0x1002, 0x9902),
2672 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2673 { PCI_DEVICE(0x1002, 0xaaa0),
2674 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2675 { PCI_DEVICE(0x1002, 0xaaa8),
2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2677 { PCI_DEVICE(0x1002, 0xaab0),
2678 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2679 { PCI_DEVICE(0x1002, 0xaac0),
2680 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2681 AZX_DCAPS_PM_RUNTIME },
2682 { PCI_DEVICE(0x1002, 0xaac8),
2683 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2684 AZX_DCAPS_PM_RUNTIME },
2685 { PCI_DEVICE(0x1002, 0xaad8),
2686 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2687 AZX_DCAPS_PM_RUNTIME },
2688 { PCI_DEVICE(0x1002, 0xaae0),
2689 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2690 AZX_DCAPS_PM_RUNTIME },
2691 { PCI_DEVICE(0x1002, 0xaae8),
2692 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2693 AZX_DCAPS_PM_RUNTIME },
2694 { PCI_DEVICE(0x1002, 0xaaf0),
2695 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2696 AZX_DCAPS_PM_RUNTIME },
2697 { PCI_DEVICE(0x1002, 0xaaf8),
2698 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2699 AZX_DCAPS_PM_RUNTIME },
2700 { PCI_DEVICE(0x1002, 0xab00),
2701 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2702 AZX_DCAPS_PM_RUNTIME },
2703 { PCI_DEVICE(0x1002, 0xab08),
2704 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2705 AZX_DCAPS_PM_RUNTIME },
2706 { PCI_DEVICE(0x1002, 0xab10),
2707 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2708 AZX_DCAPS_PM_RUNTIME },
2709 { PCI_DEVICE(0x1002, 0xab18),
2710 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2711 AZX_DCAPS_PM_RUNTIME },
2712 { PCI_DEVICE(0x1002, 0xab20),
2713 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2714 AZX_DCAPS_PM_RUNTIME },
2715 { PCI_DEVICE(0x1002, 0xab28),
2716 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2717 AZX_DCAPS_PM_RUNTIME },
2718 { PCI_DEVICE(0x1002, 0xab38),
2719 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS |
2720 AZX_DCAPS_PM_RUNTIME },
2721 /* VIA VT8251/VT8237A */
2722 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2723 /* VIA GFX VT7122/VX900 */
2724 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2725 /* VIA GFX VT6122/VX11 */
2726 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2727 /* SIS966 */
2728 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2729 /* ULI M5461 */
2730 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2731 /* NVIDIA MCP */
2732 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2733 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2734 .class_mask = 0xffffff,
2735 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2736 /* Teradici */
2737 { PCI_DEVICE(0x6549, 0x1200),
2738 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2739 { PCI_DEVICE(0x6549, 0x2200),
2740 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2741 /* Creative X-Fi (CA0110-IBG) */
2742 /* CTHDA chips */
2743 { PCI_DEVICE(0x1102, 0x0010),
2744 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2745 { PCI_DEVICE(0x1102, 0x0012),
2746 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2747 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2748 /* the following entry conflicts with snd-ctxfi driver,
2749 * as ctxfi driver mutates from HD-audio to native mode with
2750 * a special command sequence.
2751 */
2752 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2753 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2754 .class_mask = 0xffffff,
2755 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2756 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2757 #else
2758 /* this entry seems still valid -- i.e. without emu20kx chip */
2759 { PCI_DEVICE(0x1102, 0x0009),
2760 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2761 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2762 #endif
2763 /* CM8888 */
2764 { PCI_DEVICE(0x13f6, 0x5011),
2765 .driver_data = AZX_DRIVER_CMEDIA |
2766 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2767 /* Vortex86MX */
2768 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2769 /* VMware HDAudio */
2770 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2771 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2772 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2773 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2774 .class_mask = 0xffffff,
2775 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2776 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2777 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2778 .class_mask = 0xffffff,
2779 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2780 /* Zhaoxin */
2781 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN },
2782 { 0, }
2783 };
2784 MODULE_DEVICE_TABLE(pci, azx_ids);
2785
2786 /* pci_driver definition */
2787 static struct pci_driver azx_driver = {
2788 .name = KBUILD_MODNAME,
2789 .id_table = azx_ids,
2790 .probe = azx_probe,
2791 .remove = azx_remove,
2792 .shutdown = azx_shutdown,
2793 .driver = {
2794 .pm = AZX_PM_OPS,
2795 },
2796 };
2797
2798 module_pci_driver(azx_driver);
2799