1 /* megafunction wizard: %ARM-Based Excalibur% 2 GENERATION: STANDARD 3 VERSION: WM1.0 4 MODULE: ARM-Based Excalibur 5 PROJECT: excalibur 6 ============================================================ 7 File Name: v:\embedded\linux\bootldr\excalibur.h 8 Megafunction Name(s): ARM-Based Excalibur 9 ============================================================ 10 11 ************************************************************ 12 THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 13 ************************************************************/ 14 15 #ifndef EXCALIBUR_H_INCLUDED 16 #define EXCALIBUR_H_INCLUDED 17 18 #define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN 19 #define EXC_DEFINE_BOOT_FROM_FLASH 20 21 #define EXC_INPUT_CLK_FREQUENCY (50000000) 22 #define EXC_AHB1_CLK_FREQUENCY (150000000) 23 #define EXC_AHB2_CLK_FREQUENCY (75000000) 24 #define EXC_SDRAM_CLK_FREQUENCY (75000000) 25 26 /* Registers Block */ 27 #define EXC_REGISTERS_BASE (0x7fffc000) 28 #define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000) 29 #define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040) 30 #define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080) 31 #define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140) 32 #define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200) 33 #define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00) 34 #define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300) 35 #define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00) 36 #define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280) 37 #define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380) 38 #define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400) 39 #define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800) 40 #define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100) 41 #define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100) 42 43 #define EXC_REGISTERS_SIZE (0x00004000) 44 45 /* EBI Block(s) */ 46 #define EXC_EBI_BLOCK0_BASE (0x40000000) 47 #define EXC_EBI_BLOCK0_SIZE (0x00400000) 48 #define EXC_EBI_BLOCK0_WIDTH (8) 49 #define EXC_EBI_BLOCK0_NON_CACHEABLE 50 #define EXC_EBI_BLOCK1_BASE (0x40400000) 51 #define EXC_EBI_BLOCK1_SIZE (0x00400000) 52 #define EXC_EBI_BLOCK1_WIDTH (16) 53 #define EXC_EBI_BLOCK1_NON_CACHEABLE 54 #define EXC_EBI_BLOCK2_BASE (0x40800000) 55 #define EXC_EBI_BLOCK2_SIZE (0x00400000) 56 #define EXC_EBI_BLOCK2_WIDTH (16) 57 #define EXC_EBI_BLOCK2_NON_CACHEABLE 58 #define EXC_EBI_BLOCK3_BASE (0x40c00000) 59 #define EXC_EBI_BLOCK3_SIZE (0x00400000) 60 #define EXC_EBI_BLOCK3_WIDTH (16) 61 #define EXC_EBI_BLOCK3_NON_CACHEABLE 62 63 /* SDRAM Block(s) */ 64 #define EXC_SDRAM_BLOCK0_BASE (0x00000000) 65 #define EXC_SDRAM_BLOCK0_SIZE (0x04000000) 66 #define EXC_SDRAM_BLOCK0_WIDTH (32) 67 #define EXC_SDRAM_BLOCK1_BASE (0x04000000) 68 #define EXC_SDRAM_BLOCK1_SIZE (0x04000000) 69 #define EXC_SDRAM_BLOCK1_WIDTH (32) 70 71 /* Single Port SRAM Block(s) */ 72 #define EXC_SPSRAM_BLOCK0_BASE (0x20000000) 73 #define EXC_SPSRAM_BLOCK0_SIZE (0x00020000) 74 #define EXC_SPSRAM_BLOCK1_BASE (0x20020000) 75 #define EXC_SPSRAM_BLOCK1_SIZE (0x00020000) 76 77 /* PLD Block(s) */ 78 #define EXC_PLD_BLOCK0_BASE (0x80000000) 79 #define EXC_PLD_BLOCK0_SIZE (0x80000000) 80 #define EXC_PLD_BLOCK0_NON_CACHEABLE 81 #define EXC_PLD_BLOCK1_BASE (0x60000000) 82 #define EXC_PLD_BLOCK1_SIZE (0x10000000) 83 #define EXC_PLD_BLOCK1_NON_CACHEABLE 84 85 #endif 86