1 /*
2  * Copyright (c) 2018, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 #ifndef __MLX5_EN_XDP_H__
33 #define __MLX5_EN_XDP_H__
34 
35 #include <linux/indirect_call_wrapper.h>
36 
37 #include "en.h"
38 #include "en/txrx.h"
39 
40 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
41 
42 #define MLX5E_XDP_INLINE_WQE_MAX_DS_CNT 16
43 #define MLX5E_XDP_INLINE_WQE_SZ_THRSD \
44 	(MLX5E_XDP_INLINE_WQE_MAX_DS_CNT * MLX5_SEND_WQE_DS - \
45 	 sizeof(struct mlx5_wqe_inline_seg))
46 
47 struct mlx5e_xsk_param;
48 int mlx5e_xdp_max_mtu(struct mlx5e_params *params, struct mlx5e_xsk_param *xsk);
49 bool mlx5e_xdp_handle(struct mlx5e_rq *rq, struct page *page,
50 		      struct bpf_prog *prog, struct xdp_buff *xdp);
51 void mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq *sq);
52 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq);
53 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq);
54 void mlx5e_set_xmit_fp(struct mlx5e_xdpsq *sq, bool is_mpw);
55 void mlx5e_xdp_rx_poll_complete(struct mlx5e_rq *rq);
56 int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
57 		   u32 flags);
58 
59 INDIRECT_CALLABLE_DECLARE(bool mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq,
60 							  struct mlx5e_xmit_data *xdptxd,
61 							  struct skb_shared_info *sinfo,
62 							  int check_result));
63 INDIRECT_CALLABLE_DECLARE(bool mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq,
64 						    struct mlx5e_xmit_data *xdptxd,
65 						    struct skb_shared_info *sinfo,
66 						    int check_result));
67 INDIRECT_CALLABLE_DECLARE(int mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq *sq));
68 INDIRECT_CALLABLE_DECLARE(int mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq *sq));
69 
mlx5e_xdp_tx_enable(struct mlx5e_priv * priv)70 static inline void mlx5e_xdp_tx_enable(struct mlx5e_priv *priv)
71 {
72 	set_bit(MLX5E_STATE_XDP_TX_ENABLED, &priv->state);
73 
74 	if (priv->channels.params.xdp_prog)
75 		set_bit(MLX5E_STATE_XDP_ACTIVE, &priv->state);
76 }
77 
mlx5e_xdp_tx_disable(struct mlx5e_priv * priv)78 static inline void mlx5e_xdp_tx_disable(struct mlx5e_priv *priv)
79 {
80 	if (priv->channels.params.xdp_prog)
81 		clear_bit(MLX5E_STATE_XDP_ACTIVE, &priv->state);
82 
83 	clear_bit(MLX5E_STATE_XDP_TX_ENABLED, &priv->state);
84 	/* Let other device's napi(s) and XSK wakeups see our new state. */
85 	synchronize_net();
86 }
87 
mlx5e_xdp_tx_is_enabled(struct mlx5e_priv * priv)88 static inline bool mlx5e_xdp_tx_is_enabled(struct mlx5e_priv *priv)
89 {
90 	return test_bit(MLX5E_STATE_XDP_TX_ENABLED, &priv->state);
91 }
92 
mlx5e_xdp_is_active(struct mlx5e_priv * priv)93 static inline bool mlx5e_xdp_is_active(struct mlx5e_priv *priv)
94 {
95 	return test_bit(MLX5E_STATE_XDP_ACTIVE, &priv->state);
96 }
97 
mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq * sq)98 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
99 {
100 	if (sq->doorbell_cseg) {
101 		mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
102 		sq->doorbell_cseg = NULL;
103 	}
104 }
105 
106 /* Enable inline WQEs to shift some load from a congested HCA (HW) to
107  * a less congested cpu (SW).
108  */
mlx5e_xdp_get_inline_state(struct mlx5e_xdpsq * sq,bool cur)109 static inline bool mlx5e_xdp_get_inline_state(struct mlx5e_xdpsq *sq, bool cur)
110 {
111 	u16 outstanding = sq->xdpi_fifo_pc - sq->xdpi_fifo_cc;
112 
113 #define MLX5E_XDP_INLINE_WATERMARK_LOW	10
114 #define MLX5E_XDP_INLINE_WATERMARK_HIGH 128
115 
116 	if (cur && outstanding <= MLX5E_XDP_INLINE_WATERMARK_LOW)
117 		return false;
118 
119 	if (!cur && outstanding >= MLX5E_XDP_INLINE_WATERMARK_HIGH)
120 		return true;
121 
122 	return cur;
123 }
124 
mlx5e_xdp_mpwqe_is_full(struct mlx5e_tx_mpwqe * session,u8 max_sq_mpw_wqebbs)125 static inline bool mlx5e_xdp_mpwqe_is_full(struct mlx5e_tx_mpwqe *session, u8 max_sq_mpw_wqebbs)
126 {
127 	if (session->inline_on)
128 		return session->ds_count + MLX5E_XDP_INLINE_WQE_MAX_DS_CNT >
129 		       max_sq_mpw_wqebbs * MLX5_SEND_WQEBB_NUM_DS;
130 
131 	return mlx5e_tx_mpwqe_is_full(session, max_sq_mpw_wqebbs);
132 }
133 
134 struct mlx5e_xdp_wqe_info {
135 	u8 num_wqebbs;
136 	u8 num_pkts;
137 };
138 
139 static inline void
mlx5e_xdp_mpwqe_add_dseg(struct mlx5e_xdpsq * sq,struct mlx5e_xmit_data * xdptxd,struct mlx5e_xdpsq_stats * stats)140 mlx5e_xdp_mpwqe_add_dseg(struct mlx5e_xdpsq *sq,
141 			 struct mlx5e_xmit_data *xdptxd,
142 			 struct mlx5e_xdpsq_stats *stats)
143 {
144 	struct mlx5e_tx_mpwqe *session = &sq->mpwqe;
145 	struct mlx5_wqe_data_seg *dseg =
146 		(struct mlx5_wqe_data_seg *)session->wqe + session->ds_count;
147 	u32 dma_len = xdptxd->len;
148 
149 	session->pkt_count++;
150 	session->bytes_count += dma_len;
151 
152 	if (session->inline_on && dma_len <= MLX5E_XDP_INLINE_WQE_SZ_THRSD) {
153 		struct mlx5_wqe_inline_seg *inline_dseg =
154 			(struct mlx5_wqe_inline_seg *)dseg;
155 		u16 ds_len = sizeof(*inline_dseg) + dma_len;
156 		u16 ds_cnt = DIV_ROUND_UP(ds_len, MLX5_SEND_WQE_DS);
157 
158 		inline_dseg->byte_count = cpu_to_be32(dma_len | MLX5_INLINE_SEG);
159 		memcpy(inline_dseg->data, xdptxd->data, dma_len);
160 
161 		session->ds_count += ds_cnt;
162 		stats->inlnw++;
163 		return;
164 	}
165 
166 	dseg->addr       = cpu_to_be64(xdptxd->dma_addr);
167 	dseg->byte_count = cpu_to_be32(dma_len);
168 	dseg->lkey       = sq->mkey_be;
169 	session->ds_count++;
170 }
171 
172 static inline void
mlx5e_xdpi_fifo_push(struct mlx5e_xdp_info_fifo * fifo,struct mlx5e_xdp_info * xi)173 mlx5e_xdpi_fifo_push(struct mlx5e_xdp_info_fifo *fifo,
174 		     struct mlx5e_xdp_info *xi)
175 {
176 	u32 i = (*fifo->pc)++ & fifo->mask;
177 
178 	fifo->xi[i] = *xi;
179 }
180 
181 static inline struct mlx5e_xdp_info
mlx5e_xdpi_fifo_pop(struct mlx5e_xdp_info_fifo * fifo)182 mlx5e_xdpi_fifo_pop(struct mlx5e_xdp_info_fifo *fifo)
183 {
184 	return fifo->xi[(*fifo->cc)++ & fifo->mask];
185 }
186 #endif
187