1 /*
2 * Copyright (c) 2001 by David Brownell
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19 /* this file is part of ehci-hcd.c */
20
21 /*-------------------------------------------------------------------------*/
22
23 /*
24 * There's basically three types of memory:
25 * - data used only by the HCD ... kmalloc is fine
26 * - async and periodic schedules, shared by HC and HCD ... these
27 * need to use dma_pool or dma_alloc_coherent
28 * - driver buffers, read/written by HC ... single shot DMA mapped
29 *
30 * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
31 * No memory seen by this driver is pageable.
32 */
33
34 /*-------------------------------------------------------------------------*/
35
36 /* Allocate the key transfer structures from the previously allocated pool */
37
ehci_qtd_init(struct ehci_hcd * ehci,struct ehci_qtd * qtd,dma_addr_t dma)38 static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
39 dma_addr_t dma)
40 {
41 memset (qtd, 0, sizeof *qtd);
42 qtd->qtd_dma = dma;
43 qtd->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
44 qtd->hw_next = EHCI_LIST_END(ehci);
45 qtd->hw_alt_next = EHCI_LIST_END(ehci);
46 INIT_LIST_HEAD (&qtd->qtd_list);
47 }
48
ehci_qtd_alloc(struct ehci_hcd * ehci,gfp_t flags)49 static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
50 {
51 struct ehci_qtd *qtd;
52 dma_addr_t dma;
53
54 qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
55 if (qtd != NULL) {
56 ehci_qtd_init(ehci, qtd, dma);
57 }
58 return qtd;
59 }
60
ehci_qtd_free(struct ehci_hcd * ehci,struct ehci_qtd * qtd)61 static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
62 {
63 dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
64 }
65
66
qh_destroy(struct ehci_qh * qh)67 static void qh_destroy(struct ehci_qh *qh)
68 {
69 struct ehci_hcd *ehci = qh->ehci;
70
71 /* clean qtds first, and know this is not linked */
72 if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
73 ehci_dbg (ehci, "unused qh not empty!\n");
74 BUG ();
75 }
76 if (qh->dummy)
77 ehci_qtd_free (ehci, qh->dummy);
78 dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
79 kfree(qh);
80 }
81
ehci_qh_alloc(struct ehci_hcd * ehci,gfp_t flags)82 static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
83 {
84 struct ehci_qh *qh;
85 dma_addr_t dma;
86
87 qh = kzalloc(sizeof *qh, GFP_ATOMIC);
88 if (!qh)
89 goto done;
90 qh->hw = (struct ehci_qh_hw *)
91 dma_pool_alloc(ehci->qh_pool, flags, &dma);
92 if (!qh->hw)
93 goto fail;
94 memset(qh->hw, 0, sizeof *qh->hw);
95 qh->refcount = 1;
96 qh->ehci = ehci;
97 qh->qh_dma = dma;
98 // INIT_LIST_HEAD (&qh->qh_list);
99 INIT_LIST_HEAD (&qh->qtd_list);
100
101 /* dummy td enables safe urb queuing */
102 qh->dummy = ehci_qtd_alloc (ehci, flags);
103 if (qh->dummy == NULL) {
104 ehci_dbg (ehci, "no dummy td\n");
105 goto fail1;
106 }
107 done:
108 return qh;
109 fail1:
110 dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
111 fail:
112 kfree(qh);
113 return NULL;
114 }
115
116 /* to share a qh (cpu threads, or hc) */
qh_get(struct ehci_qh * qh)117 static inline struct ehci_qh *qh_get (struct ehci_qh *qh)
118 {
119 WARN_ON(!qh->refcount);
120 qh->refcount++;
121 return qh;
122 }
123
qh_put(struct ehci_qh * qh)124 static inline void qh_put (struct ehci_qh *qh)
125 {
126 if (!--qh->refcount)
127 qh_destroy(qh);
128 }
129
130 /*-------------------------------------------------------------------------*/
131
132 /* The queue heads and transfer descriptors are managed from pools tied
133 * to each of the "per device" structures.
134 * This is the initialisation and cleanup code.
135 */
136
ehci_mem_cleanup(struct ehci_hcd * ehci)137 static void ehci_mem_cleanup (struct ehci_hcd *ehci)
138 {
139 free_cached_lists(ehci);
140 if (ehci->async)
141 qh_put (ehci->async);
142 ehci->async = NULL;
143
144 if (ehci->dummy)
145 qh_put(ehci->dummy);
146 ehci->dummy = NULL;
147
148 /* DMA consistent memory and pools */
149 if (ehci->qtd_pool)
150 dma_pool_destroy (ehci->qtd_pool);
151 ehci->qtd_pool = NULL;
152
153 if (ehci->qh_pool) {
154 dma_pool_destroy (ehci->qh_pool);
155 ehci->qh_pool = NULL;
156 }
157
158 if (ehci->itd_pool)
159 dma_pool_destroy (ehci->itd_pool);
160 ehci->itd_pool = NULL;
161
162 if (ehci->sitd_pool)
163 dma_pool_destroy (ehci->sitd_pool);
164 ehci->sitd_pool = NULL;
165
166 if (ehci->periodic)
167 dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
168 ehci->periodic_size * sizeof (u32),
169 ehci->periodic, ehci->periodic_dma);
170 ehci->periodic = NULL;
171
172 /* shadow periodic table */
173 kfree(ehci->pshadow);
174 ehci->pshadow = NULL;
175 }
176
177 /* remember to add cleanup code (above) if you add anything here */
ehci_mem_init(struct ehci_hcd * ehci,gfp_t flags)178 static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
179 {
180 int i;
181
182 /* QTDs for control/bulk/intr transfers */
183 ehci->qtd_pool = dma_pool_create ("ehci_qtd",
184 ehci_to_hcd(ehci)->self.controller,
185 sizeof (struct ehci_qtd),
186 32 /* byte alignment (for hw parts) */,
187 4096 /* can't cross 4K */);
188 if (!ehci->qtd_pool) {
189 goto fail;
190 }
191
192 /* QHs for control/bulk/intr transfers */
193 ehci->qh_pool = dma_pool_create ("ehci_qh",
194 ehci_to_hcd(ehci)->self.controller,
195 sizeof(struct ehci_qh_hw),
196 32 /* byte alignment (for hw parts) */,
197 4096 /* can't cross 4K */);
198 if (!ehci->qh_pool) {
199 goto fail;
200 }
201 ehci->async = ehci_qh_alloc (ehci, flags);
202 if (!ehci->async) {
203 goto fail;
204 }
205
206 /* ITD for high speed ISO transfers */
207 ehci->itd_pool = dma_pool_create ("ehci_itd",
208 ehci_to_hcd(ehci)->self.controller,
209 sizeof (struct ehci_itd),
210 32 /* byte alignment (for hw parts) */,
211 4096 /* can't cross 4K */);
212 if (!ehci->itd_pool) {
213 goto fail;
214 }
215
216 /* SITD for full/low speed split ISO transfers */
217 ehci->sitd_pool = dma_pool_create ("ehci_sitd",
218 ehci_to_hcd(ehci)->self.controller,
219 sizeof (struct ehci_sitd),
220 32 /* byte alignment (for hw parts) */,
221 4096 /* can't cross 4K */);
222 if (!ehci->sitd_pool) {
223 goto fail;
224 }
225
226 /* Hardware periodic table */
227 ehci->periodic = (__le32 *)
228 dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
229 ehci->periodic_size * sizeof(__le32),
230 &ehci->periodic_dma, 0);
231 if (ehci->periodic == NULL) {
232 goto fail;
233 }
234
235 if (ehci->use_dummy_qh) {
236 struct ehci_qh_hw *hw;
237 ehci->dummy = ehci_qh_alloc(ehci, flags);
238 if (!ehci->dummy)
239 goto fail;
240
241 hw = ehci->dummy->hw;
242 hw->hw_next = EHCI_LIST_END(ehci);
243 hw->hw_qtd_next = EHCI_LIST_END(ehci);
244 hw->hw_alt_next = EHCI_LIST_END(ehci);
245 hw->hw_token &= ~QTD_STS_ACTIVE;
246 ehci->dummy->hw = hw;
247
248 for (i = 0; i < ehci->periodic_size; i++)
249 ehci->periodic[i] = ehci->dummy->qh_dma;
250 } else {
251 for (i = 0; i < ehci->periodic_size; i++)
252 ehci->periodic[i] = EHCI_LIST_END(ehci);
253 }
254
255 /* software shadow of hardware table */
256 ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
257 if (ehci->pshadow != NULL)
258 return 0;
259
260 fail:
261 ehci_dbg (ehci, "couldn't init memory\n");
262 ehci_mem_cleanup (ehci);
263 return -ENOMEM;
264 }
265