1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
2  *
3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * Copyright 2014 Advanced Micro Devices, Inc.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24  * OTHER DEALINGS IN THE SOFTWARE.
25  *
26  * Authors:
27  *    Kevin E. Martin <martin@valinux.com>
28  *    Gareth Hughes <gareth@valinux.com>
29  *    Keith Whitwell <keith@tungstengraphics.com>
30  */
31 
32 #ifndef __AMDGPU_DRM_H__
33 #define __AMDGPU_DRM_H__
34 
35 #include "drm.h"
36 
37 #if defined(__cplusplus)
38 extern "C" {
39 #endif
40 
41 #define DRM_AMDGPU_GEM_CREATE		0x00
42 #define DRM_AMDGPU_GEM_MMAP		0x01
43 #define DRM_AMDGPU_CTX			0x02
44 #define DRM_AMDGPU_BO_LIST		0x03
45 #define DRM_AMDGPU_CS			0x04
46 #define DRM_AMDGPU_INFO			0x05
47 #define DRM_AMDGPU_GEM_METADATA		0x06
48 #define DRM_AMDGPU_GEM_WAIT_IDLE	0x07
49 #define DRM_AMDGPU_GEM_VA		0x08
50 #define DRM_AMDGPU_WAIT_CS		0x09
51 #define DRM_AMDGPU_GEM_OP		0x10
52 #define DRM_AMDGPU_GEM_USERPTR		0x11
53 #define DRM_AMDGPU_WAIT_FENCES		0x12
54 #define DRM_AMDGPU_VM			0x13
55 #define DRM_AMDGPU_FENCE_TO_HANDLE	0x14
56 #define DRM_AMDGPU_SCHED		0x15
57 
58 #define DRM_IOCTL_AMDGPU_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
59 #define DRM_IOCTL_AMDGPU_GEM_MMAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
60 #define DRM_IOCTL_AMDGPU_CTX		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
61 #define DRM_IOCTL_AMDGPU_BO_LIST	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
62 #define DRM_IOCTL_AMDGPU_CS		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
63 #define DRM_IOCTL_AMDGPU_INFO		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
64 #define DRM_IOCTL_AMDGPU_GEM_METADATA	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
66 #define DRM_IOCTL_AMDGPU_GEM_VA		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
67 #define DRM_IOCTL_AMDGPU_WAIT_CS	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
68 #define DRM_IOCTL_AMDGPU_GEM_OP		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES	DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
71 #define DRM_IOCTL_AMDGPU_VM		DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73 #define DRM_IOCTL_AMDGPU_SCHED		DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
74 
75 /**
76  * DOC: memory domains
77  *
78  * %AMDGPU_GEM_DOMAIN_CPU	System memory that is not GPU accessible.
79  * Memory in this pool could be swapped out to disk if there is pressure.
80  *
81  * %AMDGPU_GEM_DOMAIN_GTT	GPU accessible system memory, mapped into the
82  * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
83  * pages of system memory, allows GPU access system memory in a linearized
84  * fashion.
85  *
86  * %AMDGPU_GEM_DOMAIN_VRAM	Local video memory. For APUs, it is memory
87  * carved out by the BIOS.
88  *
89  * %AMDGPU_GEM_DOMAIN_GDS	Global on-chip data storage used to share data
90  * across shader threads.
91  *
92  * %AMDGPU_GEM_DOMAIN_GWS	Global wave sync, used to synchronize the
93  * execution of all the waves on a device.
94  *
95  * %AMDGPU_GEM_DOMAIN_OA	Ordered append, used by 3D or Compute engines
96  * for appending data.
97  */
98 #define AMDGPU_GEM_DOMAIN_CPU		0x1
99 #define AMDGPU_GEM_DOMAIN_GTT		0x2
100 #define AMDGPU_GEM_DOMAIN_VRAM		0x4
101 #define AMDGPU_GEM_DOMAIN_GDS		0x8
102 #define AMDGPU_GEM_DOMAIN_GWS		0x10
103 #define AMDGPU_GEM_DOMAIN_OA		0x20
104 #define AMDGPU_GEM_DOMAIN_MASK		(AMDGPU_GEM_DOMAIN_CPU | \
105 					 AMDGPU_GEM_DOMAIN_GTT | \
106 					 AMDGPU_GEM_DOMAIN_VRAM | \
107 					 AMDGPU_GEM_DOMAIN_GDS | \
108 					 AMDGPU_GEM_DOMAIN_GWS | \
109 					 AMDGPU_GEM_DOMAIN_OA)
110 
111 /* Flag that CPU access will be required for the case of VRAM domain */
112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED	(1 << 0)
113 /* Flag that CPU access will not work, this VRAM domain is invisible */
114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS		(1 << 1)
115 /* Flag that USWC attributes should be used for GTT */
116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC		(1 << 2)
117 /* Flag that the memory should be in VRAM and cleared */
118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED		(1 << 3)
119 /* Flag that allocating the BO should use linear VRAM */
120 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS	(1 << 5)
121 /* Flag that BO is always valid in this VM */
122 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID	(1 << 6)
123 /* Flag that BO sharing will be explicitly synchronized */
124 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC		(1 << 7)
125 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
126  * for the second page onward should be set to NC. It should never
127  * be used by user space applications.
128  */
129 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9		(1 << 8)
130 /* Flag that BO may contain sensitive data that must be wiped before
131  * releasing the memory
132  */
133 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE	(1 << 9)
134 /* Flag that BO will be encrypted and that the TMZ bit should be
135  * set in the PTEs when mapping this buffer via GPUVM or
136  * accessing it with various hw blocks
137  */
138 #define AMDGPU_GEM_CREATE_ENCRYPTED		(1 << 10)
139 /* Flag that BO will be used only in preemptible context, which does
140  * not require GTT memory accounting
141  */
142 #define AMDGPU_GEM_CREATE_PREEMPTIBLE		(1 << 11)
143 /* Flag that BO can be discarded under memory pressure without keeping the
144  * content.
145  */
146 #define AMDGPU_GEM_CREATE_DISCARDABLE		(1 << 12)
147 
148 struct drm_amdgpu_gem_create_in  {
149 	/** the requested memory size */
150 	__u64 bo_size;
151 	/** physical start_addr alignment in bytes for some HW requirements */
152 	__u64 alignment;
153 	/** the requested memory domains */
154 	__u64 domains;
155 	/** allocation flags */
156 	__u64 domain_flags;
157 };
158 
159 struct drm_amdgpu_gem_create_out  {
160 	/** returned GEM object handle */
161 	__u32 handle;
162 	__u32 _pad;
163 };
164 
165 union drm_amdgpu_gem_create {
166 	struct drm_amdgpu_gem_create_in		in;
167 	struct drm_amdgpu_gem_create_out	out;
168 };
169 
170 /** Opcode to create new residency list.  */
171 #define AMDGPU_BO_LIST_OP_CREATE	0
172 /** Opcode to destroy previously created residency list */
173 #define AMDGPU_BO_LIST_OP_DESTROY	1
174 /** Opcode to update resource information in the list */
175 #define AMDGPU_BO_LIST_OP_UPDATE	2
176 
177 struct drm_amdgpu_bo_list_in {
178 	/** Type of operation */
179 	__u32 operation;
180 	/** Handle of list or 0 if we want to create one */
181 	__u32 list_handle;
182 	/** Number of BOs in list  */
183 	__u32 bo_number;
184 	/** Size of each element describing BO */
185 	__u32 bo_info_size;
186 	/** Pointer to array describing BOs */
187 	__u64 bo_info_ptr;
188 };
189 
190 struct drm_amdgpu_bo_list_entry {
191 	/** Handle of BO */
192 	__u32 bo_handle;
193 	/** New (if specified) BO priority to be used during migration */
194 	__u32 bo_priority;
195 };
196 
197 struct drm_amdgpu_bo_list_out {
198 	/** Handle of resource list  */
199 	__u32 list_handle;
200 	__u32 _pad;
201 };
202 
203 union drm_amdgpu_bo_list {
204 	struct drm_amdgpu_bo_list_in in;
205 	struct drm_amdgpu_bo_list_out out;
206 };
207 
208 /* context related */
209 #define AMDGPU_CTX_OP_ALLOC_CTX	1
210 #define AMDGPU_CTX_OP_FREE_CTX	2
211 #define AMDGPU_CTX_OP_QUERY_STATE	3
212 #define AMDGPU_CTX_OP_QUERY_STATE2	4
213 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE	5
214 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE	6
215 
216 /* GPU reset status */
217 #define AMDGPU_CTX_NO_RESET		0
218 /* this the context caused it */
219 #define AMDGPU_CTX_GUILTY_RESET		1
220 /* some other context caused it */
221 #define AMDGPU_CTX_INNOCENT_RESET	2
222 /* unknown cause */
223 #define AMDGPU_CTX_UNKNOWN_RESET	3
224 
225 /* indicate gpu reset occured after ctx created */
226 #define AMDGPU_CTX_QUERY2_FLAGS_RESET    (1<<0)
227 /* indicate vram lost occured after ctx created */
228 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
229 /* indicate some job from this context once cause gpu hang */
230 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY   (1<<2)
231 /* indicate some errors are detected by RAS */
232 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE   (1<<3)
233 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE   (1<<4)
234 
235 /* Context priority level */
236 #define AMDGPU_CTX_PRIORITY_UNSET       -2048
237 #define AMDGPU_CTX_PRIORITY_VERY_LOW    -1023
238 #define AMDGPU_CTX_PRIORITY_LOW         -512
239 #define AMDGPU_CTX_PRIORITY_NORMAL      0
240 /*
241  * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
242  * CAP_SYS_NICE or DRM_MASTER
243 */
244 #define AMDGPU_CTX_PRIORITY_HIGH        512
245 #define AMDGPU_CTX_PRIORITY_VERY_HIGH   1023
246 
247 /* select a stable profiling pstate for perfmon tools */
248 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK  0xf
249 #define AMDGPU_CTX_STABLE_PSTATE_NONE  0
250 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD  1
251 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK  2
252 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK  3
253 #define AMDGPU_CTX_STABLE_PSTATE_PEAK  4
254 
255 struct drm_amdgpu_ctx_in {
256 	/** AMDGPU_CTX_OP_* */
257 	__u32	op;
258 	/** Flags */
259 	__u32	flags;
260 	__u32	ctx_id;
261 	/** AMDGPU_CTX_PRIORITY_* */
262 	__s32	priority;
263 };
264 
265 union drm_amdgpu_ctx_out {
266 		struct {
267 			__u32	ctx_id;
268 			__u32	_pad;
269 		} alloc;
270 
271 		struct {
272 			/** For future use, no flags defined so far */
273 			__u64	flags;
274 			/** Number of resets caused by this context so far. */
275 			__u32	hangs;
276 			/** Reset status since the last call of the ioctl. */
277 			__u32	reset_status;
278 		} state;
279 
280 		struct {
281 			__u32	flags;
282 			__u32	_pad;
283 		} pstate;
284 };
285 
286 union drm_amdgpu_ctx {
287 	struct drm_amdgpu_ctx_in in;
288 	union drm_amdgpu_ctx_out out;
289 };
290 
291 /* vm ioctl */
292 #define AMDGPU_VM_OP_RESERVE_VMID	1
293 #define AMDGPU_VM_OP_UNRESERVE_VMID	2
294 
295 struct drm_amdgpu_vm_in {
296 	/** AMDGPU_VM_OP_* */
297 	__u32	op;
298 	__u32	flags;
299 };
300 
301 struct drm_amdgpu_vm_out {
302 	/** For future use, no flags defined so far */
303 	__u64	flags;
304 };
305 
306 union drm_amdgpu_vm {
307 	struct drm_amdgpu_vm_in in;
308 	struct drm_amdgpu_vm_out out;
309 };
310 
311 /* sched ioctl */
312 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE	1
313 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE	2
314 
315 struct drm_amdgpu_sched_in {
316 	/* AMDGPU_SCHED_OP_* */
317 	__u32	op;
318 	__u32	fd;
319 	/** AMDGPU_CTX_PRIORITY_* */
320 	__s32	priority;
321 	__u32   ctx_id;
322 };
323 
324 union drm_amdgpu_sched {
325 	struct drm_amdgpu_sched_in in;
326 };
327 
328 /*
329  * This is not a reliable API and you should expect it to fail for any
330  * number of reasons and have fallback path that do not use userptr to
331  * perform any operation.
332  */
333 #define AMDGPU_GEM_USERPTR_READONLY	(1 << 0)
334 #define AMDGPU_GEM_USERPTR_ANONONLY	(1 << 1)
335 #define AMDGPU_GEM_USERPTR_VALIDATE	(1 << 2)
336 #define AMDGPU_GEM_USERPTR_REGISTER	(1 << 3)
337 
338 struct drm_amdgpu_gem_userptr {
339 	__u64		addr;
340 	__u64		size;
341 	/* AMDGPU_GEM_USERPTR_* */
342 	__u32		flags;
343 	/* Resulting GEM handle */
344 	__u32		handle;
345 };
346 
347 /* SI-CI-VI: */
348 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
349 #define AMDGPU_TILING_ARRAY_MODE_SHIFT			0
350 #define AMDGPU_TILING_ARRAY_MODE_MASK			0xf
351 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT			4
352 #define AMDGPU_TILING_PIPE_CONFIG_MASK			0x1f
353 #define AMDGPU_TILING_TILE_SPLIT_SHIFT			9
354 #define AMDGPU_TILING_TILE_SPLIT_MASK			0x7
355 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT		12
356 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK		0x7
357 #define AMDGPU_TILING_BANK_WIDTH_SHIFT			15
358 #define AMDGPU_TILING_BANK_WIDTH_MASK			0x3
359 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT			17
360 #define AMDGPU_TILING_BANK_HEIGHT_MASK			0x3
361 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT		19
362 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK		0x3
363 #define AMDGPU_TILING_NUM_BANKS_SHIFT			21
364 #define AMDGPU_TILING_NUM_BANKS_MASK			0x3
365 
366 /* GFX9 and later: */
367 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT		0
368 #define AMDGPU_TILING_SWIZZLE_MODE_MASK			0x1f
369 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT		5
370 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK		0xFFFFFF
371 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT		29
372 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK		0x3FFF
373 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT		43
374 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK		0x1
375 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT	44
376 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK		0x1
377 #define AMDGPU_TILING_SCANOUT_SHIFT			63
378 #define AMDGPU_TILING_SCANOUT_MASK			0x1
379 
380 /* Set/Get helpers for tiling flags. */
381 #define AMDGPU_TILING_SET(field, value) \
382 	(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
383 #define AMDGPU_TILING_GET(value, field) \
384 	(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
385 
386 #define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1
387 #define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2
388 
389 /** The same structure is shared for input/output */
390 struct drm_amdgpu_gem_metadata {
391 	/** GEM Object handle */
392 	__u32	handle;
393 	/** Do we want get or set metadata */
394 	__u32	op;
395 	struct {
396 		/** For future use, no flags defined so far */
397 		__u64	flags;
398 		/** family specific tiling info */
399 		__u64	tiling_info;
400 		__u32	data_size_bytes;
401 		__u32	data[64];
402 	} data;
403 };
404 
405 struct drm_amdgpu_gem_mmap_in {
406 	/** the GEM object handle */
407 	__u32 handle;
408 	__u32 _pad;
409 };
410 
411 struct drm_amdgpu_gem_mmap_out {
412 	/** mmap offset from the vma offset manager */
413 	__u64 addr_ptr;
414 };
415 
416 union drm_amdgpu_gem_mmap {
417 	struct drm_amdgpu_gem_mmap_in   in;
418 	struct drm_amdgpu_gem_mmap_out out;
419 };
420 
421 struct drm_amdgpu_gem_wait_idle_in {
422 	/** GEM object handle */
423 	__u32 handle;
424 	/** For future use, no flags defined so far */
425 	__u32 flags;
426 	/** Absolute timeout to wait */
427 	__u64 timeout;
428 };
429 
430 struct drm_amdgpu_gem_wait_idle_out {
431 	/** BO status:  0 - BO is idle, 1 - BO is busy */
432 	__u32 status;
433 	/** Returned current memory domain */
434 	__u32 domain;
435 };
436 
437 union drm_amdgpu_gem_wait_idle {
438 	struct drm_amdgpu_gem_wait_idle_in  in;
439 	struct drm_amdgpu_gem_wait_idle_out out;
440 };
441 
442 struct drm_amdgpu_wait_cs_in {
443 	/* Command submission handle
444          * handle equals 0 means none to wait for
445          * handle equals ~0ull means wait for the latest sequence number
446          */
447 	__u64 handle;
448 	/** Absolute timeout to wait */
449 	__u64 timeout;
450 	__u32 ip_type;
451 	__u32 ip_instance;
452 	__u32 ring;
453 	__u32 ctx_id;
454 };
455 
456 struct drm_amdgpu_wait_cs_out {
457 	/** CS status:  0 - CS completed, 1 - CS still busy */
458 	__u64 status;
459 };
460 
461 union drm_amdgpu_wait_cs {
462 	struct drm_amdgpu_wait_cs_in in;
463 	struct drm_amdgpu_wait_cs_out out;
464 };
465 
466 struct drm_amdgpu_fence {
467 	__u32 ctx_id;
468 	__u32 ip_type;
469 	__u32 ip_instance;
470 	__u32 ring;
471 	__u64 seq_no;
472 };
473 
474 struct drm_amdgpu_wait_fences_in {
475 	/** This points to uint64_t * which points to fences */
476 	__u64 fences;
477 	__u32 fence_count;
478 	__u32 wait_all;
479 	__u64 timeout_ns;
480 };
481 
482 struct drm_amdgpu_wait_fences_out {
483 	__u32 status;
484 	__u32 first_signaled;
485 };
486 
487 union drm_amdgpu_wait_fences {
488 	struct drm_amdgpu_wait_fences_in in;
489 	struct drm_amdgpu_wait_fences_out out;
490 };
491 
492 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO	0
493 #define AMDGPU_GEM_OP_SET_PLACEMENT		1
494 
495 /* Sets or returns a value associated with a buffer. */
496 struct drm_amdgpu_gem_op {
497 	/** GEM object handle */
498 	__u32	handle;
499 	/** AMDGPU_GEM_OP_* */
500 	__u32	op;
501 	/** Input or return value */
502 	__u64	value;
503 };
504 
505 #define AMDGPU_VA_OP_MAP			1
506 #define AMDGPU_VA_OP_UNMAP			2
507 #define AMDGPU_VA_OP_CLEAR			3
508 #define AMDGPU_VA_OP_REPLACE			4
509 
510 /* Delay the page table update till the next CS */
511 #define AMDGPU_VM_DELAY_UPDATE		(1 << 0)
512 
513 /* Mapping flags */
514 /* readable mapping */
515 #define AMDGPU_VM_PAGE_READABLE		(1 << 1)
516 /* writable mapping */
517 #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
518 /* executable mapping, new for VI */
519 #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
520 /* partially resident texture */
521 #define AMDGPU_VM_PAGE_PRT		(1 << 4)
522 /* MTYPE flags use bit 5 to 8 */
523 #define AMDGPU_VM_MTYPE_MASK		(0xf << 5)
524 /* Default MTYPE. Pre-AI must use this.  Recommended for newer ASICs. */
525 #define AMDGPU_VM_MTYPE_DEFAULT		(0 << 5)
526 /* Use Non Coherent MTYPE instead of default MTYPE */
527 #define AMDGPU_VM_MTYPE_NC		(1 << 5)
528 /* Use Write Combine MTYPE instead of default MTYPE */
529 #define AMDGPU_VM_MTYPE_WC		(2 << 5)
530 /* Use Cache Coherent MTYPE instead of default MTYPE */
531 #define AMDGPU_VM_MTYPE_CC		(3 << 5)
532 /* Use UnCached MTYPE instead of default MTYPE */
533 #define AMDGPU_VM_MTYPE_UC		(4 << 5)
534 /* Use Read Write MTYPE instead of default MTYPE */
535 #define AMDGPU_VM_MTYPE_RW		(5 << 5)
536 /* don't allocate MALL */
537 #define AMDGPU_VM_PAGE_NOALLOC		(1 << 9)
538 
539 struct drm_amdgpu_gem_va {
540 	/** GEM object handle */
541 	__u32 handle;
542 	__u32 _pad;
543 	/** AMDGPU_VA_OP_* */
544 	__u32 operation;
545 	/** AMDGPU_VM_PAGE_* */
546 	__u32 flags;
547 	/** va address to assign . Must be correctly aligned.*/
548 	__u64 va_address;
549 	/** Specify offset inside of BO to assign. Must be correctly aligned.*/
550 	__u64 offset_in_bo;
551 	/** Specify mapping size. Must be correctly aligned. */
552 	__u64 map_size;
553 };
554 
555 #define AMDGPU_HW_IP_GFX          0
556 #define AMDGPU_HW_IP_COMPUTE      1
557 #define AMDGPU_HW_IP_DMA          2
558 #define AMDGPU_HW_IP_UVD          3
559 #define AMDGPU_HW_IP_VCE          4
560 #define AMDGPU_HW_IP_UVD_ENC      5
561 #define AMDGPU_HW_IP_VCN_DEC      6
562 #define AMDGPU_HW_IP_VCN_ENC      7
563 #define AMDGPU_HW_IP_VCN_JPEG     8
564 #define AMDGPU_HW_IP_NUM          9
565 
566 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
567 
568 #define AMDGPU_CHUNK_ID_IB		0x01
569 #define AMDGPU_CHUNK_ID_FENCE		0x02
570 #define AMDGPU_CHUNK_ID_DEPENDENCIES	0x03
571 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN      0x04
572 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
573 #define AMDGPU_CHUNK_ID_BO_HANDLES      0x06
574 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES	0x07
575 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT    0x08
576 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x09
577 
578 struct drm_amdgpu_cs_chunk {
579 	__u32		chunk_id;
580 	__u32		length_dw;
581 	__u64		chunk_data;
582 };
583 
584 struct drm_amdgpu_cs_in {
585 	/** Rendering context id */
586 	__u32		ctx_id;
587 	/**  Handle of resource list associated with CS */
588 	__u32		bo_list_handle;
589 	__u32		num_chunks;
590 	__u32		flags;
591 	/** this points to __u64 * which point to cs chunks */
592 	__u64		chunks;
593 };
594 
595 struct drm_amdgpu_cs_out {
596 	__u64 handle;
597 };
598 
599 union drm_amdgpu_cs {
600 	struct drm_amdgpu_cs_in in;
601 	struct drm_amdgpu_cs_out out;
602 };
603 
604 /* Specify flags to be used for IB */
605 
606 /* This IB should be submitted to CE */
607 #define AMDGPU_IB_FLAG_CE	(1<<0)
608 
609 /* Preamble flag, which means the IB could be dropped if no context switch */
610 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
611 
612 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
613 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
614 
615 /* The IB fence should do the L2 writeback but not invalidate any shader
616  * caches (L2/vL1/sL1/I$). */
617 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
618 
619 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
620  * This will reset wave ID counters for the IB.
621  */
622 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
623 
624 /* Flag the IB as secure (TMZ)
625  */
626 #define AMDGPU_IB_FLAGS_SECURE  (1 << 5)
627 
628 /* Tell KMD to flush and invalidate caches
629  */
630 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC  (1 << 6)
631 
632 struct drm_amdgpu_cs_chunk_ib {
633 	__u32 _pad;
634 	/** AMDGPU_IB_FLAG_* */
635 	__u32 flags;
636 	/** Virtual address to begin IB execution */
637 	__u64 va_start;
638 	/** Size of submission */
639 	__u32 ib_bytes;
640 	/** HW IP to submit to */
641 	__u32 ip_type;
642 	/** HW IP index of the same type to submit to  */
643 	__u32 ip_instance;
644 	/** Ring index to submit to */
645 	__u32 ring;
646 };
647 
648 struct drm_amdgpu_cs_chunk_dep {
649 	__u32 ip_type;
650 	__u32 ip_instance;
651 	__u32 ring;
652 	__u32 ctx_id;
653 	__u64 handle;
654 };
655 
656 struct drm_amdgpu_cs_chunk_fence {
657 	__u32 handle;
658 	__u32 offset;
659 };
660 
661 struct drm_amdgpu_cs_chunk_sem {
662 	__u32 handle;
663 };
664 
665 struct drm_amdgpu_cs_chunk_syncobj {
666        __u32 handle;
667        __u32 flags;
668        __u64 point;
669 };
670 
671 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ	0
672 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD	1
673 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD	2
674 
675 union drm_amdgpu_fence_to_handle {
676 	struct {
677 		struct drm_amdgpu_fence fence;
678 		__u32 what;
679 		__u32 pad;
680 	} in;
681 	struct {
682 		__u32 handle;
683 	} out;
684 };
685 
686 struct drm_amdgpu_cs_chunk_data {
687 	union {
688 		struct drm_amdgpu_cs_chunk_ib		ib_data;
689 		struct drm_amdgpu_cs_chunk_fence	fence_data;
690 	};
691 };
692 
693 /*
694  *  Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
695  *
696  */
697 #define AMDGPU_IDS_FLAGS_FUSION         0x1
698 #define AMDGPU_IDS_FLAGS_PREEMPTION     0x2
699 #define AMDGPU_IDS_FLAGS_TMZ            0x4
700 
701 /* indicate if acceleration can be working */
702 #define AMDGPU_INFO_ACCEL_WORKING		0x00
703 /* get the crtc_id from the mode object id? */
704 #define AMDGPU_INFO_CRTC_FROM_ID		0x01
705 /* query hw IP info */
706 #define AMDGPU_INFO_HW_IP_INFO			0x02
707 /* query hw IP instance count for the specified type */
708 #define AMDGPU_INFO_HW_IP_COUNT			0x03
709 /* timestamp for GL_ARB_timer_query */
710 #define AMDGPU_INFO_TIMESTAMP			0x05
711 /* Query the firmware version */
712 #define AMDGPU_INFO_FW_VERSION			0x0e
713 	/* Subquery id: Query VCE firmware version */
714 	#define AMDGPU_INFO_FW_VCE		0x1
715 	/* Subquery id: Query UVD firmware version */
716 	#define AMDGPU_INFO_FW_UVD		0x2
717 	/* Subquery id: Query GMC firmware version */
718 	#define AMDGPU_INFO_FW_GMC		0x03
719 	/* Subquery id: Query GFX ME firmware version */
720 	#define AMDGPU_INFO_FW_GFX_ME		0x04
721 	/* Subquery id: Query GFX PFP firmware version */
722 	#define AMDGPU_INFO_FW_GFX_PFP		0x05
723 	/* Subquery id: Query GFX CE firmware version */
724 	#define AMDGPU_INFO_FW_GFX_CE		0x06
725 	/* Subquery id: Query GFX RLC firmware version */
726 	#define AMDGPU_INFO_FW_GFX_RLC		0x07
727 	/* Subquery id: Query GFX MEC firmware version */
728 	#define AMDGPU_INFO_FW_GFX_MEC		0x08
729 	/* Subquery id: Query SMC firmware version */
730 	#define AMDGPU_INFO_FW_SMC		0x0a
731 	/* Subquery id: Query SDMA firmware version */
732 	#define AMDGPU_INFO_FW_SDMA		0x0b
733 	/* Subquery id: Query PSP SOS firmware version */
734 	#define AMDGPU_INFO_FW_SOS		0x0c
735 	/* Subquery id: Query PSP ASD firmware version */
736 	#define AMDGPU_INFO_FW_ASD		0x0d
737 	/* Subquery id: Query VCN firmware version */
738 	#define AMDGPU_INFO_FW_VCN		0x0e
739 	/* Subquery id: Query GFX RLC SRLC firmware version */
740 	#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
741 	/* Subquery id: Query GFX RLC SRLG firmware version */
742 	#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
743 	/* Subquery id: Query GFX RLC SRLS firmware version */
744 	#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
745 	/* Subquery id: Query DMCU firmware version */
746 	#define AMDGPU_INFO_FW_DMCU		0x12
747 	#define AMDGPU_INFO_FW_TA		0x13
748 	/* Subquery id: Query DMCUB firmware version */
749 	#define AMDGPU_INFO_FW_DMCUB		0x14
750 	/* Subquery id: Query TOC firmware version */
751 	#define AMDGPU_INFO_FW_TOC		0x15
752 	/* Subquery id: Query CAP firmware version */
753 	#define AMDGPU_INFO_FW_CAP		0x16
754 
755 /* number of bytes moved for TTM migration */
756 #define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
757 /* the used VRAM size */
758 #define AMDGPU_INFO_VRAM_USAGE			0x10
759 /* the used GTT size */
760 #define AMDGPU_INFO_GTT_USAGE			0x11
761 /* Information about GDS, etc. resource configuration */
762 #define AMDGPU_INFO_GDS_CONFIG			0x13
763 /* Query information about VRAM and GTT domains */
764 #define AMDGPU_INFO_VRAM_GTT			0x14
765 /* Query information about register in MMR address space*/
766 #define AMDGPU_INFO_READ_MMR_REG		0x15
767 /* Query information about device: rev id, family, etc. */
768 #define AMDGPU_INFO_DEV_INFO			0x16
769 /* visible vram usage */
770 #define AMDGPU_INFO_VIS_VRAM_USAGE		0x17
771 /* number of TTM buffer evictions */
772 #define AMDGPU_INFO_NUM_EVICTIONS		0x18
773 /* Query memory about VRAM and GTT domains */
774 #define AMDGPU_INFO_MEMORY			0x19
775 /* Query vce clock table */
776 #define AMDGPU_INFO_VCE_CLOCK_TABLE		0x1A
777 /* Query vbios related information */
778 #define AMDGPU_INFO_VBIOS			0x1B
779 	/* Subquery id: Query vbios size */
780 	#define AMDGPU_INFO_VBIOS_SIZE		0x1
781 	/* Subquery id: Query vbios image */
782 	#define AMDGPU_INFO_VBIOS_IMAGE		0x2
783 	/* Subquery id: Query vbios info */
784 	#define AMDGPU_INFO_VBIOS_INFO		0x3
785 /* Query UVD handles */
786 #define AMDGPU_INFO_NUM_HANDLES			0x1C
787 /* Query sensor related information */
788 #define AMDGPU_INFO_SENSOR			0x1D
789 	/* Subquery id: Query GPU shader clock */
790 	#define AMDGPU_INFO_SENSOR_GFX_SCLK		0x1
791 	/* Subquery id: Query GPU memory clock */
792 	#define AMDGPU_INFO_SENSOR_GFX_MCLK		0x2
793 	/* Subquery id: Query GPU temperature */
794 	#define AMDGPU_INFO_SENSOR_GPU_TEMP		0x3
795 	/* Subquery id: Query GPU load */
796 	#define AMDGPU_INFO_SENSOR_GPU_LOAD		0x4
797 	/* Subquery id: Query average GPU power	*/
798 	#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER	0x5
799 	/* Subquery id: Query northbridge voltage */
800 	#define AMDGPU_INFO_SENSOR_VDDNB		0x6
801 	/* Subquery id: Query graphics voltage */
802 	#define AMDGPU_INFO_SENSOR_VDDGFX		0x7
803 	/* Subquery id: Query GPU stable pstate shader clock */
804 	#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK		0x8
805 	/* Subquery id: Query GPU stable pstate memory clock */
806 	#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK		0x9
807 /* Number of VRAM page faults on CPU access. */
808 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS	0x1E
809 #define AMDGPU_INFO_VRAM_LOST_COUNTER		0x1F
810 /* query ras mask of enabled features*/
811 #define AMDGPU_INFO_RAS_ENABLED_FEATURES	0x20
812 /* RAS MASK: UMC (VRAM) */
813 #define AMDGPU_INFO_RAS_ENABLED_UMC			(1 << 0)
814 /* RAS MASK: SDMA */
815 #define AMDGPU_INFO_RAS_ENABLED_SDMA			(1 << 1)
816 /* RAS MASK: GFX */
817 #define AMDGPU_INFO_RAS_ENABLED_GFX			(1 << 2)
818 /* RAS MASK: MMHUB */
819 #define AMDGPU_INFO_RAS_ENABLED_MMHUB			(1 << 3)
820 /* RAS MASK: ATHUB */
821 #define AMDGPU_INFO_RAS_ENABLED_ATHUB			(1 << 4)
822 /* RAS MASK: PCIE */
823 #define AMDGPU_INFO_RAS_ENABLED_PCIE			(1 << 5)
824 /* RAS MASK: HDP */
825 #define AMDGPU_INFO_RAS_ENABLED_HDP			(1 << 6)
826 /* RAS MASK: XGMI */
827 #define AMDGPU_INFO_RAS_ENABLED_XGMI			(1 << 7)
828 /* RAS MASK: DF */
829 #define AMDGPU_INFO_RAS_ENABLED_DF			(1 << 8)
830 /* RAS MASK: SMN */
831 #define AMDGPU_INFO_RAS_ENABLED_SMN			(1 << 9)
832 /* RAS MASK: SEM */
833 #define AMDGPU_INFO_RAS_ENABLED_SEM			(1 << 10)
834 /* RAS MASK: MP0 */
835 #define AMDGPU_INFO_RAS_ENABLED_MP0			(1 << 11)
836 /* RAS MASK: MP1 */
837 #define AMDGPU_INFO_RAS_ENABLED_MP1			(1 << 12)
838 /* RAS MASK: FUSE */
839 #define AMDGPU_INFO_RAS_ENABLED_FUSE			(1 << 13)
840 /* query video encode/decode caps */
841 #define AMDGPU_INFO_VIDEO_CAPS			0x21
842 	/* Subquery id: Decode */
843 	#define AMDGPU_INFO_VIDEO_CAPS_DECODE		0
844 	/* Subquery id: Encode */
845 	#define AMDGPU_INFO_VIDEO_CAPS_ENCODE		1
846 
847 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT	0
848 #define AMDGPU_INFO_MMR_SE_INDEX_MASK	0xff
849 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
850 #define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff
851 
852 struct drm_amdgpu_query_fw {
853 	/** AMDGPU_INFO_FW_* */
854 	__u32 fw_type;
855 	/**
856 	 * Index of the IP if there are more IPs of
857 	 * the same type.
858 	 */
859 	__u32 ip_instance;
860 	/**
861 	 * Index of the engine. Whether this is used depends
862 	 * on the firmware type. (e.g. MEC, SDMA)
863 	 */
864 	__u32 index;
865 	__u32 _pad;
866 };
867 
868 /* Input structure for the INFO ioctl */
869 struct drm_amdgpu_info {
870 	/* Where the return value will be stored */
871 	__u64 return_pointer;
872 	/* The size of the return value. Just like "size" in "snprintf",
873 	 * it limits how many bytes the kernel can write. */
874 	__u32 return_size;
875 	/* The query request id. */
876 	__u32 query;
877 
878 	union {
879 		struct {
880 			__u32 id;
881 			__u32 _pad;
882 		} mode_crtc;
883 
884 		struct {
885 			/** AMDGPU_HW_IP_* */
886 			__u32 type;
887 			/**
888 			 * Index of the IP if there are more IPs of the same
889 			 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
890 			 */
891 			__u32 ip_instance;
892 		} query_hw_ip;
893 
894 		struct {
895 			__u32 dword_offset;
896 			/** number of registers to read */
897 			__u32 count;
898 			__u32 instance;
899 			/** For future use, no flags defined so far */
900 			__u32 flags;
901 		} read_mmr_reg;
902 
903 		struct drm_amdgpu_query_fw query_fw;
904 
905 		struct {
906 			__u32 type;
907 			__u32 offset;
908 		} vbios_info;
909 
910 		struct {
911 			__u32 type;
912 		} sensor_info;
913 
914 		struct {
915 			__u32 type;
916 		} video_cap;
917 	};
918 };
919 
920 struct drm_amdgpu_info_gds {
921 	/** GDS GFX partition size */
922 	__u32 gds_gfx_partition_size;
923 	/** GDS compute partition size */
924 	__u32 compute_partition_size;
925 	/** total GDS memory size */
926 	__u32 gds_total_size;
927 	/** GWS size per GFX partition */
928 	__u32 gws_per_gfx_partition;
929 	/** GSW size per compute partition */
930 	__u32 gws_per_compute_partition;
931 	/** OA size per GFX partition */
932 	__u32 oa_per_gfx_partition;
933 	/** OA size per compute partition */
934 	__u32 oa_per_compute_partition;
935 	__u32 _pad;
936 };
937 
938 struct drm_amdgpu_info_vram_gtt {
939 	__u64 vram_size;
940 	__u64 vram_cpu_accessible_size;
941 	__u64 gtt_size;
942 };
943 
944 struct drm_amdgpu_heap_info {
945 	/** max. physical memory */
946 	__u64 total_heap_size;
947 
948 	/** Theoretical max. available memory in the given heap */
949 	__u64 usable_heap_size;
950 
951 	/**
952 	 * Number of bytes allocated in the heap. This includes all processes
953 	 * and private allocations in the kernel. It changes when new buffers
954 	 * are allocated, freed, and moved. It cannot be larger than
955 	 * heap_size.
956 	 */
957 	__u64 heap_usage;
958 
959 	/**
960 	 * Theoretical possible max. size of buffer which
961 	 * could be allocated in the given heap
962 	 */
963 	__u64 max_allocation;
964 };
965 
966 struct drm_amdgpu_memory_info {
967 	struct drm_amdgpu_heap_info vram;
968 	struct drm_amdgpu_heap_info cpu_accessible_vram;
969 	struct drm_amdgpu_heap_info gtt;
970 };
971 
972 struct drm_amdgpu_info_firmware {
973 	__u32 ver;
974 	__u32 feature;
975 };
976 
977 struct drm_amdgpu_info_vbios {
978 	__u8 name[64];
979 	__u8 vbios_pn[64];
980 	__u32 version;
981 	__u32 pad;
982 	__u8 vbios_ver_str[32];
983 	__u8 date[32];
984 };
985 
986 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
987 #define AMDGPU_VRAM_TYPE_GDDR1 1
988 #define AMDGPU_VRAM_TYPE_DDR2  2
989 #define AMDGPU_VRAM_TYPE_GDDR3 3
990 #define AMDGPU_VRAM_TYPE_GDDR4 4
991 #define AMDGPU_VRAM_TYPE_GDDR5 5
992 #define AMDGPU_VRAM_TYPE_HBM   6
993 #define AMDGPU_VRAM_TYPE_DDR3  7
994 #define AMDGPU_VRAM_TYPE_DDR4  8
995 #define AMDGPU_VRAM_TYPE_GDDR6 9
996 #define AMDGPU_VRAM_TYPE_DDR5  10
997 #define AMDGPU_VRAM_TYPE_LPDDR4 11
998 #define AMDGPU_VRAM_TYPE_LPDDR5 12
999 
1000 struct drm_amdgpu_info_device {
1001 	/** PCI Device ID */
1002 	__u32 device_id;
1003 	/** Internal chip revision: A0, A1, etc.) */
1004 	__u32 chip_rev;
1005 	__u32 external_rev;
1006 	/** Revision id in PCI Config space */
1007 	__u32 pci_rev;
1008 	__u32 family;
1009 	__u32 num_shader_engines;
1010 	__u32 num_shader_arrays_per_engine;
1011 	/* in KHz */
1012 	__u32 gpu_counter_freq;
1013 	__u64 max_engine_clock;
1014 	__u64 max_memory_clock;
1015 	/* cu information */
1016 	__u32 cu_active_number;
1017 	/* NOTE: cu_ao_mask is INVALID, DON'T use it */
1018 	__u32 cu_ao_mask;
1019 	__u32 cu_bitmap[4][4];
1020 	/** Render backend pipe mask. One render backend is CB+DB. */
1021 	__u32 enabled_rb_pipes_mask;
1022 	__u32 num_rb_pipes;
1023 	__u32 num_hw_gfx_contexts;
1024 	__u32 _pad;
1025 	__u64 ids_flags;
1026 	/** Starting virtual address for UMDs. */
1027 	__u64 virtual_address_offset;
1028 	/** The maximum virtual address */
1029 	__u64 virtual_address_max;
1030 	/** Required alignment of virtual addresses. */
1031 	__u32 virtual_address_alignment;
1032 	/** Page table entry - fragment size */
1033 	__u32 pte_fragment_size;
1034 	__u32 gart_page_size;
1035 	/** constant engine ram size*/
1036 	__u32 ce_ram_size;
1037 	/** video memory type info*/
1038 	__u32 vram_type;
1039 	/** video memory bit width*/
1040 	__u32 vram_bit_width;
1041 	/* vce harvesting instance */
1042 	__u32 vce_harvest_config;
1043 	/* gfx double offchip LDS buffers */
1044 	__u32 gc_double_offchip_lds_buf;
1045 	/* NGG Primitive Buffer */
1046 	__u64 prim_buf_gpu_addr;
1047 	/* NGG Position Buffer */
1048 	__u64 pos_buf_gpu_addr;
1049 	/* NGG Control Sideband */
1050 	__u64 cntl_sb_buf_gpu_addr;
1051 	/* NGG Parameter Cache */
1052 	__u64 param_buf_gpu_addr;
1053 	__u32 prim_buf_size;
1054 	__u32 pos_buf_size;
1055 	__u32 cntl_sb_buf_size;
1056 	__u32 param_buf_size;
1057 	/* wavefront size*/
1058 	__u32 wave_front_size;
1059 	/* shader visible vgprs*/
1060 	__u32 num_shader_visible_vgprs;
1061 	/* CU per shader array*/
1062 	__u32 num_cu_per_sh;
1063 	/* number of tcc blocks*/
1064 	__u32 num_tcc_blocks;
1065 	/* gs vgt table depth*/
1066 	__u32 gs_vgt_table_depth;
1067 	/* gs primitive buffer depth*/
1068 	__u32 gs_prim_buffer_depth;
1069 	/* max gs wavefront per vgt*/
1070 	__u32 max_gs_waves_per_vgt;
1071 	__u32 _pad1;
1072 	/* always on cu bitmap */
1073 	__u32 cu_ao_bitmap[4][4];
1074 	/** Starting high virtual address for UMDs. */
1075 	__u64 high_va_offset;
1076 	/** The maximum high virtual address */
1077 	__u64 high_va_max;
1078 	/* gfx10 pa_sc_tile_steering_override */
1079 	__u32 pa_sc_tile_steering_override;
1080 	/* disabled TCCs */
1081 	__u64 tcc_disabled_mask;
1082 };
1083 
1084 struct drm_amdgpu_info_hw_ip {
1085 	/** Version of h/w IP */
1086 	__u32  hw_ip_version_major;
1087 	__u32  hw_ip_version_minor;
1088 	/** Capabilities */
1089 	__u64  capabilities_flags;
1090 	/** command buffer address start alignment*/
1091 	__u32  ib_start_alignment;
1092 	/** command buffer size alignment*/
1093 	__u32  ib_size_alignment;
1094 	/** Bitmask of available rings. Bit 0 means ring 0, etc. */
1095 	__u32  available_rings;
1096 	__u32  _pad;
1097 };
1098 
1099 struct drm_amdgpu_info_num_handles {
1100 	/** Max handles as supported by firmware for UVD */
1101 	__u32  uvd_max_handles;
1102 	/** Handles currently in use for UVD */
1103 	__u32  uvd_used_handles;
1104 };
1105 
1106 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES		6
1107 
1108 struct drm_amdgpu_info_vce_clock_table_entry {
1109 	/** System clock */
1110 	__u32 sclk;
1111 	/** Memory clock */
1112 	__u32 mclk;
1113 	/** VCE clock */
1114 	__u32 eclk;
1115 	__u32 pad;
1116 };
1117 
1118 struct drm_amdgpu_info_vce_clock_table {
1119 	struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
1120 	__u32 num_valid_entries;
1121 	__u32 pad;
1122 };
1123 
1124 /* query video encode/decode caps */
1125 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2			0
1126 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4			1
1127 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1			2
1128 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC		3
1129 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC			4
1130 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG			5
1131 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9			6
1132 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1			7
1133 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT			8
1134 
1135 struct drm_amdgpu_info_video_codec_info {
1136 	__u32 valid;
1137 	__u32 max_width;
1138 	__u32 max_height;
1139 	__u32 max_pixels_per_frame;
1140 	__u32 max_level;
1141 	__u32 pad;
1142 };
1143 
1144 struct drm_amdgpu_info_video_caps {
1145 	struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
1146 };
1147 
1148 /*
1149  * Supported GPU families
1150  */
1151 #define AMDGPU_FAMILY_UNKNOWN			0
1152 #define AMDGPU_FAMILY_SI			110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
1153 #define AMDGPU_FAMILY_CI			120 /* Bonaire, Hawaii */
1154 #define AMDGPU_FAMILY_KV			125 /* Kaveri, Kabini, Mullins */
1155 #define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
1156 #define AMDGPU_FAMILY_CZ			135 /* Carrizo, Stoney */
1157 #define AMDGPU_FAMILY_AI			141 /* Vega10 */
1158 #define AMDGPU_FAMILY_RV			142 /* Raven */
1159 #define AMDGPU_FAMILY_NV			143 /* Navi10 */
1160 #define AMDGPU_FAMILY_VGH			144 /* Van Gogh */
1161 #define AMDGPU_FAMILY_GC_11_0_0			145 /* GC 11.0.0 */
1162 #define AMDGPU_FAMILY_YC			146 /* Yellow Carp */
1163 #define AMDGPU_FAMILY_GC_11_0_1			148 /* GC 11.0.1 */
1164 #define AMDGPU_FAMILY_GC_10_3_6			149 /* GC 10.3.6 */
1165 #define AMDGPU_FAMILY_GC_10_3_7			151 /* GC 10.3.7 */
1166 
1167 #if defined(__cplusplus)
1168 }
1169 #endif
1170 
1171 #endif
1172