1 /* 2 * macserial.h: Definitions for the Macintosh Z8530 serial driver. 3 * 4 * Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras. 5 * 6 * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au) 7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 8 */ 9 #ifndef _DECSERIAL_H 10 #define _DECSERIAL_H 11 12 #define NUM_ZSREGS 16 13 14 struct serial_struct { 15 int type; 16 int line; 17 int port; 18 int irq; 19 int flags; 20 int xmit_fifo_size; 21 int custom_divisor; 22 int baud_base; 23 unsigned short close_delay; 24 char reserved_char[2]; 25 int hub6; 26 unsigned short closing_wait; /* time to wait before closing */ 27 unsigned short closing_wait2; /* no longer used... */ 28 int reserved[4]; 29 }; 30 31 /* 32 * For the close wait times, 0 means wait forever for serial port to 33 * flush its output. 65535 means don't wait at all. 34 */ 35 #define ZILOG_CLOSING_WAIT_INF 0 36 #define ZILOG_CLOSING_WAIT_NONE 65535 37 38 /* 39 * Definitions for ZILOG_struct (and serial_struct) flags field 40 */ 41 #define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes 42 on the callout port */ 43 #define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */ 44 #define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */ 45 #define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */ 46 47 #define ZILOG_SPD_MASK 0x0030 48 #define ZILOG_SPD_HI 0x0010 /* Use 56000 instead of 38400 bps */ 49 50 #define ZILOG_SPD_VHI 0x0020 /* Use 115200 instead of 38400 bps */ 51 #define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */ 52 53 #define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */ 54 #define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */ 55 #define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */ 56 #define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */ 57 #define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */ 58 59 #define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */ 60 #define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged 61 * users can set or reset */ 62 63 /* Internal flags used only by kernel/chr_drv/serial.c */ 64 #define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */ 65 #define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */ 66 #define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */ 67 #define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */ 68 #define ZILOG_CLOSING 0x08000000 /* Serial port is closing */ 69 #define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */ 70 #define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */ 71 72 /* Software state per channel */ 73 74 #ifdef __KERNEL__ 75 /* 76 * This is our internal structure for each serial port's state. 77 * 78 * Many fields are paralleled by the structure used by the serial_struct 79 * structure. 80 * 81 * For definitions of the flags field, see tty.h 82 */ 83 84 struct dec_zschannel { 85 volatile unsigned char *control; 86 volatile unsigned char *data; 87 88 /* Current write register values */ 89 unsigned char curregs[NUM_ZSREGS]; 90 }; 91 92 struct dec_serial; 93 94 struct zs_hook { 95 int (*init_channel)(struct dec_serial* info); 96 void (*init_info)(struct dec_serial* info); 97 void (*rx_char)(unsigned char ch, unsigned char stat); 98 int (*poll_rx_char)(struct dec_serial* info); 99 int (*poll_tx_char)(struct dec_serial* info, 100 unsigned char ch); 101 unsigned cflags; 102 }; 103 104 struct dec_serial { 105 struct dec_serial *zs_next; /* For IRQ servicing chain */ 106 struct dec_zschannel *zs_channel; /* Channel registers */ 107 struct dec_zschannel *zs_chan_a; /* A side registers */ 108 unsigned char read_reg_zero; 109 110 char soft_carrier; /* Use soft carrier on this channel */ 111 char break_abort; /* Is serial console in, so process brk/abrt */ 112 struct zs_hook *hook; /* Hook on this channel */ 113 char is_cons; /* Is this our console. */ 114 unsigned char tx_active; /* character is being xmitted */ 115 unsigned char tx_stopped; /* output is suspended */ 116 117 /* We need to know the current clock divisor 118 * to read the bps rate the chip has currently 119 * loaded. 120 */ 121 unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */ 122 int zs_baud; 123 124 char change_needed; 125 126 int magic; 127 int baud_base; 128 int port; 129 int irq; 130 int flags; /* defined in tty.h */ 131 int type; /* UART type */ 132 struct tty_struct *tty; 133 int read_status_mask; 134 int ignore_status_mask; 135 int timeout; 136 int xmit_fifo_size; 137 int custom_divisor; 138 int x_char; /* xon/xoff character */ 139 int close_delay; 140 unsigned short closing_wait; 141 unsigned short closing_wait2; 142 unsigned long event; 143 unsigned long last_active; 144 int line; 145 int count; /* # of fd on device */ 146 int blocked_open; /* # of blocked opens */ 147 long session; /* Session of opening process */ 148 long pgrp; /* pgrp of opening process */ 149 unsigned char *xmit_buf; 150 int xmit_head; 151 int xmit_tail; 152 int xmit_cnt; 153 struct tq_struct tqueue; 154 struct tq_struct tqueue_hangup; 155 struct termios normal_termios; 156 struct termios callout_termios; 157 wait_queue_head_t open_wait; 158 wait_queue_head_t close_wait; 159 }; 160 161 162 #define SERIAL_MAGIC 0x5301 163 164 /* 165 * The size of the serial xmit buffer is 1 page, or 4096 bytes 166 */ 167 #define SERIAL_XMIT_SIZE 4096 168 169 /* 170 * Events are used to schedule things to happen at timer-interrupt 171 * time, instead of at rs interrupt time. 172 */ 173 #define RS_EVENT_WRITE_WAKEUP 0 174 175 #endif /* __KERNEL__ */ 176 177 /* Conversion routines to/from brg time constants from/to bits 178 * per second. 179 */ 180 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) 181 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) 182 183 /* The Zilog register set */ 184 185 #define FLAG 0x7e 186 187 /* Write Register 0 */ 188 #define R0 0 /* Register selects */ 189 #define R1 1 190 #define R2 2 191 #define R3 3 192 #define R4 4 193 #define R5 5 194 #define R6 6 195 #define R7 7 196 #define R8 8 197 #define R9 9 198 #define R10 10 199 #define R11 11 200 #define R12 12 201 #define R13 13 202 #define R14 14 203 #define R15 15 204 205 #define NULLCODE 0 /* Null Code */ 206 #define POINT_HIGH 0x8 /* Select upper half of registers */ 207 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 208 #define SEND_ABORT 0x18 /* HDLC Abort */ 209 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 210 #define RES_Tx_P 0x28 /* Reset TxINT Pending */ 211 #define ERR_RES 0x30 /* Error Reset */ 212 #define RES_H_IUS 0x38 /* Reset highest IUS */ 213 214 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 215 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 216 #define RES_EOM_L 0xC0 /* Reset EOM latch */ 217 218 /* Write Register 1 */ 219 220 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */ 221 #define TxINT_ENAB 0x2 /* Tx Int Enable */ 222 #define PAR_SPEC 0x4 /* Parity is special condition */ 223 224 #define RxINT_DISAB 0 /* Rx Int Disable */ 225 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */ 226 #define RxINT_ALL 0x10 /* Int on all Rx Characters or error */ 227 #define RxINT_ERR 0x18 /* Int on error only */ 228 #define RxINT_MASK 0x18 229 230 #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */ 231 #define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */ 232 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */ 233 234 /* Write Register #2 (Interrupt Vector) */ 235 236 /* Write Register 3 */ 237 238 #define RxENABLE 0x1 /* Rx Enable */ 239 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ 240 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */ 241 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */ 242 #define ENT_HM 0x10 /* Enter Hunt Mode */ 243 #define AUTO_ENAB 0x20 /* Auto Enables */ 244 #define Rx5 0x0 /* Rx 5 Bits/Character */ 245 #define Rx7 0x40 /* Rx 7 Bits/Character */ 246 #define Rx6 0x80 /* Rx 6 Bits/Character */ 247 #define Rx8 0xc0 /* Rx 8 Bits/Character */ 248 #define RxNBITS_MASK 0xc0 249 250 /* Write Register 4 */ 251 252 #define PAR_ENA 0x1 /* Parity Enable */ 253 #define PAR_EVEN 0x2 /* Parity Even/Odd* */ 254 255 #define SYNC_ENAB 0 /* Sync Modes Enable */ 256 #define SB1 0x4 /* 1 stop bit/char */ 257 #define SB15 0x8 /* 1.5 stop bits/char */ 258 #define SB2 0xc /* 2 stop bits/char */ 259 #define SB_MASK 0xc 260 261 #define MONSYNC 0 /* 8 Bit Sync character */ 262 #define BISYNC 0x10 /* 16 bit sync character */ 263 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ 264 #define EXTSYNC 0x30 /* External Sync Mode */ 265 266 #define X1CLK 0x0 /* x1 clock mode */ 267 #define X16CLK 0x40 /* x16 clock mode */ 268 #define X32CLK 0x80 /* x32 clock mode */ 269 #define X64CLK 0xC0 /* x64 clock mode */ 270 #define XCLK_MASK 0xC0 271 272 /* Write Register 5 */ 273 274 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */ 275 #define RTS 0x2 /* RTS */ 276 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */ 277 #define TxENAB 0x8 /* Tx Enable */ 278 #define SND_BRK 0x10 /* Send Break */ 279 #define Tx5 0x0 /* Tx 5 bits (or less)/character */ 280 #define Tx7 0x20 /* Tx 7 bits/character */ 281 #define Tx6 0x40 /* Tx 6 bits/character */ 282 #define Tx8 0x60 /* Tx 8 bits/character */ 283 #define TxNBITS_MASK 0x60 284 #define DTR 0x80 /* DTR */ 285 286 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ 287 288 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ 289 290 /* Write Register 8 (transmit buffer) */ 291 292 /* Write Register 9 (Master interrupt control) */ 293 #define VIS 1 /* Vector Includes Status */ 294 #define NV 2 /* No Vector */ 295 #define DLC 4 /* Disable Lower Chain */ 296 #define MIE 8 /* Master Interrupt Enable */ 297 #define STATHI 0x10 /* Status high */ 298 #define SOFTACK 0x20 /* Software Interrupt Acknowledge */ 299 #define NORESET 0 /* No reset on write to R9 */ 300 #define CHRB 0x40 /* Reset channel B */ 301 #define CHRA 0x80 /* Reset channel A */ 302 #define FHWRES 0xc0 /* Force hardware reset */ 303 304 /* Write Register 10 (misc control bits) */ 305 #define BIT6 1 /* 6 bit/8bit sync */ 306 #define LOOPMODE 2 /* SDLC Loop mode */ 307 #define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */ 308 #define MARKIDLE 8 /* Mark/flag on idle */ 309 #define GAOP 0x10 /* Go active on poll */ 310 #define NRZ 0 /* NRZ mode */ 311 #define NRZI 0x20 /* NRZI mode */ 312 #define FM1 0x40 /* FM1 (transition = 1) */ 313 #define FM0 0x60 /* FM0 (transition = 0) */ 314 #define CRCPS 0x80 /* CRC Preset I/O */ 315 316 /* Write Register 11 (Clock Mode control) */ 317 #define TRxCXT 0 /* TRxC = Xtal output */ 318 #define TRxCTC 1 /* TRxC = Transmit clock */ 319 #define TRxCBR 2 /* TRxC = BR Generator Output */ 320 #define TRxCDP 3 /* TRxC = DPLL output */ 321 #define TRxCOI 4 /* TRxC O/I */ 322 #define TCRTxCP 0 /* Transmit clock = RTxC pin */ 323 #define TCTRxCP 8 /* Transmit clock = TRxC pin */ 324 #define TCBR 0x10 /* Transmit clock = BR Generator output */ 325 #define TCDPLL 0x18 /* Transmit clock = DPLL output */ 326 #define RCRTxCP 0 /* Receive clock = RTxC pin */ 327 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */ 328 #define RCBR 0x40 /* Receive clock = BR Generator output */ 329 #define RCDPLL 0x60 /* Receive clock = DPLL output */ 330 #define RTxCX 0x80 /* RTxC Xtal/No Xtal */ 331 332 /* Write Register 12 (lower byte of baud rate generator time constant) */ 333 334 /* Write Register 13 (upper byte of baud rate generator time constant) */ 335 336 /* Write Register 14 (Misc control bits) */ 337 #define BRENABL 1 /* Baud rate generator enable */ 338 #define BRSRC 2 /* Baud rate generator source */ 339 #define DTRREQ 4 /* DTR/Request function */ 340 #define AUTOECHO 8 /* Auto Echo */ 341 #define LOOPBAK 0x10 /* Local loopback */ 342 #define SEARCH 0x20 /* Enter search mode */ 343 #define RMC 0x40 /* Reset missing clock */ 344 #define DISDPLL 0x60 /* Disable DPLL */ 345 #define SSBR 0x80 /* Set DPLL source = BR generator */ 346 #define SSRTxC 0xa0 /* Set DPLL source = RTxC */ 347 #define SFMM 0xc0 /* Set FM mode */ 348 #define SNRZI 0xe0 /* Set NRZI mode */ 349 350 /* Write Register 15 (external/status interrupt control) */ 351 #define ZCIE 2 /* Zero count IE */ 352 #define DCDIE 8 /* DCD IE */ 353 #define SYNCIE 0x10 /* Sync/hunt IE */ 354 #define CTSIE 0x20 /* CTS IE */ 355 #define TxUIE 0x40 /* Tx Underrun/EOM IE */ 356 #define BRKIE 0x80 /* Break/Abort IE */ 357 358 359 /* Read Register 0 */ 360 #define Rx_CH_AV 0x1 /* Rx Character Available */ 361 #define ZCOUNT 0x2 /* Zero count */ 362 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */ 363 #define DCD 0x8 /* DCD */ 364 #define SYNC_HUNT 0x10 /* Sync/hunt */ 365 #define CTS 0x20 /* CTS */ 366 #define TxEOM 0x40 /* Tx underrun */ 367 #define BRK_ABRT 0x80 /* Break/Abort */ 368 369 /* Read Register 1 */ 370 #define ALL_SNT 0x1 /* All sent */ 371 /* Residue Data for 8 Rx bits/char programmed */ 372 #define RES3 0x8 /* 0/3 */ 373 #define RES4 0x4 /* 0/4 */ 374 #define RES5 0xc /* 0/5 */ 375 #define RES6 0x2 /* 0/6 */ 376 #define RES7 0xa /* 0/7 */ 377 #define RES8 0x6 /* 0/8 */ 378 #define RES18 0xe /* 1/8 */ 379 #define RES28 0x0 /* 2/8 */ 380 /* Special Rx Condition Interrupts */ 381 #define PAR_ERR 0x10 /* Parity error */ 382 #define Rx_OVR 0x20 /* Rx Overrun Error */ 383 #define FRM_ERR 0x40 /* CRC/Framing Error */ 384 #define END_FR 0x80 /* End of Frame (SDLC) */ 385 386 /* Read Register 2 (channel b only) - Interrupt vector */ 387 388 /* Read Register 3 (interrupt pending register) ch a only */ 389 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */ 390 #define CHBTxIP 0x2 /* Channel B Tx IP */ 391 #define CHBRxIP 0x4 /* Channel B Rx IP */ 392 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */ 393 #define CHATxIP 0x10 /* Channel A Tx IP */ 394 #define CHARxIP 0x20 /* Channel A Rx IP */ 395 396 /* Read Register 8 (receive data register) */ 397 398 /* Read Register 10 (misc status bits) */ 399 #define ONLOOP 2 /* On loop */ 400 #define LOOPSEND 0x10 /* Loop sending */ 401 #define CLK2MIS 0x40 /* Two clocks missing */ 402 #define CLK1MIS 0x80 /* One clock missing */ 403 404 /* Read Register 12 (lower byte of baud rate generator constant) */ 405 406 /* Read Register 13 (upper byte of baud rate generator constant) */ 407 408 /* Read Register 15 (value of WR 15) */ 409 410 /* Misc macros */ 411 #define ZS_CLEARERR(channel) (write_zsreg(channel, 0, ERR_RES)) 412 #define ZS_CLEARFIFO(channel) do { volatile unsigned char garbage; \ 413 garbage = read_zsdata(channel); \ 414 garbage = read_zsdata(channel); \ 415 garbage = read_zsdata(channel); \ 416 } while(0) 417 418 #endif /* !(_DECSERIAL_H) */ 419