1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * drivers/soc/tegra/pmc.c
4  *
5  * Copyright (c) 2010 Google, Inc
6  * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
7  *
8  * Author:
9  *	Colin Cross <ccross@google.com>
10  */
11 
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
13 
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
26 #include <linux/io.h>
27 #include <linux/iopoll.h>
28 #include <linux/irqdomain.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/of_address.h>
32 #include <linux/of_clk.h>
33 #include <linux/of.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_platform.h>
36 #include <linux/pinctrl/pinconf-generic.h>
37 #include <linux/pinctrl/pinconf.h>
38 #include <linux/pinctrl/pinctrl.h>
39 #include <linux/platform_device.h>
40 #include <linux/pm_domain.h>
41 #include <linux/pm_opp.h>
42 #include <linux/power_supply.h>
43 #include <linux/reboot.h>
44 #include <linux/regmap.h>
45 #include <linux/reset.h>
46 #include <linux/seq_file.h>
47 #include <linux/slab.h>
48 #include <linux/spinlock.h>
49 
50 #include <soc/tegra/common.h>
51 #include <soc/tegra/fuse.h>
52 #include <soc/tegra/pmc.h>
53 
54 #include <dt-bindings/interrupt-controller/arm-gic.h>
55 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
56 #include <dt-bindings/gpio/tegra186-gpio.h>
57 #include <dt-bindings/gpio/tegra194-gpio.h>
58 #include <dt-bindings/gpio/tegra234-gpio.h>
59 #include <dt-bindings/soc/tegra-pmc.h>
60 
61 #define PMC_CNTRL			0x0
62 #define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */
63 #define  PMC_CNTRL_CPU_PWRREQ_OE	BIT(16) /* CPU pwr req enable */
64 #define  PMC_CNTRL_CPU_PWRREQ_POLARITY	BIT(15) /* CPU pwr req polarity */
65 #define  PMC_CNTRL_SIDE_EFFECT_LP0	BIT(14) /* LP0 when CPU pwr gated */
66 #define  PMC_CNTRL_SYSCLK_OE		BIT(11) /* system clock enable */
67 #define  PMC_CNTRL_SYSCLK_POLARITY	BIT(10) /* sys clk polarity */
68 #define  PMC_CNTRL_PWRREQ_POLARITY	BIT(8)
69 #define  PMC_CNTRL_BLINK_EN		7
70 #define  PMC_CNTRL_MAIN_RST		BIT(4)
71 
72 #define PMC_WAKE_MASK			0x0c
73 #define PMC_WAKE_LEVEL			0x10
74 #define PMC_WAKE_STATUS			0x14
75 #define PMC_SW_WAKE_STATUS		0x18
76 #define PMC_DPD_PADS_ORIDE		0x1c
77 #define  PMC_DPD_PADS_ORIDE_BLINK	20
78 
79 #define DPD_SAMPLE			0x020
80 #define  DPD_SAMPLE_ENABLE		BIT(0)
81 #define  DPD_SAMPLE_DISABLE		(0 << 0)
82 
83 #define PWRGATE_TOGGLE			0x30
84 #define  PWRGATE_TOGGLE_START		BIT(8)
85 
86 #define REMOVE_CLAMPING			0x34
87 
88 #define PWRGATE_STATUS			0x38
89 
90 #define PMC_BLINK_TIMER			0x40
91 #define PMC_IMPL_E_33V_PWR		0x40
92 
93 #define PMC_PWR_DET			0x48
94 
95 #define PMC_SCRATCH0_MODE_RECOVERY	BIT(31)
96 #define PMC_SCRATCH0_MODE_BOOTLOADER	BIT(30)
97 #define PMC_SCRATCH0_MODE_RCM		BIT(1)
98 #define PMC_SCRATCH0_MODE_MASK		(PMC_SCRATCH0_MODE_RECOVERY | \
99 					 PMC_SCRATCH0_MODE_BOOTLOADER | \
100 					 PMC_SCRATCH0_MODE_RCM)
101 
102 #define PMC_CPUPWRGOOD_TIMER		0xc8
103 #define PMC_CPUPWROFF_TIMER		0xcc
104 #define PMC_COREPWRGOOD_TIMER		0x3c
105 #define PMC_COREPWROFF_TIMER		0xe0
106 
107 #define PMC_PWR_DET_VALUE		0xe4
108 
109 #define PMC_USB_DEBOUNCE_DEL		0xec
110 #define PMC_USB_AO			0xf0
111 
112 #define PMC_SCRATCH37			0x130
113 #define PMC_SCRATCH41			0x140
114 
115 #define PMC_WAKE2_MASK			0x160
116 #define PMC_WAKE2_LEVEL			0x164
117 #define PMC_WAKE2_STATUS		0x168
118 #define PMC_SW_WAKE2_STATUS		0x16c
119 
120 #define PMC_CLK_OUT_CNTRL		0x1a8
121 #define  PMC_CLK_OUT_MUX_MASK		GENMASK(1, 0)
122 #define PMC_SENSOR_CTRL			0x1b0
123 #define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)
124 #define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)
125 
126 #define  PMC_RST_STATUS_POR		0
127 #define  PMC_RST_STATUS_WATCHDOG	1
128 #define  PMC_RST_STATUS_SENSOR		2
129 #define  PMC_RST_STATUS_SW_MAIN		3
130 #define  PMC_RST_STATUS_LP0		4
131 #define  PMC_RST_STATUS_AOTAG		5
132 
133 #define IO_DPD_REQ			0x1b8
134 #define  IO_DPD_REQ_CODE_IDLE		(0U << 30)
135 #define  IO_DPD_REQ_CODE_OFF		(1U << 30)
136 #define  IO_DPD_REQ_CODE_ON		(2U << 30)
137 #define  IO_DPD_REQ_CODE_MASK		(3U << 30)
138 
139 #define IO_DPD_STATUS			0x1bc
140 #define IO_DPD2_REQ			0x1c0
141 #define IO_DPD2_STATUS			0x1c4
142 #define SEL_DPD_TIM			0x1c8
143 
144 #define PMC_UTMIP_UHSIC_TRIGGERS	0x1ec
145 #define PMC_UTMIP_UHSIC_SAVED_STATE	0x1f0
146 
147 #define PMC_UTMIP_TERM_PAD_CFG		0x1f8
148 #define PMC_UTMIP_UHSIC_SLEEP_CFG	0x1fc
149 #define PMC_UTMIP_UHSIC_FAKE		0x218
150 
151 #define PMC_SCRATCH54			0x258
152 #define  PMC_SCRATCH54_DATA_SHIFT	8
153 #define  PMC_SCRATCH54_ADDR_SHIFT	0
154 
155 #define PMC_SCRATCH55			0x25c
156 #define  PMC_SCRATCH55_RESET_TEGRA	BIT(31)
157 #define  PMC_SCRATCH55_CNTRL_ID_SHIFT	27
158 #define  PMC_SCRATCH55_PINMUX_SHIFT	24
159 #define  PMC_SCRATCH55_16BITOP		BIT(15)
160 #define  PMC_SCRATCH55_CHECKSUM_SHIFT	16
161 #define  PMC_SCRATCH55_I2CSLV1_SHIFT	0
162 
163 #define  PMC_UTMIP_UHSIC_LINE_WAKEUP	0x26c
164 
165 #define PMC_UTMIP_BIAS_MASTER_CNTRL	0x270
166 #define PMC_UTMIP_MASTER_CONFIG		0x274
167 #define PMC_UTMIP_UHSIC2_TRIGGERS	0x27c
168 #define PMC_UTMIP_MASTER2_CONFIG	0x29c
169 
170 #define GPU_RG_CNTRL			0x2d4
171 
172 #define PMC_UTMIP_PAD_CFG0		0x4c0
173 #define PMC_UTMIP_UHSIC_SLEEP_CFG1	0x4d0
174 #define PMC_UTMIP_SLEEPWALK_P3		0x4e0
175 /* Tegra186 and later */
176 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
177 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
178 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
179 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
180 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
181 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
182 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
183 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
184 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
185 
186 #define WAKE_AOWAKE_CTRL 0x4f4
187 #define  WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
188 
189 /* for secure PMC */
190 #define TEGRA_SMC_PMC		0xc2fffe00
191 #define  TEGRA_SMC_PMC_READ	0xaa
192 #define  TEGRA_SMC_PMC_WRITE	0xbb
193 
194 struct pmc_clk {
195 	struct clk_hw	hw;
196 	unsigned long	offs;
197 	u32		mux_shift;
198 	u32		force_en_shift;
199 };
200 
201 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
202 
203 struct pmc_clk_gate {
204 	struct clk_hw	hw;
205 	unsigned long	offs;
206 	u32		shift;
207 };
208 
209 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
210 
211 struct pmc_clk_init_data {
212 	char *name;
213 	const char *const *parents;
214 	int num_parents;
215 	int clk_id;
216 	u8 mux_shift;
217 	u8 force_en_shift;
218 };
219 
220 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
221 	"osc_div4", "extern1",
222 };
223 
224 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
225 	"osc_div4", "extern2",
226 };
227 
228 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
229 	"osc_div4", "extern3",
230 };
231 
232 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
233 	{
234 		.name = "pmc_clk_out_1",
235 		.parents = clk_out1_parents,
236 		.num_parents = ARRAY_SIZE(clk_out1_parents),
237 		.clk_id = TEGRA_PMC_CLK_OUT_1,
238 		.mux_shift = 6,
239 		.force_en_shift = 2,
240 	},
241 	{
242 		.name = "pmc_clk_out_2",
243 		.parents = clk_out2_parents,
244 		.num_parents = ARRAY_SIZE(clk_out2_parents),
245 		.clk_id = TEGRA_PMC_CLK_OUT_2,
246 		.mux_shift = 14,
247 		.force_en_shift = 10,
248 	},
249 	{
250 		.name = "pmc_clk_out_3",
251 		.parents = clk_out3_parents,
252 		.num_parents = ARRAY_SIZE(clk_out3_parents),
253 		.clk_id = TEGRA_PMC_CLK_OUT_3,
254 		.mux_shift = 22,
255 		.force_en_shift = 18,
256 	},
257 };
258 
259 struct tegra_powergate {
260 	struct generic_pm_domain genpd;
261 	struct tegra_pmc *pmc;
262 	unsigned int id;
263 	struct clk **clks;
264 	unsigned int num_clks;
265 	unsigned long *clk_rates;
266 	struct reset_control *reset;
267 };
268 
269 struct tegra_io_pad_soc {
270 	enum tegra_io_pad id;
271 	unsigned int dpd;
272 	unsigned int voltage;
273 	const char *name;
274 };
275 
276 struct tegra_pmc_regs {
277 	unsigned int scratch0;
278 	unsigned int dpd_req;
279 	unsigned int dpd_status;
280 	unsigned int dpd2_req;
281 	unsigned int dpd2_status;
282 	unsigned int rst_status;
283 	unsigned int rst_source_shift;
284 	unsigned int rst_source_mask;
285 	unsigned int rst_level_shift;
286 	unsigned int rst_level_mask;
287 };
288 
289 struct tegra_wake_event {
290 	const char *name;
291 	unsigned int id;
292 	unsigned int irq;
293 	struct {
294 		unsigned int instance;
295 		unsigned int pin;
296 	} gpio;
297 };
298 
299 #define TEGRA_WAKE_SIMPLE(_name, _id)			\
300 	{						\
301 		.name = _name,				\
302 		.id = _id,				\
303 		.irq = 0,				\
304 		.gpio = {				\
305 			.instance = UINT_MAX,		\
306 			.pin = UINT_MAX,		\
307 		},					\
308 	}
309 
310 #define TEGRA_WAKE_IRQ(_name, _id, _irq)		\
311 	{						\
312 		.name = _name,				\
313 		.id = _id,				\
314 		.irq = _irq,				\
315 		.gpio = {				\
316 			.instance = UINT_MAX,		\
317 			.pin = UINT_MAX,		\
318 		},					\
319 	}
320 
321 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin)	\
322 	{						\
323 		.name = _name,				\
324 		.id = _id,				\
325 		.irq = 0,				\
326 		.gpio = {				\
327 			.instance = _instance,		\
328 			.pin = _pin,			\
329 		},					\
330 	}
331 
332 struct tegra_pmc_soc {
333 	unsigned int num_powergates;
334 	const char *const *powergates;
335 	unsigned int num_cpu_powergates;
336 	const u8 *cpu_powergates;
337 
338 	bool has_tsense_reset;
339 	bool has_gpu_clamps;
340 	bool needs_mbist_war;
341 	bool has_impl_33v_pwr;
342 	bool maybe_tz_only;
343 
344 	const struct tegra_io_pad_soc *io_pads;
345 	unsigned int num_io_pads;
346 
347 	const struct pinctrl_pin_desc *pin_descs;
348 	unsigned int num_pin_descs;
349 
350 	const struct tegra_pmc_regs *regs;
351 	void (*init)(struct tegra_pmc *pmc);
352 	void (*setup_irq_polarity)(struct tegra_pmc *pmc,
353 				   struct device_node *np,
354 				   bool invert);
355 	int (*irq_set_wake)(struct irq_data *data, unsigned int on);
356 	int (*irq_set_type)(struct irq_data *data, unsigned int type);
357 	int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
358 			     bool new_state);
359 
360 	const char * const *reset_sources;
361 	unsigned int num_reset_sources;
362 	const char * const *reset_levels;
363 	unsigned int num_reset_levels;
364 
365 	/*
366 	 * These describe events that can wake the system from sleep (i.e.
367 	 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
368 	 * are dealt with in the LIC.
369 	 */
370 	const struct tegra_wake_event *wake_events;
371 	unsigned int num_wake_events;
372 
373 	const struct pmc_clk_init_data *pmc_clks_data;
374 	unsigned int num_pmc_clks;
375 	bool has_blink_output;
376 	bool has_usb_sleepwalk;
377 	bool supports_core_domain;
378 };
379 
380 /**
381  * struct tegra_pmc - NVIDIA Tegra PMC
382  * @dev: pointer to PMC device structure
383  * @base: pointer to I/O remapped register region
384  * @wake: pointer to I/O remapped region for WAKE registers
385  * @aotag: pointer to I/O remapped region for AOTAG registers
386  * @scratch: pointer to I/O remapped region for scratch registers
387  * @clk: pointer to pclk clock
388  * @soc: pointer to SoC data structure
389  * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
390  * @debugfs: pointer to debugfs entry
391  * @rate: currently configured rate of pclk
392  * @suspend_mode: lowest suspend mode available
393  * @cpu_good_time: CPU power good time (in microseconds)
394  * @cpu_off_time: CPU power off time (in microsecends)
395  * @core_osc_time: core power good OSC time (in microseconds)
396  * @core_pmu_time: core power good PMU time (in microseconds)
397  * @core_off_time: core power off time (in microseconds)
398  * @corereq_high: core power request is active-high
399  * @sysclkreq_high: system clock request is active-high
400  * @combined_req: combined power request for CPU & core
401  * @cpu_pwr_good_en: CPU power good signal is enabled
402  * @lp0_vec_phys: physical base address of the LP0 warm boot code
403  * @lp0_vec_size: size of the LP0 warm boot code
404  * @powergates_available: Bitmap of available power gates
405  * @powergates_lock: mutex for power gate register access
406  * @pctl_dev: pin controller exposed by the PMC
407  * @domain: IRQ domain provided by the PMC
408  * @irq: chip implementation for the IRQ domain
409  * @clk_nb: pclk clock changes handler
410  * @core_domain_state_synced: flag marking the core domain's state as synced
411  * @core_domain_registered: flag marking the core domain as registered
412  */
413 struct tegra_pmc {
414 	struct device *dev;
415 	void __iomem *base;
416 	void __iomem *wake;
417 	void __iomem *aotag;
418 	void __iomem *scratch;
419 	struct clk *clk;
420 	struct dentry *debugfs;
421 
422 	const struct tegra_pmc_soc *soc;
423 	bool tz_only;
424 
425 	unsigned long rate;
426 
427 	enum tegra_suspend_mode suspend_mode;
428 	u32 cpu_good_time;
429 	u32 cpu_off_time;
430 	u32 core_osc_time;
431 	u32 core_pmu_time;
432 	u32 core_off_time;
433 	bool corereq_high;
434 	bool sysclkreq_high;
435 	bool combined_req;
436 	bool cpu_pwr_good_en;
437 	u32 lp0_vec_phys;
438 	u32 lp0_vec_size;
439 	DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
440 
441 	struct mutex powergates_lock;
442 
443 	struct pinctrl_dev *pctl_dev;
444 
445 	struct irq_domain *domain;
446 	struct irq_chip irq;
447 
448 	struct notifier_block clk_nb;
449 
450 	bool core_domain_state_synced;
451 	bool core_domain_registered;
452 };
453 
454 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
455 	.base = NULL,
456 	.suspend_mode = TEGRA_SUSPEND_NOT_READY,
457 };
458 
459 static inline struct tegra_powergate *
to_powergate(struct generic_pm_domain * domain)460 to_powergate(struct generic_pm_domain *domain)
461 {
462 	return container_of(domain, struct tegra_powergate, genpd);
463 }
464 
tegra_pmc_readl(struct tegra_pmc * pmc,unsigned long offset)465 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
466 {
467 	struct arm_smccc_res res;
468 
469 	if (pmc->tz_only) {
470 		arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
471 			      0, 0, 0, &res);
472 		if (res.a0) {
473 			if (pmc->dev)
474 				dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
475 					 __func__, res.a0);
476 			else
477 				pr_warn("%s(): SMC failed: %lu\n", __func__,
478 					res.a0);
479 		}
480 
481 		return res.a1;
482 	}
483 
484 	return readl(pmc->base + offset);
485 }
486 
tegra_pmc_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)487 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
488 			     unsigned long offset)
489 {
490 	struct arm_smccc_res res;
491 
492 	if (pmc->tz_only) {
493 		arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
494 			      value, 0, 0, 0, 0, &res);
495 		if (res.a0) {
496 			if (pmc->dev)
497 				dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
498 					 __func__, res.a0);
499 			else
500 				pr_warn("%s(): SMC failed: %lu\n", __func__,
501 					res.a0);
502 		}
503 	} else {
504 		writel(value, pmc->base + offset);
505 	}
506 }
507 
tegra_pmc_scratch_readl(struct tegra_pmc * pmc,unsigned long offset)508 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
509 {
510 	if (pmc->tz_only)
511 		return tegra_pmc_readl(pmc, offset);
512 
513 	return readl(pmc->scratch + offset);
514 }
515 
tegra_pmc_scratch_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)516 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
517 				     unsigned long offset)
518 {
519 	if (pmc->tz_only)
520 		tegra_pmc_writel(pmc, value, offset);
521 	else
522 		writel(value, pmc->scratch + offset);
523 }
524 
525 /*
526  * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
527  * This currently doesn't work because readx_poll_timeout() can only operate
528  * on functions that take a single argument.
529  */
tegra_powergate_state(int id)530 static inline bool tegra_powergate_state(int id)
531 {
532 	if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
533 		return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
534 	else
535 		return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
536 }
537 
tegra_powergate_is_valid(struct tegra_pmc * pmc,int id)538 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
539 {
540 	return (pmc->soc && pmc->soc->powergates[id]);
541 }
542 
tegra_powergate_is_available(struct tegra_pmc * pmc,int id)543 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
544 {
545 	return test_bit(id, pmc->powergates_available);
546 }
547 
tegra_powergate_lookup(struct tegra_pmc * pmc,const char * name)548 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
549 {
550 	unsigned int i;
551 
552 	if (!pmc || !pmc->soc || !name)
553 		return -EINVAL;
554 
555 	for (i = 0; i < pmc->soc->num_powergates; i++) {
556 		if (!tegra_powergate_is_valid(pmc, i))
557 			continue;
558 
559 		if (!strcmp(name, pmc->soc->powergates[i]))
560 			return i;
561 	}
562 
563 	return -ENODEV;
564 }
565 
tegra20_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)566 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
567 				 bool new_state)
568 {
569 	unsigned int retries = 100;
570 	bool status;
571 	int ret;
572 
573 	/*
574 	 * As per TRM documentation, the toggle command will be dropped by PMC
575 	 * if there is contention with a HW-initiated toggling (i.e. CPU core
576 	 * power-gated), the command should be retried in that case.
577 	 */
578 	do {
579 		tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
580 
581 		/* wait for PMC to execute the command */
582 		ret = readx_poll_timeout(tegra_powergate_state, id, status,
583 					 status == new_state, 1, 10);
584 	} while (ret == -ETIMEDOUT && retries--);
585 
586 	return ret;
587 }
588 
tegra_powergate_toggle_ready(struct tegra_pmc * pmc)589 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
590 {
591 	return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
592 }
593 
tegra114_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)594 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
595 				  bool new_state)
596 {
597 	bool status;
598 	int err;
599 
600 	/* wait while PMC power gating is contended */
601 	err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
602 				 status == true, 1, 100);
603 	if (err)
604 		return err;
605 
606 	tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
607 
608 	/* wait for PMC to accept the command */
609 	err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
610 				 status == true, 1, 100);
611 	if (err)
612 		return err;
613 
614 	/* wait for PMC to execute the command */
615 	err = readx_poll_timeout(tegra_powergate_state, id, status,
616 				 status == new_state, 10, 100000);
617 	if (err)
618 		return err;
619 
620 	return 0;
621 }
622 
623 /**
624  * tegra_powergate_set() - set the state of a partition
625  * @pmc: power management controller
626  * @id: partition ID
627  * @new_state: new state of the partition
628  */
tegra_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)629 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
630 			       bool new_state)
631 {
632 	int err;
633 
634 	if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
635 		return -EINVAL;
636 
637 	mutex_lock(&pmc->powergates_lock);
638 
639 	if (tegra_powergate_state(id) == new_state) {
640 		mutex_unlock(&pmc->powergates_lock);
641 		return 0;
642 	}
643 
644 	err = pmc->soc->powergate_set(pmc, id, new_state);
645 
646 	mutex_unlock(&pmc->powergates_lock);
647 
648 	return err;
649 }
650 
__tegra_powergate_remove_clamping(struct tegra_pmc * pmc,unsigned int id)651 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
652 					     unsigned int id)
653 {
654 	u32 mask;
655 
656 	mutex_lock(&pmc->powergates_lock);
657 
658 	/*
659 	 * On Tegra124 and later, the clamps for the GPU are controlled by a
660 	 * separate register (with different semantics).
661 	 */
662 	if (id == TEGRA_POWERGATE_3D) {
663 		if (pmc->soc->has_gpu_clamps) {
664 			tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
665 			goto out;
666 		}
667 	}
668 
669 	/*
670 	 * Tegra 2 has a bug where PCIE and VDE clamping masks are
671 	 * swapped relatively to the partition ids
672 	 */
673 	if (id == TEGRA_POWERGATE_VDEC)
674 		mask = (1 << TEGRA_POWERGATE_PCIE);
675 	else if (id == TEGRA_POWERGATE_PCIE)
676 		mask = (1 << TEGRA_POWERGATE_VDEC);
677 	else
678 		mask = (1 << id);
679 
680 	tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
681 
682 out:
683 	mutex_unlock(&pmc->powergates_lock);
684 
685 	return 0;
686 }
687 
tegra_powergate_prepare_clocks(struct tegra_powergate * pg)688 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
689 {
690 	unsigned long safe_rate = 100 * 1000 * 1000;
691 	unsigned int i;
692 	int err;
693 
694 	for (i = 0; i < pg->num_clks; i++) {
695 		pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
696 
697 		if (!pg->clk_rates[i]) {
698 			err = -EINVAL;
699 			goto out;
700 		}
701 
702 		if (pg->clk_rates[i] <= safe_rate)
703 			continue;
704 
705 		/*
706 		 * We don't know whether voltage state is okay for the
707 		 * current clock rate, hence it's better to temporally
708 		 * switch clock to a safe rate which is suitable for
709 		 * all voltages, before enabling the clock.
710 		 */
711 		err = clk_set_rate(pg->clks[i], safe_rate);
712 		if (err)
713 			goto out;
714 	}
715 
716 	return 0;
717 
718 out:
719 	while (i--)
720 		clk_set_rate(pg->clks[i], pg->clk_rates[i]);
721 
722 	return err;
723 }
724 
tegra_powergate_unprepare_clocks(struct tegra_powergate * pg)725 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
726 {
727 	unsigned int i;
728 	int err;
729 
730 	for (i = 0; i < pg->num_clks; i++) {
731 		err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
732 		if (err)
733 			return err;
734 	}
735 
736 	return 0;
737 }
738 
tegra_powergate_disable_clocks(struct tegra_powergate * pg)739 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
740 {
741 	unsigned int i;
742 
743 	for (i = 0; i < pg->num_clks; i++)
744 		clk_disable_unprepare(pg->clks[i]);
745 }
746 
tegra_powergate_enable_clocks(struct tegra_powergate * pg)747 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
748 {
749 	unsigned int i;
750 	int err;
751 
752 	for (i = 0; i < pg->num_clks; i++) {
753 		err = clk_prepare_enable(pg->clks[i]);
754 		if (err)
755 			goto out;
756 	}
757 
758 	return 0;
759 
760 out:
761 	while (i--)
762 		clk_disable_unprepare(pg->clks[i]);
763 
764 	return err;
765 }
766 
tegra_powergate_power_up(struct tegra_powergate * pg,bool disable_clocks)767 static int tegra_powergate_power_up(struct tegra_powergate *pg,
768 				    bool disable_clocks)
769 {
770 	int err;
771 
772 	err = reset_control_assert(pg->reset);
773 	if (err)
774 		return err;
775 
776 	usleep_range(10, 20);
777 
778 	err = tegra_powergate_set(pg->pmc, pg->id, true);
779 	if (err < 0)
780 		return err;
781 
782 	usleep_range(10, 20);
783 
784 	err = tegra_powergate_prepare_clocks(pg);
785 	if (err)
786 		goto powergate_off;
787 
788 	err = tegra_powergate_enable_clocks(pg);
789 	if (err)
790 		goto unprepare_clks;
791 
792 	usleep_range(10, 20);
793 
794 	err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
795 	if (err)
796 		goto disable_clks;
797 
798 	usleep_range(10, 20);
799 
800 	err = reset_control_deassert(pg->reset);
801 	if (err)
802 		goto disable_clks;
803 
804 	usleep_range(10, 20);
805 
806 	if (pg->pmc->soc->needs_mbist_war)
807 		err = tegra210_clk_handle_mbist_war(pg->id);
808 	if (err)
809 		goto disable_clks;
810 
811 	if (disable_clocks)
812 		tegra_powergate_disable_clocks(pg);
813 
814 	err = tegra_powergate_unprepare_clocks(pg);
815 	if (err)
816 		return err;
817 
818 	return 0;
819 
820 disable_clks:
821 	tegra_powergate_disable_clocks(pg);
822 	usleep_range(10, 20);
823 
824 unprepare_clks:
825 	tegra_powergate_unprepare_clocks(pg);
826 
827 powergate_off:
828 	tegra_powergate_set(pg->pmc, pg->id, false);
829 
830 	return err;
831 }
832 
tegra_powergate_power_down(struct tegra_powergate * pg)833 static int tegra_powergate_power_down(struct tegra_powergate *pg)
834 {
835 	int err;
836 
837 	err = tegra_powergate_prepare_clocks(pg);
838 	if (err)
839 		return err;
840 
841 	err = tegra_powergate_enable_clocks(pg);
842 	if (err)
843 		goto unprepare_clks;
844 
845 	usleep_range(10, 20);
846 
847 	err = reset_control_assert(pg->reset);
848 	if (err)
849 		goto disable_clks;
850 
851 	usleep_range(10, 20);
852 
853 	tegra_powergate_disable_clocks(pg);
854 
855 	usleep_range(10, 20);
856 
857 	err = tegra_powergate_set(pg->pmc, pg->id, false);
858 	if (err)
859 		goto assert_resets;
860 
861 	err = tegra_powergate_unprepare_clocks(pg);
862 	if (err)
863 		return err;
864 
865 	return 0;
866 
867 assert_resets:
868 	tegra_powergate_enable_clocks(pg);
869 	usleep_range(10, 20);
870 	reset_control_deassert(pg->reset);
871 	usleep_range(10, 20);
872 
873 disable_clks:
874 	tegra_powergate_disable_clocks(pg);
875 
876 unprepare_clks:
877 	tegra_powergate_unprepare_clocks(pg);
878 
879 	return err;
880 }
881 
tegra_genpd_power_on(struct generic_pm_domain * domain)882 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
883 {
884 	struct tegra_powergate *pg = to_powergate(domain);
885 	struct device *dev = pg->pmc->dev;
886 	int err;
887 
888 	err = tegra_powergate_power_up(pg, true);
889 	if (err) {
890 		dev_err(dev, "failed to turn on PM domain %s: %d\n",
891 			pg->genpd.name, err);
892 		goto out;
893 	}
894 
895 	reset_control_release(pg->reset);
896 
897 out:
898 	return err;
899 }
900 
tegra_genpd_power_off(struct generic_pm_domain * domain)901 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
902 {
903 	struct tegra_powergate *pg = to_powergate(domain);
904 	struct device *dev = pg->pmc->dev;
905 	int err;
906 
907 	err = reset_control_acquire(pg->reset);
908 	if (err < 0) {
909 		dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
910 			pg->genpd.name, err);
911 		return err;
912 	}
913 
914 	err = tegra_powergate_power_down(pg);
915 	if (err) {
916 		dev_err(dev, "failed to turn off PM domain %s: %d\n",
917 			pg->genpd.name, err);
918 		reset_control_release(pg->reset);
919 	}
920 
921 	return err;
922 }
923 
924 /**
925  * tegra_powergate_power_on() - power on partition
926  * @id: partition ID
927  */
tegra_powergate_power_on(unsigned int id)928 int tegra_powergate_power_on(unsigned int id)
929 {
930 	if (!tegra_powergate_is_available(pmc, id))
931 		return -EINVAL;
932 
933 	return tegra_powergate_set(pmc, id, true);
934 }
935 EXPORT_SYMBOL(tegra_powergate_power_on);
936 
937 /**
938  * tegra_powergate_power_off() - power off partition
939  * @id: partition ID
940  */
tegra_powergate_power_off(unsigned int id)941 int tegra_powergate_power_off(unsigned int id)
942 {
943 	if (!tegra_powergate_is_available(pmc, id))
944 		return -EINVAL;
945 
946 	return tegra_powergate_set(pmc, id, false);
947 }
948 EXPORT_SYMBOL(tegra_powergate_power_off);
949 
950 /**
951  * tegra_powergate_is_powered() - check if partition is powered
952  * @pmc: power management controller
953  * @id: partition ID
954  */
tegra_powergate_is_powered(struct tegra_pmc * pmc,unsigned int id)955 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
956 {
957 	if (!tegra_powergate_is_valid(pmc, id))
958 		return -EINVAL;
959 
960 	return tegra_powergate_state(id);
961 }
962 
963 /**
964  * tegra_powergate_remove_clamping() - remove power clamps for partition
965  * @id: partition ID
966  */
tegra_powergate_remove_clamping(unsigned int id)967 int tegra_powergate_remove_clamping(unsigned int id)
968 {
969 	if (!tegra_powergate_is_available(pmc, id))
970 		return -EINVAL;
971 
972 	return __tegra_powergate_remove_clamping(pmc, id);
973 }
974 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
975 
976 /**
977  * tegra_powergate_sequence_power_up() - power up partition
978  * @id: partition ID
979  * @clk: clock for partition
980  * @rst: reset for partition
981  *
982  * Must be called with clk disabled, and returns with clk enabled.
983  */
tegra_powergate_sequence_power_up(unsigned int id,struct clk * clk,struct reset_control * rst)984 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
985 				      struct reset_control *rst)
986 {
987 	struct tegra_powergate *pg;
988 	int err;
989 
990 	if (!tegra_powergate_is_available(pmc, id))
991 		return -EINVAL;
992 
993 	pg = kzalloc(sizeof(*pg), GFP_KERNEL);
994 	if (!pg)
995 		return -ENOMEM;
996 
997 	pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
998 	if (!pg->clk_rates) {
999 		kfree(pg->clks);
1000 		return -ENOMEM;
1001 	}
1002 
1003 	pg->id = id;
1004 	pg->clks = &clk;
1005 	pg->num_clks = 1;
1006 	pg->reset = rst;
1007 	pg->pmc = pmc;
1008 
1009 	err = tegra_powergate_power_up(pg, false);
1010 	if (err)
1011 		dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
1012 			err);
1013 
1014 	kfree(pg->clk_rates);
1015 	kfree(pg);
1016 
1017 	return err;
1018 }
1019 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1020 
1021 /**
1022  * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1023  * @pmc: power management controller
1024  * @cpuid: CPU partition ID
1025  *
1026  * Returns the partition ID corresponding to the CPU partition ID or a
1027  * negative error code on failure.
1028  */
tegra_get_cpu_powergate_id(struct tegra_pmc * pmc,unsigned int cpuid)1029 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1030 				      unsigned int cpuid)
1031 {
1032 	if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1033 		return pmc->soc->cpu_powergates[cpuid];
1034 
1035 	return -EINVAL;
1036 }
1037 
1038 /**
1039  * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1040  * @cpuid: CPU partition ID
1041  */
tegra_pmc_cpu_is_powered(unsigned int cpuid)1042 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1043 {
1044 	int id;
1045 
1046 	id = tegra_get_cpu_powergate_id(pmc, cpuid);
1047 	if (id < 0)
1048 		return false;
1049 
1050 	return tegra_powergate_is_powered(pmc, id);
1051 }
1052 
1053 /**
1054  * tegra_pmc_cpu_power_on() - power on CPU partition
1055  * @cpuid: CPU partition ID
1056  */
tegra_pmc_cpu_power_on(unsigned int cpuid)1057 int tegra_pmc_cpu_power_on(unsigned int cpuid)
1058 {
1059 	int id;
1060 
1061 	id = tegra_get_cpu_powergate_id(pmc, cpuid);
1062 	if (id < 0)
1063 		return id;
1064 
1065 	return tegra_powergate_set(pmc, id, true);
1066 }
1067 
1068 /**
1069  * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1070  * @cpuid: CPU partition ID
1071  */
tegra_pmc_cpu_remove_clamping(unsigned int cpuid)1072 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1073 {
1074 	int id;
1075 
1076 	id = tegra_get_cpu_powergate_id(pmc, cpuid);
1077 	if (id < 0)
1078 		return id;
1079 
1080 	return tegra_powergate_remove_clamping(id);
1081 }
1082 
tegra_pmc_program_reboot_reason(const char * cmd)1083 static void tegra_pmc_program_reboot_reason(const char *cmd)
1084 {
1085 	u32 value;
1086 
1087 	value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1088 	value &= ~PMC_SCRATCH0_MODE_MASK;
1089 
1090 	if (cmd) {
1091 		if (strcmp(cmd, "recovery") == 0)
1092 			value |= PMC_SCRATCH0_MODE_RECOVERY;
1093 
1094 		if (strcmp(cmd, "bootloader") == 0)
1095 			value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1096 
1097 		if (strcmp(cmd, "forced-recovery") == 0)
1098 			value |= PMC_SCRATCH0_MODE_RCM;
1099 	}
1100 
1101 	tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1102 }
1103 
tegra_pmc_reboot_notify(struct notifier_block * this,unsigned long action,void * data)1104 static int tegra_pmc_reboot_notify(struct notifier_block *this,
1105 				   unsigned long action, void *data)
1106 {
1107 	if (action == SYS_RESTART)
1108 		tegra_pmc_program_reboot_reason(data);
1109 
1110 	return NOTIFY_DONE;
1111 }
1112 
1113 static struct notifier_block tegra_pmc_reboot_notifier = {
1114 	.notifier_call = tegra_pmc_reboot_notify,
1115 };
1116 
tegra_pmc_restart(void)1117 static void tegra_pmc_restart(void)
1118 {
1119 	u32 value;
1120 
1121 	/* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
1122 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
1123 	value |= PMC_CNTRL_MAIN_RST;
1124 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
1125 }
1126 
tegra_pmc_restart_handler(struct sys_off_data * data)1127 static int tegra_pmc_restart_handler(struct sys_off_data *data)
1128 {
1129 	tegra_pmc_restart();
1130 
1131 	return NOTIFY_DONE;
1132 }
1133 
tegra_pmc_power_off_handler(struct sys_off_data * data)1134 static int tegra_pmc_power_off_handler(struct sys_off_data *data)
1135 {
1136 	/*
1137 	 * Reboot Nexus 7 into special bootloader mode if USB cable is
1138 	 * connected in order to display battery status and power off.
1139 	 */
1140 	if (of_machine_is_compatible("asus,grouper") &&
1141 	    power_supply_is_system_supplied()) {
1142 		const u32 go_to_charger_mode = 0xa5a55a5a;
1143 
1144 		tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37);
1145 		tegra_pmc_restart();
1146 	}
1147 
1148 	return NOTIFY_DONE;
1149 }
1150 
powergate_show(struct seq_file * s,void * data)1151 static int powergate_show(struct seq_file *s, void *data)
1152 {
1153 	unsigned int i;
1154 	int status;
1155 
1156 	seq_printf(s, " powergate powered\n");
1157 	seq_printf(s, "------------------\n");
1158 
1159 	for (i = 0; i < pmc->soc->num_powergates; i++) {
1160 		status = tegra_powergate_is_powered(pmc, i);
1161 		if (status < 0)
1162 			continue;
1163 
1164 		seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1165 			   status ? "yes" : "no");
1166 	}
1167 
1168 	return 0;
1169 }
1170 
1171 DEFINE_SHOW_ATTRIBUTE(powergate);
1172 
tegra_powergate_debugfs_init(void)1173 static int tegra_powergate_debugfs_init(void)
1174 {
1175 	pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1176 					   &powergate_fops);
1177 	if (!pmc->debugfs)
1178 		return -ENOMEM;
1179 
1180 	return 0;
1181 }
1182 
tegra_powergate_of_get_clks(struct tegra_powergate * pg,struct device_node * np)1183 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1184 				       struct device_node *np)
1185 {
1186 	struct clk *clk;
1187 	unsigned int i, count;
1188 	int err;
1189 
1190 	count = of_clk_get_parent_count(np);
1191 	if (count == 0)
1192 		return -ENODEV;
1193 
1194 	pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1195 	if (!pg->clks)
1196 		return -ENOMEM;
1197 
1198 	pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1199 	if (!pg->clk_rates) {
1200 		kfree(pg->clks);
1201 		return -ENOMEM;
1202 	}
1203 
1204 	for (i = 0; i < count; i++) {
1205 		pg->clks[i] = of_clk_get(np, i);
1206 		if (IS_ERR(pg->clks[i])) {
1207 			err = PTR_ERR(pg->clks[i]);
1208 			goto err;
1209 		}
1210 	}
1211 
1212 	pg->num_clks = count;
1213 
1214 	return 0;
1215 
1216 err:
1217 	while (i--)
1218 		clk_put(pg->clks[i]);
1219 
1220 	kfree(pg->clk_rates);
1221 	kfree(pg->clks);
1222 
1223 	return err;
1224 }
1225 
tegra_powergate_of_get_resets(struct tegra_powergate * pg,struct device_node * np,bool off)1226 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1227 					 struct device_node *np, bool off)
1228 {
1229 	struct device *dev = pg->pmc->dev;
1230 	int err;
1231 
1232 	pg->reset = of_reset_control_array_get_exclusive_released(np);
1233 	if (IS_ERR(pg->reset)) {
1234 		err = PTR_ERR(pg->reset);
1235 		dev_err(dev, "failed to get device resets: %d\n", err);
1236 		return err;
1237 	}
1238 
1239 	err = reset_control_acquire(pg->reset);
1240 	if (err < 0) {
1241 		pr_err("failed to acquire resets: %d\n", err);
1242 		goto out;
1243 	}
1244 
1245 	if (off) {
1246 		err = reset_control_assert(pg->reset);
1247 	} else {
1248 		err = reset_control_deassert(pg->reset);
1249 		if (err < 0)
1250 			goto out;
1251 
1252 		reset_control_release(pg->reset);
1253 	}
1254 
1255 out:
1256 	if (err) {
1257 		reset_control_release(pg->reset);
1258 		reset_control_put(pg->reset);
1259 	}
1260 
1261 	return err;
1262 }
1263 
tegra_powergate_add(struct tegra_pmc * pmc,struct device_node * np)1264 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1265 {
1266 	struct device *dev = pmc->dev;
1267 	struct tegra_powergate *pg;
1268 	int id, err = 0;
1269 	bool off;
1270 
1271 	pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1272 	if (!pg)
1273 		return -ENOMEM;
1274 
1275 	id = tegra_powergate_lookup(pmc, np->name);
1276 	if (id < 0) {
1277 		dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1278 		err = -ENODEV;
1279 		goto free_mem;
1280 	}
1281 
1282 	/*
1283 	 * Clear the bit for this powergate so it cannot be managed
1284 	 * directly via the legacy APIs for controlling powergates.
1285 	 */
1286 	clear_bit(id, pmc->powergates_available);
1287 
1288 	pg->id = id;
1289 	pg->genpd.name = np->name;
1290 	pg->genpd.power_off = tegra_genpd_power_off;
1291 	pg->genpd.power_on = tegra_genpd_power_on;
1292 	pg->pmc = pmc;
1293 
1294 	off = !tegra_powergate_is_powered(pmc, pg->id);
1295 
1296 	err = tegra_powergate_of_get_clks(pg, np);
1297 	if (err < 0) {
1298 		dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1299 		goto set_available;
1300 	}
1301 
1302 	err = tegra_powergate_of_get_resets(pg, np, off);
1303 	if (err < 0) {
1304 		dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1305 		goto remove_clks;
1306 	}
1307 
1308 	if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1309 		if (off)
1310 			WARN_ON(tegra_powergate_power_up(pg, true));
1311 
1312 		goto remove_resets;
1313 	}
1314 
1315 	err = pm_genpd_init(&pg->genpd, NULL, off);
1316 	if (err < 0) {
1317 		dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1318 		       err);
1319 		goto remove_resets;
1320 	}
1321 
1322 	err = of_genpd_add_provider_simple(np, &pg->genpd);
1323 	if (err < 0) {
1324 		dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1325 			np, err);
1326 		goto remove_genpd;
1327 	}
1328 
1329 	dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1330 
1331 	return 0;
1332 
1333 remove_genpd:
1334 	pm_genpd_remove(&pg->genpd);
1335 
1336 remove_resets:
1337 	reset_control_put(pg->reset);
1338 
1339 remove_clks:
1340 	while (pg->num_clks--)
1341 		clk_put(pg->clks[pg->num_clks]);
1342 
1343 	kfree(pg->clks);
1344 
1345 set_available:
1346 	set_bit(id, pmc->powergates_available);
1347 
1348 free_mem:
1349 	kfree(pg);
1350 
1351 	return err;
1352 }
1353 
tegra_pmc_core_domain_state_synced(void)1354 bool tegra_pmc_core_domain_state_synced(void)
1355 {
1356 	return pmc->core_domain_state_synced;
1357 }
1358 
1359 static int
tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain * genpd,unsigned int level)1360 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd,
1361 					unsigned int level)
1362 {
1363 	struct dev_pm_opp *opp;
1364 	int err;
1365 
1366 	opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
1367 	if (IS_ERR(opp)) {
1368 		dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
1369 			level, opp);
1370 		return PTR_ERR(opp);
1371 	}
1372 
1373 	mutex_lock(&pmc->powergates_lock);
1374 	err = dev_pm_opp_set_opp(pmc->dev, opp);
1375 	mutex_unlock(&pmc->powergates_lock);
1376 
1377 	dev_pm_opp_put(opp);
1378 
1379 	if (err) {
1380 		dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
1381 			level, err);
1382 		return err;
1383 	}
1384 
1385 	return 0;
1386 }
1387 
1388 static unsigned int
tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain * genpd,struct dev_pm_opp * opp)1389 tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd,
1390 					   struct dev_pm_opp *opp)
1391 {
1392 	return dev_pm_opp_get_level(opp);
1393 }
1394 
tegra_pmc_core_pd_add(struct tegra_pmc * pmc,struct device_node * np)1395 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
1396 {
1397 	struct generic_pm_domain *genpd;
1398 	const char *rname[] = { "core", NULL};
1399 	int err;
1400 
1401 	genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);
1402 	if (!genpd)
1403 		return -ENOMEM;
1404 
1405 	genpd->name = "core";
1406 	genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;
1407 	genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state;
1408 
1409 	err = devm_pm_opp_set_regulators(pmc->dev, rname);
1410 	if (err)
1411 		return dev_err_probe(pmc->dev, err,
1412 				     "failed to set core OPP regulator\n");
1413 
1414 	err = pm_genpd_init(genpd, NULL, false);
1415 	if (err) {
1416 		dev_err(pmc->dev, "failed to init core genpd: %d\n", err);
1417 		return err;
1418 	}
1419 
1420 	err = of_genpd_add_provider_simple(np, genpd);
1421 	if (err) {
1422 		dev_err(pmc->dev, "failed to add core genpd: %d\n", err);
1423 		goto remove_genpd;
1424 	}
1425 
1426 	pmc->core_domain_registered = true;
1427 
1428 	return 0;
1429 
1430 remove_genpd:
1431 	pm_genpd_remove(genpd);
1432 
1433 	return err;
1434 }
1435 
tegra_powergate_init(struct tegra_pmc * pmc,struct device_node * parent)1436 static int tegra_powergate_init(struct tegra_pmc *pmc,
1437 				struct device_node *parent)
1438 {
1439 	struct of_phandle_args child_args, parent_args;
1440 	struct device_node *np, *child;
1441 	int err = 0;
1442 
1443 	/*
1444 	 * Core power domain is the parent of powergate domains, hence it
1445 	 * should be registered first.
1446 	 */
1447 	np = of_get_child_by_name(parent, "core-domain");
1448 	if (np) {
1449 		err = tegra_pmc_core_pd_add(pmc, np);
1450 		of_node_put(np);
1451 		if (err)
1452 			return err;
1453 	}
1454 
1455 	np = of_get_child_by_name(parent, "powergates");
1456 	if (!np)
1457 		return 0;
1458 
1459 	for_each_child_of_node(np, child) {
1460 		err = tegra_powergate_add(pmc, child);
1461 		if (err < 0) {
1462 			of_node_put(child);
1463 			break;
1464 		}
1465 
1466 		if (of_parse_phandle_with_args(child, "power-domains",
1467 					       "#power-domain-cells",
1468 					       0, &parent_args))
1469 			continue;
1470 
1471 		child_args.np = child;
1472 		child_args.args_count = 0;
1473 
1474 		err = of_genpd_add_subdomain(&parent_args, &child_args);
1475 		of_node_put(parent_args.np);
1476 		if (err) {
1477 			of_node_put(child);
1478 			break;
1479 		}
1480 	}
1481 
1482 	of_node_put(np);
1483 
1484 	return err;
1485 }
1486 
tegra_powergate_remove(struct generic_pm_domain * genpd)1487 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1488 {
1489 	struct tegra_powergate *pg = to_powergate(genpd);
1490 
1491 	reset_control_put(pg->reset);
1492 
1493 	while (pg->num_clks--)
1494 		clk_put(pg->clks[pg->num_clks]);
1495 
1496 	kfree(pg->clks);
1497 
1498 	set_bit(pg->id, pmc->powergates_available);
1499 
1500 	kfree(pg);
1501 }
1502 
tegra_powergate_remove_all(struct device_node * parent)1503 static void tegra_powergate_remove_all(struct device_node *parent)
1504 {
1505 	struct generic_pm_domain *genpd;
1506 	struct device_node *np, *child;
1507 
1508 	np = of_get_child_by_name(parent, "powergates");
1509 	if (!np)
1510 		return;
1511 
1512 	for_each_child_of_node(np, child) {
1513 		of_genpd_del_provider(child);
1514 
1515 		genpd = of_genpd_remove_last(child);
1516 		if (IS_ERR(genpd))
1517 			continue;
1518 
1519 		tegra_powergate_remove(genpd);
1520 	}
1521 
1522 	of_node_put(np);
1523 
1524 	np = of_get_child_by_name(parent, "core-domain");
1525 	if (np) {
1526 		of_genpd_del_provider(np);
1527 		of_genpd_remove_last(np);
1528 	}
1529 }
1530 
1531 static const struct tegra_io_pad_soc *
tegra_io_pad_find(struct tegra_pmc * pmc,enum tegra_io_pad id)1532 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1533 {
1534 	unsigned int i;
1535 
1536 	for (i = 0; i < pmc->soc->num_io_pads; i++)
1537 		if (pmc->soc->io_pads[i].id == id)
1538 			return &pmc->soc->io_pads[i];
1539 
1540 	return NULL;
1541 }
1542 
tegra_io_pad_get_dpd_register_bit(struct tegra_pmc * pmc,enum tegra_io_pad id,unsigned long * request,unsigned long * status,u32 * mask)1543 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1544 					     enum tegra_io_pad id,
1545 					     unsigned long *request,
1546 					     unsigned long *status,
1547 					     u32 *mask)
1548 {
1549 	const struct tegra_io_pad_soc *pad;
1550 
1551 	pad = tegra_io_pad_find(pmc, id);
1552 	if (!pad) {
1553 		dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1554 		return -ENOENT;
1555 	}
1556 
1557 	if (pad->dpd == UINT_MAX)
1558 		return -ENOTSUPP;
1559 
1560 	*mask = BIT(pad->dpd % 32);
1561 
1562 	if (pad->dpd < 32) {
1563 		*status = pmc->soc->regs->dpd_status;
1564 		*request = pmc->soc->regs->dpd_req;
1565 	} else {
1566 		*status = pmc->soc->regs->dpd2_status;
1567 		*request = pmc->soc->regs->dpd2_req;
1568 	}
1569 
1570 	return 0;
1571 }
1572 
tegra_io_pad_prepare(struct tegra_pmc * pmc,enum tegra_io_pad id,unsigned long * request,unsigned long * status,u32 * mask)1573 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1574 				unsigned long *request, unsigned long *status,
1575 				u32 *mask)
1576 {
1577 	unsigned long rate, value;
1578 	int err;
1579 
1580 	err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1581 	if (err)
1582 		return err;
1583 
1584 	if (pmc->clk) {
1585 		rate = pmc->rate;
1586 		if (!rate) {
1587 			dev_err(pmc->dev, "failed to get clock rate\n");
1588 			return -ENODEV;
1589 		}
1590 
1591 		tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1592 
1593 		/* must be at least 200 ns, in APB (PCLK) clock cycles */
1594 		value = DIV_ROUND_UP(1000000000, rate);
1595 		value = DIV_ROUND_UP(200, value);
1596 		tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1597 	}
1598 
1599 	return 0;
1600 }
1601 
tegra_io_pad_poll(struct tegra_pmc * pmc,unsigned long offset,u32 mask,u32 val,unsigned long timeout)1602 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1603 			     u32 mask, u32 val, unsigned long timeout)
1604 {
1605 	u32 value;
1606 
1607 	timeout = jiffies + msecs_to_jiffies(timeout);
1608 
1609 	while (time_after(timeout, jiffies)) {
1610 		value = tegra_pmc_readl(pmc, offset);
1611 		if ((value & mask) == val)
1612 			return 0;
1613 
1614 		usleep_range(250, 1000);
1615 	}
1616 
1617 	return -ETIMEDOUT;
1618 }
1619 
tegra_io_pad_unprepare(struct tegra_pmc * pmc)1620 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1621 {
1622 	if (pmc->clk)
1623 		tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1624 }
1625 
1626 /**
1627  * tegra_io_pad_power_enable() - enable power to I/O pad
1628  * @id: Tegra I/O pad ID for which to enable power
1629  *
1630  * Returns: 0 on success or a negative error code on failure.
1631  */
tegra_io_pad_power_enable(enum tegra_io_pad id)1632 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1633 {
1634 	unsigned long request, status;
1635 	u32 mask;
1636 	int err;
1637 
1638 	mutex_lock(&pmc->powergates_lock);
1639 
1640 	err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1641 	if (err < 0) {
1642 		dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1643 		goto unlock;
1644 	}
1645 
1646 	tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1647 
1648 	err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1649 	if (err < 0) {
1650 		dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1651 		goto unlock;
1652 	}
1653 
1654 	tegra_io_pad_unprepare(pmc);
1655 
1656 unlock:
1657 	mutex_unlock(&pmc->powergates_lock);
1658 	return err;
1659 }
1660 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1661 
1662 /**
1663  * tegra_io_pad_power_disable() - disable power to I/O pad
1664  * @id: Tegra I/O pad ID for which to disable power
1665  *
1666  * Returns: 0 on success or a negative error code on failure.
1667  */
tegra_io_pad_power_disable(enum tegra_io_pad id)1668 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1669 {
1670 	unsigned long request, status;
1671 	u32 mask;
1672 	int err;
1673 
1674 	mutex_lock(&pmc->powergates_lock);
1675 
1676 	err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1677 	if (err < 0) {
1678 		dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1679 		goto unlock;
1680 	}
1681 
1682 	tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1683 
1684 	err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1685 	if (err < 0) {
1686 		dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1687 		goto unlock;
1688 	}
1689 
1690 	tegra_io_pad_unprepare(pmc);
1691 
1692 unlock:
1693 	mutex_unlock(&pmc->powergates_lock);
1694 	return err;
1695 }
1696 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1697 
tegra_io_pad_is_powered(struct tegra_pmc * pmc,enum tegra_io_pad id)1698 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1699 {
1700 	unsigned long request, status;
1701 	u32 mask, value;
1702 	int err;
1703 
1704 	err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1705 						&mask);
1706 	if (err)
1707 		return err;
1708 
1709 	value = tegra_pmc_readl(pmc, status);
1710 
1711 	return !(value & mask);
1712 }
1713 
tegra_io_pad_set_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id,int voltage)1714 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1715 				    int voltage)
1716 {
1717 	const struct tegra_io_pad_soc *pad;
1718 	u32 value;
1719 
1720 	pad = tegra_io_pad_find(pmc, id);
1721 	if (!pad)
1722 		return -ENOENT;
1723 
1724 	if (pad->voltage == UINT_MAX)
1725 		return -ENOTSUPP;
1726 
1727 	mutex_lock(&pmc->powergates_lock);
1728 
1729 	if (pmc->soc->has_impl_33v_pwr) {
1730 		value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1731 
1732 		if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1733 			value &= ~BIT(pad->voltage);
1734 		else
1735 			value |= BIT(pad->voltage);
1736 
1737 		tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1738 	} else {
1739 		/* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1740 		value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1741 		value |= BIT(pad->voltage);
1742 		tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1743 
1744 		/* update I/O voltage */
1745 		value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1746 
1747 		if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1748 			value &= ~BIT(pad->voltage);
1749 		else
1750 			value |= BIT(pad->voltage);
1751 
1752 		tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1753 	}
1754 
1755 	mutex_unlock(&pmc->powergates_lock);
1756 
1757 	usleep_range(100, 250);
1758 
1759 	return 0;
1760 }
1761 
tegra_io_pad_get_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id)1762 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1763 {
1764 	const struct tegra_io_pad_soc *pad;
1765 	u32 value;
1766 
1767 	pad = tegra_io_pad_find(pmc, id);
1768 	if (!pad)
1769 		return -ENOENT;
1770 
1771 	if (pad->voltage == UINT_MAX)
1772 		return -ENOTSUPP;
1773 
1774 	if (pmc->soc->has_impl_33v_pwr)
1775 		value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1776 	else
1777 		value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1778 
1779 	if ((value & BIT(pad->voltage)) == 0)
1780 		return TEGRA_IO_PAD_VOLTAGE_1V8;
1781 
1782 	return TEGRA_IO_PAD_VOLTAGE_3V3;
1783 }
1784 
1785 /**
1786  * tegra_io_rail_power_on() - enable power to I/O rail
1787  * @id: Tegra I/O pad ID for which to enable power
1788  *
1789  * See also: tegra_io_pad_power_enable()
1790  */
tegra_io_rail_power_on(unsigned int id)1791 int tegra_io_rail_power_on(unsigned int id)
1792 {
1793 	return tegra_io_pad_power_enable(id);
1794 }
1795 EXPORT_SYMBOL(tegra_io_rail_power_on);
1796 
1797 /**
1798  * tegra_io_rail_power_off() - disable power to I/O rail
1799  * @id: Tegra I/O pad ID for which to disable power
1800  *
1801  * See also: tegra_io_pad_power_disable()
1802  */
tegra_io_rail_power_off(unsigned int id)1803 int tegra_io_rail_power_off(unsigned int id)
1804 {
1805 	return tegra_io_pad_power_disable(id);
1806 }
1807 EXPORT_SYMBOL(tegra_io_rail_power_off);
1808 
1809 #ifdef CONFIG_PM_SLEEP
tegra_pmc_get_suspend_mode(void)1810 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1811 {
1812 	return pmc->suspend_mode;
1813 }
1814 
tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)1815 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1816 {
1817 	if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1818 		return;
1819 
1820 	pmc->suspend_mode = mode;
1821 }
1822 
tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)1823 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1824 {
1825 	unsigned long long rate = 0;
1826 	u64 ticks;
1827 	u32 value;
1828 
1829 	switch (mode) {
1830 	case TEGRA_SUSPEND_LP1:
1831 		rate = 32768;
1832 		break;
1833 
1834 	case TEGRA_SUSPEND_LP2:
1835 		rate = pmc->rate;
1836 		break;
1837 
1838 	default:
1839 		break;
1840 	}
1841 
1842 	if (WARN_ON_ONCE(rate == 0))
1843 		rate = 100000000;
1844 
1845 	ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1846 	do_div(ticks, USEC_PER_SEC);
1847 	tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1848 
1849 	ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1850 	do_div(ticks, USEC_PER_SEC);
1851 	tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1852 
1853 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
1854 	value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1855 	value |= PMC_CNTRL_CPU_PWRREQ_OE;
1856 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
1857 }
1858 #endif
1859 
tegra_pmc_parse_dt(struct tegra_pmc * pmc,struct device_node * np)1860 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1861 {
1862 	u32 value, values[2];
1863 
1864 	if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1865 		pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1866 	} else {
1867 		switch (value) {
1868 		case 0:
1869 			pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1870 			break;
1871 
1872 		case 1:
1873 			pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1874 			break;
1875 
1876 		case 2:
1877 			pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1878 			break;
1879 
1880 		default:
1881 			pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1882 			break;
1883 		}
1884 	}
1885 
1886 	pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1887 
1888 	if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1889 		pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1890 
1891 	pmc->cpu_good_time = value;
1892 
1893 	if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1894 		pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1895 
1896 	pmc->cpu_off_time = value;
1897 
1898 	if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1899 				       values, ARRAY_SIZE(values)))
1900 		pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1901 
1902 	pmc->core_osc_time = values[0];
1903 	pmc->core_pmu_time = values[1];
1904 
1905 	if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1906 		pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1907 
1908 	pmc->core_off_time = value;
1909 
1910 	pmc->corereq_high = of_property_read_bool(np,
1911 				"nvidia,core-power-req-active-high");
1912 
1913 	pmc->sysclkreq_high = of_property_read_bool(np,
1914 				"nvidia,sys-clock-req-active-high");
1915 
1916 	pmc->combined_req = of_property_read_bool(np,
1917 				"nvidia,combined-power-req");
1918 
1919 	pmc->cpu_pwr_good_en = of_property_read_bool(np,
1920 				"nvidia,cpu-pwr-good-en");
1921 
1922 	if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1923 				       ARRAY_SIZE(values)))
1924 		if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1925 			pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1926 
1927 	pmc->lp0_vec_phys = values[0];
1928 	pmc->lp0_vec_size = values[1];
1929 
1930 	return 0;
1931 }
1932 
tegra_pmc_init(struct tegra_pmc * pmc)1933 static void tegra_pmc_init(struct tegra_pmc *pmc)
1934 {
1935 	if (pmc->soc->init)
1936 		pmc->soc->init(pmc);
1937 }
1938 
tegra_pmc_init_tsense_reset(struct tegra_pmc * pmc)1939 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1940 {
1941 	static const char disabled[] = "emergency thermal reset disabled";
1942 	u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1943 	struct device *dev = pmc->dev;
1944 	struct device_node *np;
1945 	u32 value, checksum;
1946 
1947 	if (!pmc->soc->has_tsense_reset)
1948 		return;
1949 
1950 	np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1951 	if (!np) {
1952 		dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1953 		return;
1954 	}
1955 
1956 	if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1957 		dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1958 		goto out;
1959 	}
1960 
1961 	if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1962 		dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1963 		goto out;
1964 	}
1965 
1966 	if (of_property_read_u32(np, "nvidia,reg-addr", &reg_addr)) {
1967 		dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1968 		goto out;
1969 	}
1970 
1971 	if (of_property_read_u32(np, "nvidia,reg-data", &reg_data)) {
1972 		dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1973 		goto out;
1974 	}
1975 
1976 	if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1977 		pinmux = 0;
1978 
1979 	value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1980 	value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1981 	tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1982 
1983 	value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1984 		(reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1985 	tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1986 
1987 	value = PMC_SCRATCH55_RESET_TEGRA;
1988 	value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1989 	value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1990 	value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1991 
1992 	/*
1993 	 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1994 	 * contain the checksum and are currently zero, so they are not added.
1995 	 */
1996 	checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1997 		+ ((value >> 24) & 0xff);
1998 	checksum &= 0xff;
1999 	checksum = 0x100 - checksum;
2000 
2001 	value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
2002 
2003 	tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
2004 
2005 	value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
2006 	value |= PMC_SENSOR_CTRL_ENABLE_RST;
2007 	tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
2008 
2009 	dev_info(pmc->dev, "emergency thermal reset enabled\n");
2010 
2011 out:
2012 	of_node_put(np);
2013 }
2014 
tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev * pctl_dev)2015 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
2016 {
2017 	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2018 
2019 	return pmc->soc->num_io_pads;
2020 }
2021 
tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev * pctl,unsigned int group)2022 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
2023 						       unsigned int group)
2024 {
2025 	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
2026 
2027 	return pmc->soc->io_pads[group].name;
2028 }
2029 
tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev * pctl_dev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)2030 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
2031 					       unsigned int group,
2032 					       const unsigned int **pins,
2033 					       unsigned int *num_pins)
2034 {
2035 	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2036 
2037 	*pins = &pmc->soc->io_pads[group].id;
2038 	*num_pins = 1;
2039 
2040 	return 0;
2041 }
2042 
2043 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
2044 	.get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
2045 	.get_group_name = tegra_io_pad_pinctrl_get_group_name,
2046 	.get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
2047 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
2048 	.dt_free_map = pinconf_generic_dt_free_map,
2049 };
2050 
tegra_io_pad_pinconf_get(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * config)2051 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
2052 				    unsigned int pin, unsigned long *config)
2053 {
2054 	enum pin_config_param param = pinconf_to_config_param(*config);
2055 	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2056 	const struct tegra_io_pad_soc *pad;
2057 	int ret;
2058 	u32 arg;
2059 
2060 	pad = tegra_io_pad_find(pmc, pin);
2061 	if (!pad)
2062 		return -EINVAL;
2063 
2064 	switch (param) {
2065 	case PIN_CONFIG_POWER_SOURCE:
2066 		ret = tegra_io_pad_get_voltage(pmc, pad->id);
2067 		if (ret < 0)
2068 			return ret;
2069 
2070 		arg = ret;
2071 		break;
2072 
2073 	case PIN_CONFIG_MODE_LOW_POWER:
2074 		ret = tegra_io_pad_is_powered(pmc, pad->id);
2075 		if (ret < 0)
2076 			return ret;
2077 
2078 		arg = !ret;
2079 		break;
2080 
2081 	default:
2082 		return -EINVAL;
2083 	}
2084 
2085 	*config = pinconf_to_config_packed(param, arg);
2086 
2087 	return 0;
2088 }
2089 
tegra_io_pad_pinconf_set(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * configs,unsigned int num_configs)2090 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
2091 				    unsigned int pin, unsigned long *configs,
2092 				    unsigned int num_configs)
2093 {
2094 	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2095 	const struct tegra_io_pad_soc *pad;
2096 	enum pin_config_param param;
2097 	unsigned int i;
2098 	int err;
2099 	u32 arg;
2100 
2101 	pad = tegra_io_pad_find(pmc, pin);
2102 	if (!pad)
2103 		return -EINVAL;
2104 
2105 	for (i = 0; i < num_configs; ++i) {
2106 		param = pinconf_to_config_param(configs[i]);
2107 		arg = pinconf_to_config_argument(configs[i]);
2108 
2109 		switch (param) {
2110 		case PIN_CONFIG_MODE_LOW_POWER:
2111 			if (arg)
2112 				err = tegra_io_pad_power_disable(pad->id);
2113 			else
2114 				err = tegra_io_pad_power_enable(pad->id);
2115 			if (err)
2116 				return err;
2117 			break;
2118 		case PIN_CONFIG_POWER_SOURCE:
2119 			if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
2120 			    arg != TEGRA_IO_PAD_VOLTAGE_3V3)
2121 				return -EINVAL;
2122 			err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
2123 			if (err)
2124 				return err;
2125 			break;
2126 		default:
2127 			return -EINVAL;
2128 		}
2129 	}
2130 
2131 	return 0;
2132 }
2133 
2134 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
2135 	.pin_config_get = tegra_io_pad_pinconf_get,
2136 	.pin_config_set = tegra_io_pad_pinconf_set,
2137 	.is_generic = true,
2138 };
2139 
2140 static struct pinctrl_desc tegra_pmc_pctl_desc = {
2141 	.pctlops = &tegra_io_pad_pinctrl_ops,
2142 	.confops = &tegra_io_pad_pinconf_ops,
2143 };
2144 
tegra_pmc_pinctrl_init(struct tegra_pmc * pmc)2145 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
2146 {
2147 	int err;
2148 
2149 	if (!pmc->soc->num_pin_descs)
2150 		return 0;
2151 
2152 	tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
2153 	tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
2154 	tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
2155 
2156 	pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
2157 					      pmc);
2158 	if (IS_ERR(pmc->pctl_dev)) {
2159 		err = PTR_ERR(pmc->pctl_dev);
2160 		dev_err(pmc->dev, "failed to register pin controller: %d\n",
2161 			err);
2162 		return err;
2163 	}
2164 
2165 	return 0;
2166 }
2167 
reset_reason_show(struct device * dev,struct device_attribute * attr,char * buf)2168 static ssize_t reset_reason_show(struct device *dev,
2169 				 struct device_attribute *attr, char *buf)
2170 {
2171 	u32 value;
2172 
2173 	value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2174 	value &= pmc->soc->regs->rst_source_mask;
2175 	value >>= pmc->soc->regs->rst_source_shift;
2176 
2177 	if (WARN_ON(value >= pmc->soc->num_reset_sources))
2178 		return sprintf(buf, "%s\n", "UNKNOWN");
2179 
2180 	return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2181 }
2182 
2183 static DEVICE_ATTR_RO(reset_reason);
2184 
reset_level_show(struct device * dev,struct device_attribute * attr,char * buf)2185 static ssize_t reset_level_show(struct device *dev,
2186 				struct device_attribute *attr, char *buf)
2187 {
2188 	u32 value;
2189 
2190 	value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2191 	value &= pmc->soc->regs->rst_level_mask;
2192 	value >>= pmc->soc->regs->rst_level_shift;
2193 
2194 	if (WARN_ON(value >= pmc->soc->num_reset_levels))
2195 		return sprintf(buf, "%s\n", "UNKNOWN");
2196 
2197 	return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2198 }
2199 
2200 static DEVICE_ATTR_RO(reset_level);
2201 
tegra_pmc_reset_sysfs_init(struct tegra_pmc * pmc)2202 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2203 {
2204 	struct device *dev = pmc->dev;
2205 	int err = 0;
2206 
2207 	if (pmc->soc->reset_sources) {
2208 		err = device_create_file(dev, &dev_attr_reset_reason);
2209 		if (err < 0)
2210 			dev_warn(dev,
2211 				 "failed to create attr \"reset_reason\": %d\n",
2212 				 err);
2213 	}
2214 
2215 	if (pmc->soc->reset_levels) {
2216 		err = device_create_file(dev, &dev_attr_reset_level);
2217 		if (err < 0)
2218 			dev_warn(dev,
2219 				 "failed to create attr \"reset_level\": %d\n",
2220 				 err);
2221 	}
2222 }
2223 
tegra_pmc_irq_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)2224 static int tegra_pmc_irq_translate(struct irq_domain *domain,
2225 				   struct irq_fwspec *fwspec,
2226 				   unsigned long *hwirq,
2227 				   unsigned int *type)
2228 {
2229 	if (WARN_ON(fwspec->param_count < 2))
2230 		return -EINVAL;
2231 
2232 	*hwirq = fwspec->param[0];
2233 	*type = fwspec->param[1];
2234 
2235 	return 0;
2236 }
2237 
tegra_pmc_irq_alloc(struct irq_domain * domain,unsigned int virq,unsigned int num_irqs,void * data)2238 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2239 			       unsigned int num_irqs, void *data)
2240 {
2241 	struct tegra_pmc *pmc = domain->host_data;
2242 	const struct tegra_pmc_soc *soc = pmc->soc;
2243 	struct irq_fwspec *fwspec = data;
2244 	unsigned int i;
2245 	int err = 0;
2246 
2247 	if (WARN_ON(num_irqs > 1))
2248 		return -EINVAL;
2249 
2250 	for (i = 0; i < soc->num_wake_events; i++) {
2251 		const struct tegra_wake_event *event = &soc->wake_events[i];
2252 
2253 		/* IRQ and simple wake events */
2254 		if (fwspec->param_count == 2) {
2255 			struct irq_fwspec spec;
2256 
2257 			if (event->id != fwspec->param[0])
2258 				continue;
2259 
2260 			err = irq_domain_set_hwirq_and_chip(domain, virq,
2261 							    event->id,
2262 							    &pmc->irq, pmc);
2263 			if (err < 0)
2264 				break;
2265 
2266 			/* simple hierarchies stop at the PMC level */
2267 			if (event->irq == 0) {
2268 				err = irq_domain_disconnect_hierarchy(domain->parent, virq);
2269 				break;
2270 			}
2271 
2272 			spec.fwnode = &pmc->dev->of_node->fwnode;
2273 			spec.param_count = 3;
2274 			spec.param[0] = GIC_SPI;
2275 			spec.param[1] = event->irq;
2276 			spec.param[2] = fwspec->param[1];
2277 
2278 			err = irq_domain_alloc_irqs_parent(domain, virq,
2279 							   num_irqs, &spec);
2280 
2281 			break;
2282 		}
2283 
2284 		/* GPIO wake events */
2285 		if (fwspec->param_count == 3) {
2286 			if (event->gpio.instance != fwspec->param[0] ||
2287 			    event->gpio.pin != fwspec->param[1])
2288 				continue;
2289 
2290 			err = irq_domain_set_hwirq_and_chip(domain, virq,
2291 							    event->id,
2292 							    &pmc->irq, pmc);
2293 
2294 			/* GPIO hierarchies stop at the PMC level */
2295 			if (!err && domain->parent)
2296 				err = irq_domain_disconnect_hierarchy(domain->parent,
2297 								      virq);
2298 			break;
2299 		}
2300 	}
2301 
2302 	/* If there is no wake-up event, there is no PMC mapping */
2303 	if (i == soc->num_wake_events)
2304 		err = irq_domain_disconnect_hierarchy(domain, virq);
2305 
2306 	return err;
2307 }
2308 
2309 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2310 	.translate = tegra_pmc_irq_translate,
2311 	.alloc = tegra_pmc_irq_alloc,
2312 };
2313 
tegra210_pmc_irq_set_wake(struct irq_data * data,unsigned int on)2314 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2315 {
2316 	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2317 	unsigned int offset, bit;
2318 	u32 value;
2319 
2320 	offset = data->hwirq / 32;
2321 	bit = data->hwirq % 32;
2322 
2323 	/* clear wake status */
2324 	tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2325 	tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2326 
2327 	tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2328 	tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2329 
2330 	/* enable PMC wake */
2331 	if (data->hwirq >= 32)
2332 		offset = PMC_WAKE2_MASK;
2333 	else
2334 		offset = PMC_WAKE_MASK;
2335 
2336 	value = tegra_pmc_readl(pmc, offset);
2337 
2338 	if (on)
2339 		value |= BIT(bit);
2340 	else
2341 		value &= ~BIT(bit);
2342 
2343 	tegra_pmc_writel(pmc, value, offset);
2344 
2345 	return 0;
2346 }
2347 
tegra210_pmc_irq_set_type(struct irq_data * data,unsigned int type)2348 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2349 {
2350 	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2351 	unsigned int offset, bit;
2352 	u32 value;
2353 
2354 	offset = data->hwirq / 32;
2355 	bit = data->hwirq % 32;
2356 
2357 	if (data->hwirq >= 32)
2358 		offset = PMC_WAKE2_LEVEL;
2359 	else
2360 		offset = PMC_WAKE_LEVEL;
2361 
2362 	value = tegra_pmc_readl(pmc, offset);
2363 
2364 	switch (type) {
2365 	case IRQ_TYPE_EDGE_RISING:
2366 	case IRQ_TYPE_LEVEL_HIGH:
2367 		value |= BIT(bit);
2368 		break;
2369 
2370 	case IRQ_TYPE_EDGE_FALLING:
2371 	case IRQ_TYPE_LEVEL_LOW:
2372 		value &= ~BIT(bit);
2373 		break;
2374 
2375 	case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2376 		value ^= BIT(bit);
2377 		break;
2378 
2379 	default:
2380 		return -EINVAL;
2381 	}
2382 
2383 	tegra_pmc_writel(pmc, value, offset);
2384 
2385 	return 0;
2386 }
2387 
tegra186_pmc_irq_set_wake(struct irq_data * data,unsigned int on)2388 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2389 {
2390 	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2391 	unsigned int offset, bit;
2392 	u32 value;
2393 
2394 	offset = data->hwirq / 32;
2395 	bit = data->hwirq % 32;
2396 
2397 	/* clear wake status */
2398 	writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2399 
2400 	/* route wake to tier 2 */
2401 	value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2402 
2403 	if (!on)
2404 		value &= ~(1 << bit);
2405 	else
2406 		value |= 1 << bit;
2407 
2408 	writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2409 
2410 	/* enable wakeup event */
2411 	writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2412 
2413 	return 0;
2414 }
2415 
tegra186_pmc_irq_set_type(struct irq_data * data,unsigned int type)2416 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2417 {
2418 	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2419 	u32 value;
2420 
2421 	value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2422 
2423 	switch (type) {
2424 	case IRQ_TYPE_EDGE_RISING:
2425 	case IRQ_TYPE_LEVEL_HIGH:
2426 		value |= WAKE_AOWAKE_CNTRL_LEVEL;
2427 		break;
2428 
2429 	case IRQ_TYPE_EDGE_FALLING:
2430 	case IRQ_TYPE_LEVEL_LOW:
2431 		value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2432 		break;
2433 
2434 	case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2435 		value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2436 		break;
2437 
2438 	default:
2439 		return -EINVAL;
2440 	}
2441 
2442 	writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2443 
2444 	return 0;
2445 }
2446 
tegra_irq_mask_parent(struct irq_data * data)2447 static void tegra_irq_mask_parent(struct irq_data *data)
2448 {
2449 	if (data->parent_data)
2450 		irq_chip_mask_parent(data);
2451 }
2452 
tegra_irq_unmask_parent(struct irq_data * data)2453 static void tegra_irq_unmask_parent(struct irq_data *data)
2454 {
2455 	if (data->parent_data)
2456 		irq_chip_unmask_parent(data);
2457 }
2458 
tegra_irq_eoi_parent(struct irq_data * data)2459 static void tegra_irq_eoi_parent(struct irq_data *data)
2460 {
2461 	if (data->parent_data)
2462 		irq_chip_eoi_parent(data);
2463 }
2464 
tegra_irq_set_affinity_parent(struct irq_data * data,const struct cpumask * dest,bool force)2465 static int tegra_irq_set_affinity_parent(struct irq_data *data,
2466 					 const struct cpumask *dest,
2467 					 bool force)
2468 {
2469 	if (data->parent_data)
2470 		return irq_chip_set_affinity_parent(data, dest, force);
2471 
2472 	return -EINVAL;
2473 }
2474 
tegra_pmc_irq_init(struct tegra_pmc * pmc)2475 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2476 {
2477 	struct irq_domain *parent = NULL;
2478 	struct device_node *np;
2479 
2480 	np = of_irq_find_parent(pmc->dev->of_node);
2481 	if (np) {
2482 		parent = irq_find_host(np);
2483 		of_node_put(np);
2484 	}
2485 
2486 	if (!parent)
2487 		return 0;
2488 
2489 	pmc->irq.name = dev_name(pmc->dev);
2490 	pmc->irq.irq_mask = tegra_irq_mask_parent;
2491 	pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2492 	pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2493 	pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2494 	pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2495 	pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2496 
2497 	pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2498 					       &tegra_pmc_irq_domain_ops, pmc);
2499 	if (!pmc->domain) {
2500 		dev_err(pmc->dev, "failed to allocate domain\n");
2501 		return -ENOMEM;
2502 	}
2503 
2504 	return 0;
2505 }
2506 
tegra_pmc_clk_notify_cb(struct notifier_block * nb,unsigned long action,void * ptr)2507 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2508 				   unsigned long action, void *ptr)
2509 {
2510 	struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2511 	struct clk_notifier_data *data = ptr;
2512 
2513 	switch (action) {
2514 	case PRE_RATE_CHANGE:
2515 		mutex_lock(&pmc->powergates_lock);
2516 		break;
2517 
2518 	case POST_RATE_CHANGE:
2519 		pmc->rate = data->new_rate;
2520 		fallthrough;
2521 
2522 	case ABORT_RATE_CHANGE:
2523 		mutex_unlock(&pmc->powergates_lock);
2524 		break;
2525 
2526 	default:
2527 		WARN_ON_ONCE(1);
2528 		return notifier_from_errno(-EINVAL);
2529 	}
2530 
2531 	return NOTIFY_OK;
2532 }
2533 
pmc_clk_fence_udelay(u32 offset)2534 static void pmc_clk_fence_udelay(u32 offset)
2535 {
2536 	tegra_pmc_readl(pmc, offset);
2537 	/* pmc clk propagation delay 2 us */
2538 	udelay(2);
2539 }
2540 
pmc_clk_mux_get_parent(struct clk_hw * hw)2541 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2542 {
2543 	struct pmc_clk *clk = to_pmc_clk(hw);
2544 	u32 val;
2545 
2546 	val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2547 	val &= PMC_CLK_OUT_MUX_MASK;
2548 
2549 	return val;
2550 }
2551 
pmc_clk_mux_set_parent(struct clk_hw * hw,u8 index)2552 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2553 {
2554 	struct pmc_clk *clk = to_pmc_clk(hw);
2555 	u32 val;
2556 
2557 	val = tegra_pmc_readl(pmc, clk->offs);
2558 	val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2559 	val |= index << clk->mux_shift;
2560 	tegra_pmc_writel(pmc, val, clk->offs);
2561 	pmc_clk_fence_udelay(clk->offs);
2562 
2563 	return 0;
2564 }
2565 
pmc_clk_is_enabled(struct clk_hw * hw)2566 static int pmc_clk_is_enabled(struct clk_hw *hw)
2567 {
2568 	struct pmc_clk *clk = to_pmc_clk(hw);
2569 	u32 val;
2570 
2571 	val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2572 
2573 	return val ? 1 : 0;
2574 }
2575 
pmc_clk_set_state(unsigned long offs,u32 shift,int state)2576 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2577 {
2578 	u32 val;
2579 
2580 	val = tegra_pmc_readl(pmc, offs);
2581 	val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2582 	tegra_pmc_writel(pmc, val, offs);
2583 	pmc_clk_fence_udelay(offs);
2584 }
2585 
pmc_clk_enable(struct clk_hw * hw)2586 static int pmc_clk_enable(struct clk_hw *hw)
2587 {
2588 	struct pmc_clk *clk = to_pmc_clk(hw);
2589 
2590 	pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2591 
2592 	return 0;
2593 }
2594 
pmc_clk_disable(struct clk_hw * hw)2595 static void pmc_clk_disable(struct clk_hw *hw)
2596 {
2597 	struct pmc_clk *clk = to_pmc_clk(hw);
2598 
2599 	pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2600 }
2601 
2602 static const struct clk_ops pmc_clk_ops = {
2603 	.get_parent = pmc_clk_mux_get_parent,
2604 	.set_parent = pmc_clk_mux_set_parent,
2605 	.determine_rate = __clk_mux_determine_rate,
2606 	.is_enabled = pmc_clk_is_enabled,
2607 	.enable = pmc_clk_enable,
2608 	.disable = pmc_clk_disable,
2609 };
2610 
2611 static struct clk *
tegra_pmc_clk_out_register(struct tegra_pmc * pmc,const struct pmc_clk_init_data * data,unsigned long offset)2612 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2613 			   const struct pmc_clk_init_data *data,
2614 			   unsigned long offset)
2615 {
2616 	struct clk_init_data init;
2617 	struct pmc_clk *pmc_clk;
2618 
2619 	pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2620 	if (!pmc_clk)
2621 		return ERR_PTR(-ENOMEM);
2622 
2623 	init.name = data->name;
2624 	init.ops = &pmc_clk_ops;
2625 	init.parent_names = data->parents;
2626 	init.num_parents = data->num_parents;
2627 	init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2628 		     CLK_SET_PARENT_GATE;
2629 
2630 	pmc_clk->hw.init = &init;
2631 	pmc_clk->offs = offset;
2632 	pmc_clk->mux_shift = data->mux_shift;
2633 	pmc_clk->force_en_shift = data->force_en_shift;
2634 
2635 	return clk_register(NULL, &pmc_clk->hw);
2636 }
2637 
pmc_clk_gate_is_enabled(struct clk_hw * hw)2638 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2639 {
2640 	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2641 
2642 	return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2643 }
2644 
pmc_clk_gate_enable(struct clk_hw * hw)2645 static int pmc_clk_gate_enable(struct clk_hw *hw)
2646 {
2647 	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2648 
2649 	pmc_clk_set_state(gate->offs, gate->shift, 1);
2650 
2651 	return 0;
2652 }
2653 
pmc_clk_gate_disable(struct clk_hw * hw)2654 static void pmc_clk_gate_disable(struct clk_hw *hw)
2655 {
2656 	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2657 
2658 	pmc_clk_set_state(gate->offs, gate->shift, 0);
2659 }
2660 
2661 static const struct clk_ops pmc_clk_gate_ops = {
2662 	.is_enabled = pmc_clk_gate_is_enabled,
2663 	.enable = pmc_clk_gate_enable,
2664 	.disable = pmc_clk_gate_disable,
2665 };
2666 
2667 static struct clk *
tegra_pmc_clk_gate_register(struct tegra_pmc * pmc,const char * name,const char * parent_name,unsigned long offset,u32 shift)2668 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2669 			    const char *parent_name, unsigned long offset,
2670 			    u32 shift)
2671 {
2672 	struct clk_init_data init;
2673 	struct pmc_clk_gate *gate;
2674 
2675 	gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2676 	if (!gate)
2677 		return ERR_PTR(-ENOMEM);
2678 
2679 	init.name = name;
2680 	init.ops = &pmc_clk_gate_ops;
2681 	init.parent_names = &parent_name;
2682 	init.num_parents = 1;
2683 	init.flags = 0;
2684 
2685 	gate->hw.init = &init;
2686 	gate->offs = offset;
2687 	gate->shift = shift;
2688 
2689 	return clk_register(NULL, &gate->hw);
2690 }
2691 
tegra_pmc_clock_register(struct tegra_pmc * pmc,struct device_node * np)2692 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2693 				     struct device_node *np)
2694 {
2695 	struct clk *clk;
2696 	struct clk_onecell_data *clk_data;
2697 	unsigned int num_clks;
2698 	int i, err;
2699 
2700 	num_clks = pmc->soc->num_pmc_clks;
2701 	if (pmc->soc->has_blink_output)
2702 		num_clks += 1;
2703 
2704 	if (!num_clks)
2705 		return;
2706 
2707 	clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2708 	if (!clk_data)
2709 		return;
2710 
2711 	clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2712 				      sizeof(*clk_data->clks), GFP_KERNEL);
2713 	if (!clk_data->clks)
2714 		return;
2715 
2716 	clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2717 
2718 	for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2719 		clk_data->clks[i] = ERR_PTR(-ENOENT);
2720 
2721 	for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2722 		const struct pmc_clk_init_data *data;
2723 
2724 		data = pmc->soc->pmc_clks_data + i;
2725 
2726 		clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2727 		if (IS_ERR(clk)) {
2728 			dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2729 				 data->name, PTR_ERR_OR_ZERO(clk));
2730 			return;
2731 		}
2732 
2733 		err = clk_register_clkdev(clk, data->name, NULL);
2734 		if (err) {
2735 			dev_warn(pmc->dev,
2736 				 "unable to register %s clock lookup: %d\n",
2737 				 data->name, err);
2738 			return;
2739 		}
2740 
2741 		clk_data->clks[data->clk_id] = clk;
2742 	}
2743 
2744 	if (pmc->soc->has_blink_output) {
2745 		tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2746 		clk = tegra_pmc_clk_gate_register(pmc,
2747 						  "pmc_blink_override",
2748 						  "clk_32k",
2749 						  PMC_DPD_PADS_ORIDE,
2750 						  PMC_DPD_PADS_ORIDE_BLINK);
2751 		if (IS_ERR(clk)) {
2752 			dev_warn(pmc->dev,
2753 				 "unable to register pmc_blink_override: %d\n",
2754 				 PTR_ERR_OR_ZERO(clk));
2755 			return;
2756 		}
2757 
2758 		clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2759 						  "pmc_blink_override",
2760 						  PMC_CNTRL,
2761 						  PMC_CNTRL_BLINK_EN);
2762 		if (IS_ERR(clk)) {
2763 			dev_warn(pmc->dev,
2764 				 "unable to register pmc_blink: %d\n",
2765 				 PTR_ERR_OR_ZERO(clk));
2766 			return;
2767 		}
2768 
2769 		err = clk_register_clkdev(clk, "pmc_blink", NULL);
2770 		if (err) {
2771 			dev_warn(pmc->dev,
2772 				 "unable to register pmc_blink lookup: %d\n",
2773 				 err);
2774 			return;
2775 		}
2776 
2777 		clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2778 	}
2779 
2780 	err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2781 	if (err)
2782 		dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2783 			 err);
2784 }
2785 
2786 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2787 	regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2788 	regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2789 	regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2790 	regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2791 	regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2792 	regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2793 	regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2794 	regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2795 };
2796 
2797 static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2798 	.yes_ranges = pmc_usb_sleepwalk_ranges,
2799 	.n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2800 };
2801 
tegra_pmc_regmap_readl(void * context,unsigned int offset,unsigned int * value)2802 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2803 {
2804 	struct tegra_pmc *pmc = context;
2805 
2806 	*value = tegra_pmc_readl(pmc, offset);
2807 	return 0;
2808 }
2809 
tegra_pmc_regmap_writel(void * context,unsigned int offset,unsigned int value)2810 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2811 {
2812 	struct tegra_pmc *pmc = context;
2813 
2814 	tegra_pmc_writel(pmc, value, offset);
2815 	return 0;
2816 }
2817 
2818 static const struct regmap_config usb_sleepwalk_regmap_config = {
2819 	.name = "usb_sleepwalk",
2820 	.reg_bits = 32,
2821 	.val_bits = 32,
2822 	.reg_stride = 4,
2823 	.fast_io = true,
2824 	.rd_table = &pmc_usb_sleepwalk_table,
2825 	.wr_table = &pmc_usb_sleepwalk_table,
2826 	.reg_read = tegra_pmc_regmap_readl,
2827 	.reg_write = tegra_pmc_regmap_writel,
2828 };
2829 
tegra_pmc_regmap_init(struct tegra_pmc * pmc)2830 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2831 {
2832 	struct regmap *regmap;
2833 	int err;
2834 
2835 	if (pmc->soc->has_usb_sleepwalk) {
2836 		regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2837 		if (IS_ERR(regmap)) {
2838 			err = PTR_ERR(regmap);
2839 			dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2840 			return err;
2841 		}
2842 	}
2843 
2844 	return 0;
2845 }
2846 
tegra_pmc_reset_suspend_mode(void * data)2847 static void tegra_pmc_reset_suspend_mode(void *data)
2848 {
2849 	pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
2850 }
2851 
tegra_pmc_probe(struct platform_device * pdev)2852 static int tegra_pmc_probe(struct platform_device *pdev)
2853 {
2854 	void __iomem *base;
2855 	struct resource *res;
2856 	int err;
2857 
2858 	/*
2859 	 * Early initialisation should have configured an initial
2860 	 * register mapping and setup the soc data pointer. If these
2861 	 * are not valid then something went badly wrong!
2862 	 */
2863 	if (WARN_ON(!pmc->base || !pmc->soc))
2864 		return -ENODEV;
2865 
2866 	err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2867 	if (err < 0)
2868 		return err;
2869 
2870 	err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode,
2871 				       NULL);
2872 	if (err)
2873 		return err;
2874 
2875 	/* take over the memory region from the early initialization */
2876 	base = devm_platform_ioremap_resource(pdev, 0);
2877 	if (IS_ERR(base))
2878 		return PTR_ERR(base);
2879 
2880 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2881 	if (res) {
2882 		pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2883 		if (IS_ERR(pmc->wake))
2884 			return PTR_ERR(pmc->wake);
2885 	} else {
2886 		pmc->wake = base;
2887 	}
2888 
2889 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2890 	if (res) {
2891 		pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2892 		if (IS_ERR(pmc->aotag))
2893 			return PTR_ERR(pmc->aotag);
2894 	} else {
2895 		pmc->aotag = base;
2896 	}
2897 
2898 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2899 	if (res) {
2900 		pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2901 		if (IS_ERR(pmc->scratch))
2902 			return PTR_ERR(pmc->scratch);
2903 	} else {
2904 		pmc->scratch = base;
2905 	}
2906 
2907 	pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk");
2908 	if (IS_ERR(pmc->clk))
2909 		return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk),
2910 				     "failed to get pclk\n");
2911 
2912 	/*
2913 	 * PMC should be last resort for restarting since it soft-resets
2914 	 * CPU without resetting everything else.
2915 	 */
2916 	err = devm_register_reboot_notifier(&pdev->dev,
2917 					    &tegra_pmc_reboot_notifier);
2918 	if (err) {
2919 		dev_err(&pdev->dev, "unable to register reboot notifier, %d\n",
2920 			err);
2921 		return err;
2922 	}
2923 
2924 	err = devm_register_sys_off_handler(&pdev->dev,
2925 					    SYS_OFF_MODE_RESTART,
2926 					    SYS_OFF_PRIO_LOW,
2927 					    tegra_pmc_restart_handler, NULL);
2928 	if (err) {
2929 		dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",
2930 			err);
2931 		return err;
2932 	}
2933 
2934 	/*
2935 	 * PMC should be primary power-off method if it soft-resets CPU,
2936 	 * asking bootloader to shutdown hardware.
2937 	 */
2938 	err = devm_register_sys_off_handler(&pdev->dev,
2939 					    SYS_OFF_MODE_POWER_OFF,
2940 					    SYS_OFF_PRIO_FIRMWARE,
2941 					    tegra_pmc_power_off_handler, NULL);
2942 	if (err) {
2943 		dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",
2944 			err);
2945 		return err;
2946 	}
2947 
2948 	/*
2949 	 * PCLK clock rate can't be retrieved using CLK API because it
2950 	 * causes lockup if CPU enters LP2 idle state from some other
2951 	 * CLK notifier, hence we're caching the rate's value locally.
2952 	 */
2953 	if (pmc->clk) {
2954 		pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2955 		err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2956 		if (err) {
2957 			dev_err(&pdev->dev,
2958 				"failed to register clk notifier\n");
2959 			return err;
2960 		}
2961 
2962 		pmc->rate = clk_get_rate(pmc->clk);
2963 	}
2964 
2965 	pmc->dev = &pdev->dev;
2966 
2967 	tegra_pmc_init(pmc);
2968 
2969 	tegra_pmc_init_tsense_reset(pmc);
2970 
2971 	tegra_pmc_reset_sysfs_init(pmc);
2972 
2973 	if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2974 		err = tegra_powergate_debugfs_init();
2975 		if (err < 0)
2976 			goto cleanup_sysfs;
2977 	}
2978 
2979 	err = tegra_pmc_pinctrl_init(pmc);
2980 	if (err)
2981 		goto cleanup_debugfs;
2982 
2983 	err = tegra_pmc_regmap_init(pmc);
2984 	if (err < 0)
2985 		goto cleanup_debugfs;
2986 
2987 	err = tegra_powergate_init(pmc, pdev->dev.of_node);
2988 	if (err < 0)
2989 		goto cleanup_powergates;
2990 
2991 	err = tegra_pmc_irq_init(pmc);
2992 	if (err < 0)
2993 		goto cleanup_powergates;
2994 
2995 	mutex_lock(&pmc->powergates_lock);
2996 	iounmap(pmc->base);
2997 	pmc->base = base;
2998 	mutex_unlock(&pmc->powergates_lock);
2999 
3000 	tegra_pmc_clock_register(pmc, pdev->dev.of_node);
3001 	platform_set_drvdata(pdev, pmc);
3002 	tegra_pm_init_suspend();
3003 
3004 	return 0;
3005 
3006 cleanup_powergates:
3007 	tegra_powergate_remove_all(pdev->dev.of_node);
3008 cleanup_debugfs:
3009 	debugfs_remove(pmc->debugfs);
3010 cleanup_sysfs:
3011 	device_remove_file(&pdev->dev, &dev_attr_reset_reason);
3012 	device_remove_file(&pdev->dev, &dev_attr_reset_level);
3013 	clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
3014 
3015 	return err;
3016 }
3017 
3018 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
tegra_pmc_suspend(struct device * dev)3019 static int tegra_pmc_suspend(struct device *dev)
3020 {
3021 	struct tegra_pmc *pmc = dev_get_drvdata(dev);
3022 
3023 	tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
3024 
3025 	return 0;
3026 }
3027 
tegra_pmc_resume(struct device * dev)3028 static int tegra_pmc_resume(struct device *dev)
3029 {
3030 	struct tegra_pmc *pmc = dev_get_drvdata(dev);
3031 
3032 	tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
3033 
3034 	return 0;
3035 }
3036 
3037 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
3038 
3039 #endif
3040 
3041 static const char * const tegra20_powergates[] = {
3042 	[TEGRA_POWERGATE_CPU] = "cpu",
3043 	[TEGRA_POWERGATE_3D] = "td",
3044 	[TEGRA_POWERGATE_VENC] = "venc",
3045 	[TEGRA_POWERGATE_VDEC] = "vdec",
3046 	[TEGRA_POWERGATE_PCIE] = "pcie",
3047 	[TEGRA_POWERGATE_L2] = "l2",
3048 	[TEGRA_POWERGATE_MPE] = "mpe",
3049 };
3050 
3051 static const struct tegra_pmc_regs tegra20_pmc_regs = {
3052 	.scratch0 = 0x50,
3053 	.dpd_req = 0x1b8,
3054 	.dpd_status = 0x1bc,
3055 	.dpd2_req = 0x1c0,
3056 	.dpd2_status = 0x1c4,
3057 	.rst_status = 0x1b4,
3058 	.rst_source_shift = 0x0,
3059 	.rst_source_mask = 0x7,
3060 	.rst_level_shift = 0x0,
3061 	.rst_level_mask = 0x0,
3062 };
3063 
tegra20_pmc_init(struct tegra_pmc * pmc)3064 static void tegra20_pmc_init(struct tegra_pmc *pmc)
3065 {
3066 	u32 value, osc, pmu, off;
3067 
3068 	/* Always enable CPU power request */
3069 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
3070 	value |= PMC_CNTRL_CPU_PWRREQ_OE;
3071 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
3072 
3073 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
3074 
3075 	if (pmc->sysclkreq_high)
3076 		value &= ~PMC_CNTRL_SYSCLK_POLARITY;
3077 	else
3078 		value |= PMC_CNTRL_SYSCLK_POLARITY;
3079 
3080 	if (pmc->corereq_high)
3081 		value &= ~PMC_CNTRL_PWRREQ_POLARITY;
3082 	else
3083 		value |= PMC_CNTRL_PWRREQ_POLARITY;
3084 
3085 	/* configure the output polarity while the request is tristated */
3086 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
3087 
3088 	/* now enable the request */
3089 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
3090 	value |= PMC_CNTRL_SYSCLK_OE;
3091 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
3092 
3093 	/* program core timings which are applicable only for suspend state */
3094 	if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
3095 		osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
3096 		pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
3097 		off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
3098 		tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
3099 				 PMC_COREPWRGOOD_TIMER);
3100 		tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
3101 	}
3102 }
3103 
tegra20_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)3104 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3105 					   struct device_node *np,
3106 					   bool invert)
3107 {
3108 	u32 value;
3109 
3110 	value = tegra_pmc_readl(pmc, PMC_CNTRL);
3111 
3112 	if (invert)
3113 		value |= PMC_CNTRL_INTR_POLARITY;
3114 	else
3115 		value &= ~PMC_CNTRL_INTR_POLARITY;
3116 
3117 	tegra_pmc_writel(pmc, value, PMC_CNTRL);
3118 }
3119 
3120 static const struct tegra_pmc_soc tegra20_pmc_soc = {
3121 	.supports_core_domain = true,
3122 	.num_powergates = ARRAY_SIZE(tegra20_powergates),
3123 	.powergates = tegra20_powergates,
3124 	.num_cpu_powergates = 0,
3125 	.cpu_powergates = NULL,
3126 	.has_tsense_reset = false,
3127 	.has_gpu_clamps = false,
3128 	.needs_mbist_war = false,
3129 	.has_impl_33v_pwr = false,
3130 	.maybe_tz_only = false,
3131 	.num_io_pads = 0,
3132 	.io_pads = NULL,
3133 	.num_pin_descs = 0,
3134 	.pin_descs = NULL,
3135 	.regs = &tegra20_pmc_regs,
3136 	.init = tegra20_pmc_init,
3137 	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3138 	.powergate_set = tegra20_powergate_set,
3139 	.reset_sources = NULL,
3140 	.num_reset_sources = 0,
3141 	.reset_levels = NULL,
3142 	.num_reset_levels = 0,
3143 	.pmc_clks_data = NULL,
3144 	.num_pmc_clks = 0,
3145 	.has_blink_output = true,
3146 	.has_usb_sleepwalk = true,
3147 };
3148 
3149 static const char * const tegra30_powergates[] = {
3150 	[TEGRA_POWERGATE_CPU] = "cpu0",
3151 	[TEGRA_POWERGATE_3D] = "td",
3152 	[TEGRA_POWERGATE_VENC] = "venc",
3153 	[TEGRA_POWERGATE_VDEC] = "vdec",
3154 	[TEGRA_POWERGATE_PCIE] = "pcie",
3155 	[TEGRA_POWERGATE_L2] = "l2",
3156 	[TEGRA_POWERGATE_MPE] = "mpe",
3157 	[TEGRA_POWERGATE_HEG] = "heg",
3158 	[TEGRA_POWERGATE_SATA] = "sata",
3159 	[TEGRA_POWERGATE_CPU1] = "cpu1",
3160 	[TEGRA_POWERGATE_CPU2] = "cpu2",
3161 	[TEGRA_POWERGATE_CPU3] = "cpu3",
3162 	[TEGRA_POWERGATE_CELP] = "celp",
3163 	[TEGRA_POWERGATE_3D1] = "td2",
3164 };
3165 
3166 static const u8 tegra30_cpu_powergates[] = {
3167 	TEGRA_POWERGATE_CPU,
3168 	TEGRA_POWERGATE_CPU1,
3169 	TEGRA_POWERGATE_CPU2,
3170 	TEGRA_POWERGATE_CPU3,
3171 };
3172 
3173 static const char * const tegra30_reset_sources[] = {
3174 	"POWER_ON_RESET",
3175 	"WATCHDOG",
3176 	"SENSOR",
3177 	"SW_MAIN",
3178 	"LP0"
3179 };
3180 
3181 static const struct tegra_pmc_soc tegra30_pmc_soc = {
3182 	.supports_core_domain = true,
3183 	.num_powergates = ARRAY_SIZE(tegra30_powergates),
3184 	.powergates = tegra30_powergates,
3185 	.num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
3186 	.cpu_powergates = tegra30_cpu_powergates,
3187 	.has_tsense_reset = true,
3188 	.has_gpu_clamps = false,
3189 	.needs_mbist_war = false,
3190 	.has_impl_33v_pwr = false,
3191 	.maybe_tz_only = false,
3192 	.num_io_pads = 0,
3193 	.io_pads = NULL,
3194 	.num_pin_descs = 0,
3195 	.pin_descs = NULL,
3196 	.regs = &tegra20_pmc_regs,
3197 	.init = tegra20_pmc_init,
3198 	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3199 	.powergate_set = tegra20_powergate_set,
3200 	.reset_sources = tegra30_reset_sources,
3201 	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3202 	.reset_levels = NULL,
3203 	.num_reset_levels = 0,
3204 	.pmc_clks_data = tegra_pmc_clks_data,
3205 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3206 	.has_blink_output = true,
3207 	.has_usb_sleepwalk = true,
3208 };
3209 
3210 static const char * const tegra114_powergates[] = {
3211 	[TEGRA_POWERGATE_CPU] = "crail",
3212 	[TEGRA_POWERGATE_3D] = "td",
3213 	[TEGRA_POWERGATE_VENC] = "venc",
3214 	[TEGRA_POWERGATE_VDEC] = "vdec",
3215 	[TEGRA_POWERGATE_MPE] = "mpe",
3216 	[TEGRA_POWERGATE_HEG] = "heg",
3217 	[TEGRA_POWERGATE_CPU1] = "cpu1",
3218 	[TEGRA_POWERGATE_CPU2] = "cpu2",
3219 	[TEGRA_POWERGATE_CPU3] = "cpu3",
3220 	[TEGRA_POWERGATE_CELP] = "celp",
3221 	[TEGRA_POWERGATE_CPU0] = "cpu0",
3222 	[TEGRA_POWERGATE_C0NC] = "c0nc",
3223 	[TEGRA_POWERGATE_C1NC] = "c1nc",
3224 	[TEGRA_POWERGATE_DIS] = "dis",
3225 	[TEGRA_POWERGATE_DISB] = "disb",
3226 	[TEGRA_POWERGATE_XUSBA] = "xusba",
3227 	[TEGRA_POWERGATE_XUSBB] = "xusbb",
3228 	[TEGRA_POWERGATE_XUSBC] = "xusbc",
3229 };
3230 
3231 static const u8 tegra114_cpu_powergates[] = {
3232 	TEGRA_POWERGATE_CPU0,
3233 	TEGRA_POWERGATE_CPU1,
3234 	TEGRA_POWERGATE_CPU2,
3235 	TEGRA_POWERGATE_CPU3,
3236 };
3237 
3238 static const struct tegra_pmc_soc tegra114_pmc_soc = {
3239 	.supports_core_domain = false,
3240 	.num_powergates = ARRAY_SIZE(tegra114_powergates),
3241 	.powergates = tegra114_powergates,
3242 	.num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3243 	.cpu_powergates = tegra114_cpu_powergates,
3244 	.has_tsense_reset = true,
3245 	.has_gpu_clamps = false,
3246 	.needs_mbist_war = false,
3247 	.has_impl_33v_pwr = false,
3248 	.maybe_tz_only = false,
3249 	.num_io_pads = 0,
3250 	.io_pads = NULL,
3251 	.num_pin_descs = 0,
3252 	.pin_descs = NULL,
3253 	.regs = &tegra20_pmc_regs,
3254 	.init = tegra20_pmc_init,
3255 	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3256 	.powergate_set = tegra114_powergate_set,
3257 	.reset_sources = tegra30_reset_sources,
3258 	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3259 	.reset_levels = NULL,
3260 	.num_reset_levels = 0,
3261 	.pmc_clks_data = tegra_pmc_clks_data,
3262 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3263 	.has_blink_output = true,
3264 	.has_usb_sleepwalk = true,
3265 };
3266 
3267 static const char * const tegra124_powergates[] = {
3268 	[TEGRA_POWERGATE_CPU] = "crail",
3269 	[TEGRA_POWERGATE_3D] = "3d",
3270 	[TEGRA_POWERGATE_VENC] = "venc",
3271 	[TEGRA_POWERGATE_PCIE] = "pcie",
3272 	[TEGRA_POWERGATE_VDEC] = "vdec",
3273 	[TEGRA_POWERGATE_MPE] = "mpe",
3274 	[TEGRA_POWERGATE_HEG] = "heg",
3275 	[TEGRA_POWERGATE_SATA] = "sata",
3276 	[TEGRA_POWERGATE_CPU1] = "cpu1",
3277 	[TEGRA_POWERGATE_CPU2] = "cpu2",
3278 	[TEGRA_POWERGATE_CPU3] = "cpu3",
3279 	[TEGRA_POWERGATE_CELP] = "celp",
3280 	[TEGRA_POWERGATE_CPU0] = "cpu0",
3281 	[TEGRA_POWERGATE_C0NC] = "c0nc",
3282 	[TEGRA_POWERGATE_C1NC] = "c1nc",
3283 	[TEGRA_POWERGATE_SOR] = "sor",
3284 	[TEGRA_POWERGATE_DIS] = "dis",
3285 	[TEGRA_POWERGATE_DISB] = "disb",
3286 	[TEGRA_POWERGATE_XUSBA] = "xusba",
3287 	[TEGRA_POWERGATE_XUSBB] = "xusbb",
3288 	[TEGRA_POWERGATE_XUSBC] = "xusbc",
3289 	[TEGRA_POWERGATE_VIC] = "vic",
3290 	[TEGRA_POWERGATE_IRAM] = "iram",
3291 };
3292 
3293 static const u8 tegra124_cpu_powergates[] = {
3294 	TEGRA_POWERGATE_CPU0,
3295 	TEGRA_POWERGATE_CPU1,
3296 	TEGRA_POWERGATE_CPU2,
3297 	TEGRA_POWERGATE_CPU3,
3298 };
3299 
3300 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name)	\
3301 	((struct tegra_io_pad_soc) {			\
3302 		.id	= (_id),			\
3303 		.dpd	= (_dpd),			\
3304 		.voltage = (_voltage),			\
3305 		.name	= (_name),			\
3306 	})
3307 
3308 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name)	\
3309 	((struct pinctrl_pin_desc) {			\
3310 		.number = (_id),			\
3311 		.name	= (_name)			\
3312 	})
3313 
3314 #define TEGRA124_IO_PAD_TABLE(_pad)                                   \
3315 	/* .id                          .dpd  .voltage  .name */      \
3316 	_pad(TEGRA_IO_PAD_AUDIO,        17,   UINT_MAX, "audio"),     \
3317 	_pad(TEGRA_IO_PAD_BB,           15,   UINT_MAX, "bb"),        \
3318 	_pad(TEGRA_IO_PAD_CAM,          36,   UINT_MAX, "cam"),       \
3319 	_pad(TEGRA_IO_PAD_COMP,         22,   UINT_MAX, "comp"),      \
3320 	_pad(TEGRA_IO_PAD_CSIA,         0,    UINT_MAX, "csia"),      \
3321 	_pad(TEGRA_IO_PAD_CSIB,         1,    UINT_MAX, "csb"),       \
3322 	_pad(TEGRA_IO_PAD_CSIE,         44,   UINT_MAX, "cse"),       \
3323 	_pad(TEGRA_IO_PAD_DSI,          2,    UINT_MAX, "dsi"),       \
3324 	_pad(TEGRA_IO_PAD_DSIB,         39,   UINT_MAX, "dsib"),      \
3325 	_pad(TEGRA_IO_PAD_DSIC,         40,   UINT_MAX, "dsic"),      \
3326 	_pad(TEGRA_IO_PAD_DSID,         41,   UINT_MAX, "dsid"),      \
3327 	_pad(TEGRA_IO_PAD_HDMI,         28,   UINT_MAX, "hdmi"),      \
3328 	_pad(TEGRA_IO_PAD_HSIC,         19,   UINT_MAX, "hsic"),      \
3329 	_pad(TEGRA_IO_PAD_HV,           38,   UINT_MAX, "hv"),        \
3330 	_pad(TEGRA_IO_PAD_LVDS,         57,   UINT_MAX, "lvds"),      \
3331 	_pad(TEGRA_IO_PAD_MIPI_BIAS,    3,    UINT_MAX, "mipi-bias"), \
3332 	_pad(TEGRA_IO_PAD_NAND,         13,   UINT_MAX, "nand"),      \
3333 	_pad(TEGRA_IO_PAD_PEX_BIAS,     4,    UINT_MAX, "pex-bias"),  \
3334 	_pad(TEGRA_IO_PAD_PEX_CLK1,     5,    UINT_MAX, "pex-clk1"),  \
3335 	_pad(TEGRA_IO_PAD_PEX_CLK2,     6,    UINT_MAX, "pex-clk2"),  \
3336 	_pad(TEGRA_IO_PAD_PEX_CNTRL,    32,   UINT_MAX, "pex-cntrl"), \
3337 	_pad(TEGRA_IO_PAD_SDMMC1,       33,   UINT_MAX, "sdmmc1"),    \
3338 	_pad(TEGRA_IO_PAD_SDMMC3,       34,   UINT_MAX, "sdmmc3"),    \
3339 	_pad(TEGRA_IO_PAD_SDMMC4,       35,   UINT_MAX, "sdmmc4"),    \
3340 	_pad(TEGRA_IO_PAD_SYS_DDC,      58,   UINT_MAX, "sys_ddc"),   \
3341 	_pad(TEGRA_IO_PAD_UART,         14,   UINT_MAX, "uart"),      \
3342 	_pad(TEGRA_IO_PAD_USB0,         9,    UINT_MAX, "usb0"),      \
3343 	_pad(TEGRA_IO_PAD_USB1,         10,   UINT_MAX, "usb1"),      \
3344 	_pad(TEGRA_IO_PAD_USB2,         11,   UINT_MAX, "usb2"),      \
3345 	_pad(TEGRA_IO_PAD_USB_BIAS,     12,   UINT_MAX, "usb_bias")
3346 
3347 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3348 	TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
3349 };
3350 
3351 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3352 	TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3353 };
3354 
3355 static const struct tegra_pmc_soc tegra124_pmc_soc = {
3356 	.supports_core_domain = false,
3357 	.num_powergates = ARRAY_SIZE(tegra124_powergates),
3358 	.powergates = tegra124_powergates,
3359 	.num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3360 	.cpu_powergates = tegra124_cpu_powergates,
3361 	.has_tsense_reset = true,
3362 	.has_gpu_clamps = true,
3363 	.needs_mbist_war = false,
3364 	.has_impl_33v_pwr = false,
3365 	.maybe_tz_only = false,
3366 	.num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3367 	.io_pads = tegra124_io_pads,
3368 	.num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3369 	.pin_descs = tegra124_pin_descs,
3370 	.regs = &tegra20_pmc_regs,
3371 	.init = tegra20_pmc_init,
3372 	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3373 	.powergate_set = tegra114_powergate_set,
3374 	.reset_sources = tegra30_reset_sources,
3375 	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3376 	.reset_levels = NULL,
3377 	.num_reset_levels = 0,
3378 	.pmc_clks_data = tegra_pmc_clks_data,
3379 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3380 	.has_blink_output = true,
3381 	.has_usb_sleepwalk = true,
3382 };
3383 
3384 static const char * const tegra210_powergates[] = {
3385 	[TEGRA_POWERGATE_CPU] = "crail",
3386 	[TEGRA_POWERGATE_3D] = "3d",
3387 	[TEGRA_POWERGATE_VENC] = "venc",
3388 	[TEGRA_POWERGATE_PCIE] = "pcie",
3389 	[TEGRA_POWERGATE_MPE] = "mpe",
3390 	[TEGRA_POWERGATE_SATA] = "sata",
3391 	[TEGRA_POWERGATE_CPU1] = "cpu1",
3392 	[TEGRA_POWERGATE_CPU2] = "cpu2",
3393 	[TEGRA_POWERGATE_CPU3] = "cpu3",
3394 	[TEGRA_POWERGATE_CPU0] = "cpu0",
3395 	[TEGRA_POWERGATE_C0NC] = "c0nc",
3396 	[TEGRA_POWERGATE_SOR] = "sor",
3397 	[TEGRA_POWERGATE_DIS] = "dis",
3398 	[TEGRA_POWERGATE_DISB] = "disb",
3399 	[TEGRA_POWERGATE_XUSBA] = "xusba",
3400 	[TEGRA_POWERGATE_XUSBB] = "xusbb",
3401 	[TEGRA_POWERGATE_XUSBC] = "xusbc",
3402 	[TEGRA_POWERGATE_VIC] = "vic",
3403 	[TEGRA_POWERGATE_IRAM] = "iram",
3404 	[TEGRA_POWERGATE_NVDEC] = "nvdec",
3405 	[TEGRA_POWERGATE_NVJPG] = "nvjpg",
3406 	[TEGRA_POWERGATE_AUD] = "aud",
3407 	[TEGRA_POWERGATE_DFD] = "dfd",
3408 	[TEGRA_POWERGATE_VE2] = "ve2",
3409 };
3410 
3411 static const u8 tegra210_cpu_powergates[] = {
3412 	TEGRA_POWERGATE_CPU0,
3413 	TEGRA_POWERGATE_CPU1,
3414 	TEGRA_POWERGATE_CPU2,
3415 	TEGRA_POWERGATE_CPU3,
3416 };
3417 
3418 #define TEGRA210_IO_PAD_TABLE(_pad)                                        \
3419 	/*   .id                        .dpd     .voltage  .name */        \
3420 	_pad(TEGRA_IO_PAD_AUDIO,       17,       5,        "audio"),       \
3421 	_pad(TEGRA_IO_PAD_AUDIO_HV,    61,       18,       "audio-hv"),    \
3422 	_pad(TEGRA_IO_PAD_CAM,         36,       10,       "cam"),         \
3423 	_pad(TEGRA_IO_PAD_CSIA,        0,        UINT_MAX, "csia"),        \
3424 	_pad(TEGRA_IO_PAD_CSIB,        1,        UINT_MAX, "csib"),        \
3425 	_pad(TEGRA_IO_PAD_CSIC,        42,       UINT_MAX, "csic"),        \
3426 	_pad(TEGRA_IO_PAD_CSID,        43,       UINT_MAX, "csid"),        \
3427 	_pad(TEGRA_IO_PAD_CSIE,        44,       UINT_MAX, "csie"),        \
3428 	_pad(TEGRA_IO_PAD_CSIF,        45,       UINT_MAX, "csif"),        \
3429 	_pad(TEGRA_IO_PAD_DBG,         25,       19,       "dbg"),         \
3430 	_pad(TEGRA_IO_PAD_DEBUG_NONAO, 26,       UINT_MAX, "debug-nonao"), \
3431 	_pad(TEGRA_IO_PAD_DMIC,        50,       20,       "dmic"),        \
3432 	_pad(TEGRA_IO_PAD_DP,          51,       UINT_MAX, "dp"),          \
3433 	_pad(TEGRA_IO_PAD_DSI,         2,        UINT_MAX, "dsi"),         \
3434 	_pad(TEGRA_IO_PAD_DSIB,        39,       UINT_MAX, "dsib"),        \
3435 	_pad(TEGRA_IO_PAD_DSIC,        40,       UINT_MAX, "dsic"),        \
3436 	_pad(TEGRA_IO_PAD_DSID,        41,       UINT_MAX, "dsid"),        \
3437 	_pad(TEGRA_IO_PAD_EMMC,        35,       UINT_MAX, "emmc"),        \
3438 	_pad(TEGRA_IO_PAD_EMMC2,       37,       UINT_MAX, "emmc2"),       \
3439 	_pad(TEGRA_IO_PAD_GPIO,        27,       21,       "gpio"),        \
3440 	_pad(TEGRA_IO_PAD_HDMI,        28,       UINT_MAX, "hdmi"),        \
3441 	_pad(TEGRA_IO_PAD_HSIC,        19,       UINT_MAX, "hsic"),        \
3442 	_pad(TEGRA_IO_PAD_LVDS,        57,       UINT_MAX, "lvds"),        \
3443 	_pad(TEGRA_IO_PAD_MIPI_BIAS,   3,        UINT_MAX, "mipi-bias"),   \
3444 	_pad(TEGRA_IO_PAD_PEX_BIAS,    4,        UINT_MAX, "pex-bias"),    \
3445 	_pad(TEGRA_IO_PAD_PEX_CLK1,    5,        UINT_MAX, "pex-clk1"),    \
3446 	_pad(TEGRA_IO_PAD_PEX_CLK2,    6,        UINT_MAX, "pex-clk2"),    \
3447 	_pad(TEGRA_IO_PAD_PEX_CNTRL,   UINT_MAX, 11,       "pex-cntrl"),   \
3448 	_pad(TEGRA_IO_PAD_SDMMC1,      33,       12,       "sdmmc1"),      \
3449 	_pad(TEGRA_IO_PAD_SDMMC3,      34,       13,       "sdmmc3"),      \
3450 	_pad(TEGRA_IO_PAD_SPI,         46,       22,       "spi"),         \
3451 	_pad(TEGRA_IO_PAD_SPI_HV,      47,       23,       "spi-hv"),      \
3452 	_pad(TEGRA_IO_PAD_UART,        14,       2,        "uart"),        \
3453 	_pad(TEGRA_IO_PAD_USB0,        9,        UINT_MAX, "usb0"),        \
3454 	_pad(TEGRA_IO_PAD_USB1,        10,       UINT_MAX, "usb1"),        \
3455 	_pad(TEGRA_IO_PAD_USB2,        11,       UINT_MAX, "usb2"),        \
3456 	_pad(TEGRA_IO_PAD_USB3,        18,       UINT_MAX, "usb3"),        \
3457 	_pad(TEGRA_IO_PAD_USB_BIAS,    12,       UINT_MAX, "usb-bias")
3458 
3459 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3460 	TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
3461 };
3462 
3463 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3464 	TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3465 };
3466 
3467 static const char * const tegra210_reset_sources[] = {
3468 	"POWER_ON_RESET",
3469 	"WATCHDOG",
3470 	"SENSOR",
3471 	"SW_MAIN",
3472 	"LP0",
3473 	"AOTAG"
3474 };
3475 
3476 static const struct tegra_wake_event tegra210_wake_events[] = {
3477 	TEGRA_WAKE_IRQ("rtc", 16, 2),
3478 	TEGRA_WAKE_IRQ("pmu", 51, 86),
3479 };
3480 
3481 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3482 	.supports_core_domain = false,
3483 	.num_powergates = ARRAY_SIZE(tegra210_powergates),
3484 	.powergates = tegra210_powergates,
3485 	.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3486 	.cpu_powergates = tegra210_cpu_powergates,
3487 	.has_tsense_reset = true,
3488 	.has_gpu_clamps = true,
3489 	.needs_mbist_war = true,
3490 	.has_impl_33v_pwr = false,
3491 	.maybe_tz_only = true,
3492 	.num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3493 	.io_pads = tegra210_io_pads,
3494 	.num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3495 	.pin_descs = tegra210_pin_descs,
3496 	.regs = &tegra20_pmc_regs,
3497 	.init = tegra20_pmc_init,
3498 	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3499 	.powergate_set = tegra114_powergate_set,
3500 	.irq_set_wake = tegra210_pmc_irq_set_wake,
3501 	.irq_set_type = tegra210_pmc_irq_set_type,
3502 	.reset_sources = tegra210_reset_sources,
3503 	.num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3504 	.reset_levels = NULL,
3505 	.num_reset_levels = 0,
3506 	.num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3507 	.wake_events = tegra210_wake_events,
3508 	.pmc_clks_data = tegra_pmc_clks_data,
3509 	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3510 	.has_blink_output = true,
3511 	.has_usb_sleepwalk = true,
3512 };
3513 
3514 #define TEGRA186_IO_PAD_TABLE(_pad)                                          \
3515 	/*   .id                        .dpd      .voltage  .name */         \
3516 	_pad(TEGRA_IO_PAD_CSIA,         0,        UINT_MAX, "csia"),         \
3517 	_pad(TEGRA_IO_PAD_CSIB,         1,        UINT_MAX, "csib"),         \
3518 	_pad(TEGRA_IO_PAD_DSI,          2,        UINT_MAX, "dsi"),          \
3519 	_pad(TEGRA_IO_PAD_MIPI_BIAS,    3,        UINT_MAX, "mipi-bias"),    \
3520 	_pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4,        UINT_MAX, "pex-clk-bias"), \
3521 	_pad(TEGRA_IO_PAD_PEX_CLK3,     5,        UINT_MAX, "pex-clk3"),     \
3522 	_pad(TEGRA_IO_PAD_PEX_CLK2,     6,        UINT_MAX, "pex-clk2"),     \
3523 	_pad(TEGRA_IO_PAD_PEX_CLK1,     7,        UINT_MAX, "pex-clk1"),     \
3524 	_pad(TEGRA_IO_PAD_USB0,         9,        UINT_MAX, "usb0"),         \
3525 	_pad(TEGRA_IO_PAD_USB1,         10,       UINT_MAX, "usb1"),         \
3526 	_pad(TEGRA_IO_PAD_USB2,         11,       UINT_MAX, "usb2"),         \
3527 	_pad(TEGRA_IO_PAD_USB_BIAS,     12,       UINT_MAX, "usb-bias"),     \
3528 	_pad(TEGRA_IO_PAD_UART,         14,       UINT_MAX, "uart"),         \
3529 	_pad(TEGRA_IO_PAD_AUDIO,        17,       UINT_MAX, "audio"),        \
3530 	_pad(TEGRA_IO_PAD_HSIC,         19,       UINT_MAX, "hsic"),         \
3531 	_pad(TEGRA_IO_PAD_DBG,          25,       UINT_MAX, "dbg"),          \
3532 	_pad(TEGRA_IO_PAD_HDMI_DP0,     28,       UINT_MAX, "hdmi-dp0"),     \
3533 	_pad(TEGRA_IO_PAD_HDMI_DP1,     29,       UINT_MAX, "hdmi-dp1"),     \
3534 	_pad(TEGRA_IO_PAD_PEX_CNTRL,    32,       UINT_MAX, "pex-cntrl"),    \
3535 	_pad(TEGRA_IO_PAD_SDMMC2_HV,    34,       5,        "sdmmc2-hv"),    \
3536 	_pad(TEGRA_IO_PAD_SDMMC4,       36,       UINT_MAX, "sdmmc4"),       \
3537 	_pad(TEGRA_IO_PAD_CAM,          38,       UINT_MAX, "cam"),          \
3538 	_pad(TEGRA_IO_PAD_DSIB,         40,       UINT_MAX, "dsib"),         \
3539 	_pad(TEGRA_IO_PAD_DSIC,         41,       UINT_MAX, "dsic"),         \
3540 	_pad(TEGRA_IO_PAD_DSID,         42,       UINT_MAX, "dsid"),         \
3541 	_pad(TEGRA_IO_PAD_CSIC,         43,       UINT_MAX, "csic"),         \
3542 	_pad(TEGRA_IO_PAD_CSID,         44,       UINT_MAX, "csid"),         \
3543 	_pad(TEGRA_IO_PAD_CSIE,         45,       UINT_MAX, "csie"),         \
3544 	_pad(TEGRA_IO_PAD_CSIF,         46,       UINT_MAX, "csif"),         \
3545 	_pad(TEGRA_IO_PAD_SPI,          47,       UINT_MAX, "spi"),          \
3546 	_pad(TEGRA_IO_PAD_UFS,          49,       UINT_MAX, "ufs"),          \
3547 	_pad(TEGRA_IO_PAD_DMIC_HV,      52,       2,        "dmic-hv"),	     \
3548 	_pad(TEGRA_IO_PAD_EDP,          53,       UINT_MAX, "edp"),          \
3549 	_pad(TEGRA_IO_PAD_SDMMC1_HV,    55,       4,        "sdmmc1-hv"),    \
3550 	_pad(TEGRA_IO_PAD_SDMMC3_HV,    56,       6,        "sdmmc3-hv"),    \
3551 	_pad(TEGRA_IO_PAD_CONN,         60,       UINT_MAX, "conn"),         \
3552 	_pad(TEGRA_IO_PAD_AUDIO_HV,     61,       1,        "audio-hv"),     \
3553 	_pad(TEGRA_IO_PAD_AO_HV,        UINT_MAX, 0,        "ao-hv")
3554 
3555 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3556 	TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
3557 };
3558 
3559 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3560 	TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3561 };
3562 
3563 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3564 	.scratch0 = 0x2000,
3565 	.dpd_req = 0x74,
3566 	.dpd_status = 0x78,
3567 	.dpd2_req = 0x7c,
3568 	.dpd2_status = 0x80,
3569 	.rst_status = 0x70,
3570 	.rst_source_shift = 0x2,
3571 	.rst_source_mask = 0x3c,
3572 	.rst_level_shift = 0x0,
3573 	.rst_level_mask = 0x3,
3574 };
3575 
tegra186_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)3576 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3577 					    struct device_node *np,
3578 					    bool invert)
3579 {
3580 	struct resource regs;
3581 	void __iomem *wake;
3582 	u32 value;
3583 	int index;
3584 
3585 	index = of_property_match_string(np, "reg-names", "wake");
3586 	if (index < 0) {
3587 		dev_err(pmc->dev, "failed to find PMC wake registers\n");
3588 		return;
3589 	}
3590 
3591 	of_address_to_resource(np, index, &regs);
3592 
3593 	wake = ioremap(regs.start, resource_size(&regs));
3594 	if (!wake) {
3595 		dev_err(pmc->dev, "failed to map PMC wake registers\n");
3596 		return;
3597 	}
3598 
3599 	value = readl(wake + WAKE_AOWAKE_CTRL);
3600 
3601 	if (invert)
3602 		value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3603 	else
3604 		value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3605 
3606 	writel(value, wake + WAKE_AOWAKE_CTRL);
3607 
3608 	iounmap(wake);
3609 }
3610 
3611 static const char * const tegra186_reset_sources[] = {
3612 	"SYS_RESET",
3613 	"AOWDT",
3614 	"MCCPLEXWDT",
3615 	"BPMPWDT",
3616 	"SCEWDT",
3617 	"SPEWDT",
3618 	"APEWDT",
3619 	"BCCPLEXWDT",
3620 	"SENSOR",
3621 	"AOTAG",
3622 	"VFSENSOR",
3623 	"SWREST",
3624 	"SC7",
3625 	"HSM",
3626 	"CORESIGHT"
3627 };
3628 
3629 static const char * const tegra186_reset_levels[] = {
3630 	"L0", "L1", "L2", "WARM"
3631 };
3632 
3633 static const struct tegra_wake_event tegra186_wake_events[] = {
3634 	TEGRA_WAKE_IRQ("pmu", 24, 209),
3635 	TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3636 	TEGRA_WAKE_IRQ("rtc", 73, 10),
3637 };
3638 
3639 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3640 	.supports_core_domain = false,
3641 	.num_powergates = 0,
3642 	.powergates = NULL,
3643 	.num_cpu_powergates = 0,
3644 	.cpu_powergates = NULL,
3645 	.has_tsense_reset = false,
3646 	.has_gpu_clamps = false,
3647 	.needs_mbist_war = false,
3648 	.has_impl_33v_pwr = true,
3649 	.maybe_tz_only = false,
3650 	.num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3651 	.io_pads = tegra186_io_pads,
3652 	.num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3653 	.pin_descs = tegra186_pin_descs,
3654 	.regs = &tegra186_pmc_regs,
3655 	.init = NULL,
3656 	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3657 	.irq_set_wake = tegra186_pmc_irq_set_wake,
3658 	.irq_set_type = tegra186_pmc_irq_set_type,
3659 	.reset_sources = tegra186_reset_sources,
3660 	.num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3661 	.reset_levels = tegra186_reset_levels,
3662 	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3663 	.num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3664 	.wake_events = tegra186_wake_events,
3665 	.pmc_clks_data = NULL,
3666 	.num_pmc_clks = 0,
3667 	.has_blink_output = false,
3668 	.has_usb_sleepwalk = false,
3669 };
3670 
3671 #define TEGRA194_IO_PAD_TABLE(_pad)                                              \
3672 	/*   .id                          .dpd      .voltage  .name */           \
3673 	_pad(TEGRA_IO_PAD_CSIA,           0,        UINT_MAX, "csia"),           \
3674 	_pad(TEGRA_IO_PAD_CSIB,           1,        UINT_MAX, "csib"),           \
3675 	_pad(TEGRA_IO_PAD_MIPI_BIAS,      3,        UINT_MAX, "mipi-bias"),      \
3676 	_pad(TEGRA_IO_PAD_PEX_CLK_BIAS,   4,        UINT_MAX, "pex-clk-bias"),   \
3677 	_pad(TEGRA_IO_PAD_PEX_CLK3,       5,        UINT_MAX, "pex-clk3"),       \
3678 	_pad(TEGRA_IO_PAD_PEX_CLK2,       6,        UINT_MAX, "pex-clk2"),       \
3679 	_pad(TEGRA_IO_PAD_PEX_CLK1,       7,        UINT_MAX, "pex-clk1"),       \
3680 	_pad(TEGRA_IO_PAD_EQOS,           8,        UINT_MAX, "eqos"),           \
3681 	_pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9,        UINT_MAX, "pex-clk-2-bias"), \
3682 	_pad(TEGRA_IO_PAD_PEX_CLK_2,      10,       UINT_MAX, "pex-clk-2"),      \
3683 	_pad(TEGRA_IO_PAD_DAP3,           11,       UINT_MAX, "dap3"),           \
3684 	_pad(TEGRA_IO_PAD_DAP5,           12,       UINT_MAX, "dap5"),           \
3685 	_pad(TEGRA_IO_PAD_UART,           14,       UINT_MAX, "uart"),           \
3686 	_pad(TEGRA_IO_PAD_PWR_CTL,        15,       UINT_MAX, "pwr-ctl"),        \
3687 	_pad(TEGRA_IO_PAD_SOC_GPIO53,     16,       UINT_MAX, "soc-gpio53"),     \
3688 	_pad(TEGRA_IO_PAD_AUDIO,          17,       UINT_MAX, "audio"),          \
3689 	_pad(TEGRA_IO_PAD_GP_PWM2,        18,       UINT_MAX, "gp-pwm2"),        \
3690 	_pad(TEGRA_IO_PAD_GP_PWM3,        19,       UINT_MAX, "gp-pwm3"),        \
3691 	_pad(TEGRA_IO_PAD_SOC_GPIO12,     20,       UINT_MAX, "soc-gpio12"),     \
3692 	_pad(TEGRA_IO_PAD_SOC_GPIO13,     21,       UINT_MAX, "soc-gpio13"),     \
3693 	_pad(TEGRA_IO_PAD_SOC_GPIO10,     22,       UINT_MAX, "soc-gpio10"),     \
3694 	_pad(TEGRA_IO_PAD_UART4,          23,       UINT_MAX, "uart4"),          \
3695 	_pad(TEGRA_IO_PAD_UART5,          24,       UINT_MAX, "uart5"),          \
3696 	_pad(TEGRA_IO_PAD_DBG,            25,       UINT_MAX, "dbg"),            \
3697 	_pad(TEGRA_IO_PAD_HDMI_DP3,       26,       UINT_MAX, "hdmi-dp3"),       \
3698 	_pad(TEGRA_IO_PAD_HDMI_DP2,       27,       UINT_MAX, "hdmi-dp2"),       \
3699 	_pad(TEGRA_IO_PAD_HDMI_DP0,       28,       UINT_MAX, "hdmi-dp0"),       \
3700 	_pad(TEGRA_IO_PAD_HDMI_DP1,       29,       UINT_MAX, "hdmi-dp1"),       \
3701 	_pad(TEGRA_IO_PAD_PEX_CNTRL,      32,       UINT_MAX, "pex-cntrl"),      \
3702 	_pad(TEGRA_IO_PAD_PEX_CTL2,       33,       UINT_MAX, "pex-ctl2"),       \
3703 	_pad(TEGRA_IO_PAD_PEX_L0_RST_N,   34,       UINT_MAX, "pex-l0-rst"),     \
3704 	_pad(TEGRA_IO_PAD_PEX_L1_RST_N,   35,       UINT_MAX, "pex-l1-rst"),     \
3705 	_pad(TEGRA_IO_PAD_SDMMC4,         36,       UINT_MAX, "sdmmc4"),         \
3706 	_pad(TEGRA_IO_PAD_PEX_L5_RST_N,   37,       UINT_MAX, "pex-l5-rst"),     \
3707 	_pad(TEGRA_IO_PAD_CAM,            38,       UINT_MAX, "cam"),            \
3708 	_pad(TEGRA_IO_PAD_CSIC,           43,       UINT_MAX, "csic"),           \
3709 	_pad(TEGRA_IO_PAD_CSID,           44,       UINT_MAX, "csid"),           \
3710 	_pad(TEGRA_IO_PAD_CSIE,           45,       UINT_MAX, "csie"),           \
3711 	_pad(TEGRA_IO_PAD_CSIF,           46,       UINT_MAX, "csif"),           \
3712 	_pad(TEGRA_IO_PAD_SPI,            47,       UINT_MAX, "spi"),            \
3713 	_pad(TEGRA_IO_PAD_UFS,            49,       UINT_MAX, "ufs"),            \
3714 	_pad(TEGRA_IO_PAD_CSIG,           50,       UINT_MAX, "csig"),           \
3715 	_pad(TEGRA_IO_PAD_CSIH,           51,       UINT_MAX, "csih"),           \
3716 	_pad(TEGRA_IO_PAD_EDP,            53,       UINT_MAX, "edp"),            \
3717 	_pad(TEGRA_IO_PAD_SDMMC1_HV,      55,       4,        "sdmmc1-hv"),      \
3718 	_pad(TEGRA_IO_PAD_SDMMC3_HV,      56,       6,        "sdmmc3-hv"),      \
3719 	_pad(TEGRA_IO_PAD_CONN,           60,       UINT_MAX, "conn"),           \
3720 	_pad(TEGRA_IO_PAD_AUDIO_HV,       61,       1,        "audio-hv"),       \
3721 	_pad(TEGRA_IO_PAD_AO_HV,          UINT_MAX, 0,        "ao-hv")
3722 
3723 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3724 	TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
3725 };
3726 
3727 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3728 	TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3729 };
3730 
3731 static const struct tegra_pmc_regs tegra194_pmc_regs = {
3732 	.scratch0 = 0x2000,
3733 	.dpd_req = 0x74,
3734 	.dpd_status = 0x78,
3735 	.dpd2_req = 0x7c,
3736 	.dpd2_status = 0x80,
3737 	.rst_status = 0x70,
3738 	.rst_source_shift = 0x2,
3739 	.rst_source_mask = 0x7c,
3740 	.rst_level_shift = 0x0,
3741 	.rst_level_mask = 0x3,
3742 };
3743 
3744 static const char * const tegra194_reset_sources[] = {
3745 	"SYS_RESET_N",
3746 	"AOWDT",
3747 	"BCCPLEXWDT",
3748 	"BPMPWDT",
3749 	"SCEWDT",
3750 	"SPEWDT",
3751 	"APEWDT",
3752 	"LCCPLEXWDT",
3753 	"SENSOR",
3754 	"AOTAG",
3755 	"VFSENSOR",
3756 	"MAINSWRST",
3757 	"SC7",
3758 	"HSM",
3759 	"CSITE",
3760 	"RCEWDT",
3761 	"PVA0WDT",
3762 	"PVA1WDT",
3763 	"L1A_ASYNC",
3764 	"BPMPBOOT",
3765 	"FUSECRC",
3766 };
3767 
3768 static const struct tegra_wake_event tegra194_wake_events[] = {
3769 	TEGRA_WAKE_IRQ("pmu", 24, 209),
3770 	TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3771 	TEGRA_WAKE_IRQ("rtc", 73, 10),
3772 	TEGRA_WAKE_SIMPLE("usb3-port-0", 76),
3773 	TEGRA_WAKE_SIMPLE("usb3-port-1", 77),
3774 	TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78),
3775 	TEGRA_WAKE_SIMPLE("usb2-port-0", 79),
3776 	TEGRA_WAKE_SIMPLE("usb2-port-1", 80),
3777 	TEGRA_WAKE_SIMPLE("usb2-port-2", 81),
3778 	TEGRA_WAKE_SIMPLE("usb2-port-3", 82),
3779 };
3780 
3781 static const struct tegra_pmc_soc tegra194_pmc_soc = {
3782 	.supports_core_domain = false,
3783 	.num_powergates = 0,
3784 	.powergates = NULL,
3785 	.num_cpu_powergates = 0,
3786 	.cpu_powergates = NULL,
3787 	.has_tsense_reset = false,
3788 	.has_gpu_clamps = false,
3789 	.needs_mbist_war = false,
3790 	.has_impl_33v_pwr = true,
3791 	.maybe_tz_only = false,
3792 	.num_io_pads = ARRAY_SIZE(tegra194_io_pads),
3793 	.io_pads = tegra194_io_pads,
3794 	.num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
3795 	.pin_descs = tegra194_pin_descs,
3796 	.regs = &tegra194_pmc_regs,
3797 	.init = NULL,
3798 	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3799 	.irq_set_wake = tegra186_pmc_irq_set_wake,
3800 	.irq_set_type = tegra186_pmc_irq_set_type,
3801 	.reset_sources = tegra194_reset_sources,
3802 	.num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
3803 	.reset_levels = tegra186_reset_levels,
3804 	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3805 	.num_wake_events = ARRAY_SIZE(tegra194_wake_events),
3806 	.wake_events = tegra194_wake_events,
3807 	.pmc_clks_data = NULL,
3808 	.num_pmc_clks = 0,
3809 	.has_blink_output = false,
3810 	.has_usb_sleepwalk = false,
3811 };
3812 
3813 static const struct tegra_pmc_regs tegra234_pmc_regs = {
3814 	.scratch0 = 0x2000,
3815 	.dpd_req = 0,
3816 	.dpd_status = 0,
3817 	.dpd2_req = 0,
3818 	.dpd2_status = 0,
3819 	.rst_status = 0x70,
3820 	.rst_source_shift = 0x2,
3821 	.rst_source_mask = 0xfc,
3822 	.rst_level_shift = 0x0,
3823 	.rst_level_mask = 0x3,
3824 };
3825 
3826 static const char * const tegra234_reset_sources[] = {
3827 	"SYS_RESET_N",	/* 0x0 */
3828 	"AOWDT",
3829 	"BCCPLEXWDT",
3830 	"BPMPWDT",
3831 	"SCEWDT",
3832 	"SPEWDT",
3833 	"APEWDT",
3834 	"LCCPLEXWDT",
3835 	"SENSOR",	/* 0x8 */
3836 	NULL,
3837 	NULL,
3838 	"MAINSWRST",
3839 	"SC7",
3840 	"HSM",
3841 	NULL,
3842 	"RCEWDT",
3843 	NULL,		/* 0x10 */
3844 	NULL,
3845 	NULL,
3846 	"BPMPBOOT",
3847 	"FUSECRC",
3848 	"DCEWDT",
3849 	"PSCWDT",
3850 	"PSC",
3851 	"CSITE_SW",	/* 0x18 */
3852 	"POD",
3853 	"SCPM",
3854 	"VREFRO_POWERBAD",
3855 	"VMON",
3856 	"FMON",
3857 	"FSI_R5WDT",
3858 	"FSI_THERM",
3859 	"FSI_R52C0WDT",	/* 0x20 */
3860 	"FSI_R52C1WDT",
3861 	"FSI_R52C2WDT",
3862 	"FSI_R52C3WDT",
3863 	"FSI_FMON",
3864 	"FSI_VMON",	/* 0x25 */
3865 };
3866 
3867 static const struct tegra_wake_event tegra234_wake_events[] = {
3868 	TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)),
3869 	TEGRA_WAKE_IRQ("rtc", 73, 10),
3870 };
3871 
3872 static const struct tegra_pmc_soc tegra234_pmc_soc = {
3873 	.supports_core_domain = false,
3874 	.num_powergates = 0,
3875 	.powergates = NULL,
3876 	.num_cpu_powergates = 0,
3877 	.cpu_powergates = NULL,
3878 	.has_tsense_reset = false,
3879 	.has_gpu_clamps = false,
3880 	.needs_mbist_war = false,
3881 	.has_impl_33v_pwr = true,
3882 	.maybe_tz_only = false,
3883 	.num_io_pads = 0,
3884 	.io_pads = NULL,
3885 	.num_pin_descs = 0,
3886 	.pin_descs = NULL,
3887 	.regs = &tegra234_pmc_regs,
3888 	.init = NULL,
3889 	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3890 	.irq_set_wake = tegra186_pmc_irq_set_wake,
3891 	.irq_set_type = tegra186_pmc_irq_set_type,
3892 	.reset_sources = tegra234_reset_sources,
3893 	.num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
3894 	.reset_levels = tegra186_reset_levels,
3895 	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3896 	.num_wake_events = ARRAY_SIZE(tegra234_wake_events),
3897 	.wake_events = tegra234_wake_events,
3898 	.pmc_clks_data = NULL,
3899 	.num_pmc_clks = 0,
3900 	.has_blink_output = false,
3901 };
3902 
3903 static const struct of_device_id tegra_pmc_match[] = {
3904 	{ .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3905 	{ .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3906 	{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3907 	{ .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3908 	{ .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3909 	{ .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3910 	{ .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3911 	{ .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3912 	{ .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3913 	{ }
3914 };
3915 
tegra_pmc_sync_state(struct device * dev)3916 static void tegra_pmc_sync_state(struct device *dev)
3917 {
3918 	int err;
3919 
3920 	/*
3921 	 * Newer device-trees have power domains, but we need to prepare all
3922 	 * device drivers with runtime PM and OPP support first, otherwise
3923 	 * state syncing is unsafe.
3924 	 */
3925 	if (!pmc->soc->supports_core_domain)
3926 		return;
3927 
3928 	/*
3929 	 * Older device-trees don't have core PD, and thus, there are
3930 	 * no dependencies that will block the state syncing. We shouldn't
3931 	 * mark the domain as synced in this case.
3932 	 */
3933 	if (!pmc->core_domain_registered)
3934 		return;
3935 
3936 	pmc->core_domain_state_synced = true;
3937 
3938 	/* this is a no-op if core regulator isn't used */
3939 	mutex_lock(&pmc->powergates_lock);
3940 	err = dev_pm_opp_sync_regulators(dev);
3941 	mutex_unlock(&pmc->powergates_lock);
3942 
3943 	if (err)
3944 		dev_err(dev, "failed to sync regulators: %d\n", err);
3945 }
3946 
3947 static struct platform_driver tegra_pmc_driver = {
3948 	.driver = {
3949 		.name = "tegra-pmc",
3950 		.suppress_bind_attrs = true,
3951 		.of_match_table = tegra_pmc_match,
3952 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3953 		.pm = &tegra_pmc_pm_ops,
3954 #endif
3955 		.sync_state = tegra_pmc_sync_state,
3956 	},
3957 	.probe = tegra_pmc_probe,
3958 };
3959 builtin_platform_driver(tegra_pmc_driver);
3960 
tegra_pmc_detect_tz_only(struct tegra_pmc * pmc)3961 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3962 {
3963 	u32 value, saved;
3964 
3965 	saved = readl(pmc->base + pmc->soc->regs->scratch0);
3966 	value = saved ^ 0xffffffff;
3967 
3968 	if (value == 0xffffffff)
3969 		value = 0xdeadbeef;
3970 
3971 	/* write pattern and read it back */
3972 	writel(value, pmc->base + pmc->soc->regs->scratch0);
3973 	value = readl(pmc->base + pmc->soc->regs->scratch0);
3974 
3975 	/* if we read all-zeroes, access is restricted to TZ only */
3976 	if (value == 0) {
3977 		pr_info("access to PMC is restricted to TZ\n");
3978 		return true;
3979 	}
3980 
3981 	/* restore original value */
3982 	writel(saved, pmc->base + pmc->soc->regs->scratch0);
3983 
3984 	return false;
3985 }
3986 
3987 /*
3988  * Early initialization to allow access to registers in the very early boot
3989  * process.
3990  */
tegra_pmc_early_init(void)3991 static int __init tegra_pmc_early_init(void)
3992 {
3993 	const struct of_device_id *match;
3994 	struct device_node *np;
3995 	struct resource regs;
3996 	unsigned int i;
3997 	bool invert;
3998 
3999 	mutex_init(&pmc->powergates_lock);
4000 
4001 	np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
4002 	if (!np) {
4003 		/*
4004 		 * Fall back to legacy initialization for 32-bit ARM only. All
4005 		 * 64-bit ARM device tree files for Tegra are required to have
4006 		 * a PMC node.
4007 		 *
4008 		 * This is for backwards-compatibility with old device trees
4009 		 * that didn't contain a PMC node. Note that in this case the
4010 		 * SoC data can't be matched and therefore powergating is
4011 		 * disabled.
4012 		 */
4013 		if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
4014 			pr_warn("DT node not found, powergating disabled\n");
4015 
4016 			regs.start = 0x7000e400;
4017 			regs.end = 0x7000e7ff;
4018 			regs.flags = IORESOURCE_MEM;
4019 
4020 			pr_warn("Using memory region %pR\n", &regs);
4021 		} else {
4022 			/*
4023 			 * At this point we're not running on Tegra, so play
4024 			 * nice with multi-platform kernels.
4025 			 */
4026 			return 0;
4027 		}
4028 	} else {
4029 		/*
4030 		 * Extract information from the device tree if we've found a
4031 		 * matching node.
4032 		 */
4033 		if (of_address_to_resource(np, 0, &regs) < 0) {
4034 			pr_err("failed to get PMC registers\n");
4035 			of_node_put(np);
4036 			return -ENXIO;
4037 		}
4038 	}
4039 
4040 	pmc->base = ioremap(regs.start, resource_size(&regs));
4041 	if (!pmc->base) {
4042 		pr_err("failed to map PMC registers\n");
4043 		of_node_put(np);
4044 		return -ENXIO;
4045 	}
4046 
4047 	if (of_device_is_available(np)) {
4048 		pmc->soc = match->data;
4049 
4050 		if (pmc->soc->maybe_tz_only)
4051 			pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
4052 
4053 		/* Create a bitmap of the available and valid partitions */
4054 		for (i = 0; i < pmc->soc->num_powergates; i++)
4055 			if (pmc->soc->powergates[i])
4056 				set_bit(i, pmc->powergates_available);
4057 
4058 		/*
4059 		 * Invert the interrupt polarity if a PMC device tree node
4060 		 * exists and contains the nvidia,invert-interrupt property.
4061 		 */
4062 		invert = of_property_read_bool(np, "nvidia,invert-interrupt");
4063 
4064 		pmc->soc->setup_irq_polarity(pmc, np, invert);
4065 
4066 		of_node_put(np);
4067 	}
4068 
4069 	return 0;
4070 }
4071 early_initcall(tegra_pmc_early_init);
4072