1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3
4 #include <linux/err.h>
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/debugfs.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/serial_8250.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/platform_device.h>
14 #include <linux/platform_data/i2c-xiic.h>
15 #include <linux/ptp_clock_kernel.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/xilinx_spi.h>
18 #include <net/devlink.h>
19 #include <linux/i2c.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/nvmem-consumer.h>
22 #include <linux/crc16.h>
23
24 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
25 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
26
27 #define PCI_VENDOR_ID_CELESTICA 0x18d4
28 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
29
30 static struct class timecard_class = {
31 .owner = THIS_MODULE,
32 .name = "timecard",
33 };
34
35 struct ocp_reg {
36 u32 ctrl;
37 u32 status;
38 u32 select;
39 u32 version;
40 u32 time_ns;
41 u32 time_sec;
42 u32 __pad0[2];
43 u32 adjust_ns;
44 u32 adjust_sec;
45 u32 __pad1[2];
46 u32 offset_ns;
47 u32 offset_window_ns;
48 u32 __pad2[2];
49 u32 drift_ns;
50 u32 drift_window_ns;
51 u32 __pad3[6];
52 u32 servo_offset_p;
53 u32 servo_offset_i;
54 u32 servo_drift_p;
55 u32 servo_drift_i;
56 u32 status_offset;
57 u32 status_drift;
58 };
59
60 #define OCP_CTRL_ENABLE BIT(0)
61 #define OCP_CTRL_ADJUST_TIME BIT(1)
62 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
63 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
64 #define OCP_CTRL_ADJUST_SERVO BIT(8)
65 #define OCP_CTRL_READ_TIME_REQ BIT(30)
66 #define OCP_CTRL_READ_TIME_DONE BIT(31)
67
68 #define OCP_STATUS_IN_SYNC BIT(0)
69 #define OCP_STATUS_IN_HOLDOVER BIT(1)
70
71 #define OCP_SELECT_CLK_NONE 0
72 #define OCP_SELECT_CLK_REG 0xfe
73
74 struct tod_reg {
75 u32 ctrl;
76 u32 status;
77 u32 uart_polarity;
78 u32 version;
79 u32 adj_sec;
80 u32 __pad0[3];
81 u32 uart_baud;
82 u32 __pad1[3];
83 u32 utc_status;
84 u32 leap;
85 };
86
87 #define TOD_CTRL_PROTOCOL BIT(28)
88 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
89 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
90 #define TOD_CTRL_ENABLE BIT(0)
91 #define TOD_CTRL_GNSS_MASK ((1U << 4) - 1)
92 #define TOD_CTRL_GNSS_SHIFT 24
93
94 #define TOD_STATUS_UTC_MASK 0xff
95 #define TOD_STATUS_UTC_VALID BIT(8)
96 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
97 #define TOD_STATUS_LEAP_VALID BIT(16)
98
99 struct ts_reg {
100 u32 enable;
101 u32 error;
102 u32 polarity;
103 u32 version;
104 u32 __pad0[4];
105 u32 cable_delay;
106 u32 __pad1[3];
107 u32 intr;
108 u32 intr_mask;
109 u32 event_count;
110 u32 __pad2[1];
111 u32 ts_count;
112 u32 time_ns;
113 u32 time_sec;
114 u32 data_width;
115 u32 data;
116 };
117
118 struct pps_reg {
119 u32 ctrl;
120 u32 status;
121 u32 __pad0[6];
122 u32 cable_delay;
123 };
124
125 #define PPS_STATUS_FILTER_ERR BIT(0)
126 #define PPS_STATUS_SUPERV_ERR BIT(1)
127
128 struct img_reg {
129 u32 version;
130 };
131
132 struct gpio_reg {
133 u32 gpio1;
134 u32 __pad0;
135 u32 gpio2;
136 u32 __pad1;
137 };
138
139 struct irig_master_reg {
140 u32 ctrl;
141 u32 status;
142 u32 __pad0;
143 u32 version;
144 u32 adj_sec;
145 u32 mode_ctrl;
146 };
147
148 #define IRIG_M_CTRL_ENABLE BIT(0)
149
150 struct irig_slave_reg {
151 u32 ctrl;
152 u32 status;
153 u32 __pad0;
154 u32 version;
155 u32 adj_sec;
156 u32 mode_ctrl;
157 };
158
159 #define IRIG_S_CTRL_ENABLE BIT(0)
160
161 struct dcf_master_reg {
162 u32 ctrl;
163 u32 status;
164 u32 __pad0;
165 u32 version;
166 u32 adj_sec;
167 };
168
169 #define DCF_M_CTRL_ENABLE BIT(0)
170
171 struct dcf_slave_reg {
172 u32 ctrl;
173 u32 status;
174 u32 __pad0;
175 u32 version;
176 u32 adj_sec;
177 };
178
179 #define DCF_S_CTRL_ENABLE BIT(0)
180
181 struct signal_reg {
182 u32 enable;
183 u32 status;
184 u32 polarity;
185 u32 version;
186 u32 __pad0[4];
187 u32 cable_delay;
188 u32 __pad1[3];
189 u32 intr;
190 u32 intr_mask;
191 u32 __pad2[2];
192 u32 start_ns;
193 u32 start_sec;
194 u32 pulse_ns;
195 u32 pulse_sec;
196 u32 period_ns;
197 u32 period_sec;
198 u32 repeat_count;
199 };
200
201 struct frequency_reg {
202 u32 ctrl;
203 u32 status;
204 };
205 #define FREQ_STATUS_VALID BIT(31)
206 #define FREQ_STATUS_ERROR BIT(30)
207 #define FREQ_STATUS_OVERRUN BIT(29)
208 #define FREQ_STATUS_MASK (BIT(24) - 1)
209
210 struct ptp_ocp_flash_info {
211 const char *name;
212 int pci_offset;
213 int data_size;
214 void *data;
215 };
216
217 struct ptp_ocp_firmware_header {
218 char magic[4];
219 __be16 pci_vendor_id;
220 __be16 pci_device_id;
221 __be32 image_size;
222 __be16 hw_revision;
223 __be16 crc;
224 };
225
226 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
227
228 struct ptp_ocp_i2c_info {
229 const char *name;
230 unsigned long fixed_rate;
231 size_t data_size;
232 void *data;
233 };
234
235 struct ptp_ocp_ext_info {
236 int index;
237 irqreturn_t (*irq_fcn)(int irq, void *priv);
238 int (*enable)(void *priv, u32 req, bool enable);
239 };
240
241 struct ptp_ocp_ext_src {
242 void __iomem *mem;
243 struct ptp_ocp *bp;
244 struct ptp_ocp_ext_info *info;
245 int irq_vec;
246 };
247
248 enum ptp_ocp_sma_mode {
249 SMA_MODE_IN,
250 SMA_MODE_OUT,
251 };
252
253 struct ptp_ocp_sma_connector {
254 enum ptp_ocp_sma_mode mode;
255 bool fixed_fcn;
256 bool fixed_dir;
257 bool disabled;
258 u8 default_fcn;
259 };
260
261 struct ocp_attr_group {
262 u64 cap;
263 const struct attribute_group *group;
264 };
265
266 #define OCP_CAP_BASIC BIT(0)
267 #define OCP_CAP_SIGNAL BIT(1)
268 #define OCP_CAP_FREQ BIT(2)
269
270 struct ptp_ocp_signal {
271 ktime_t period;
272 ktime_t pulse;
273 ktime_t phase;
274 ktime_t start;
275 int duty;
276 bool polarity;
277 bool running;
278 };
279
280 #define OCP_BOARD_ID_LEN 13
281 #define OCP_SERIAL_LEN 6
282
283 struct ptp_ocp {
284 struct pci_dev *pdev;
285 struct device dev;
286 spinlock_t lock;
287 struct ocp_reg __iomem *reg;
288 struct tod_reg __iomem *tod;
289 struct pps_reg __iomem *pps_to_ext;
290 struct pps_reg __iomem *pps_to_clk;
291 struct gpio_reg __iomem *pps_select;
292 struct gpio_reg __iomem *sma_map1;
293 struct gpio_reg __iomem *sma_map2;
294 struct irig_master_reg __iomem *irig_out;
295 struct irig_slave_reg __iomem *irig_in;
296 struct dcf_master_reg __iomem *dcf_out;
297 struct dcf_slave_reg __iomem *dcf_in;
298 struct tod_reg __iomem *nmea_out;
299 struct frequency_reg __iomem *freq_in[4];
300 struct ptp_ocp_ext_src *signal_out[4];
301 struct ptp_ocp_ext_src *pps;
302 struct ptp_ocp_ext_src *ts0;
303 struct ptp_ocp_ext_src *ts1;
304 struct ptp_ocp_ext_src *ts2;
305 struct ptp_ocp_ext_src *ts3;
306 struct ptp_ocp_ext_src *ts4;
307 struct img_reg __iomem *image;
308 struct ptp_clock *ptp;
309 struct ptp_clock_info ptp_info;
310 struct platform_device *i2c_ctrl;
311 struct platform_device *spi_flash;
312 struct clk_hw *i2c_clk;
313 struct timer_list watchdog;
314 const struct attribute_group **attr_group;
315 const struct ptp_ocp_eeprom_map *eeprom_map;
316 struct dentry *debug_root;
317 time64_t gnss_lost;
318 int id;
319 int n_irqs;
320 int gnss_port;
321 int gnss2_port;
322 int mac_port; /* miniature atomic clock */
323 int nmea_port;
324 bool fw_loader;
325 u8 fw_tag;
326 u16 fw_version;
327 u8 board_id[OCP_BOARD_ID_LEN];
328 u8 serial[OCP_SERIAL_LEN];
329 bool has_eeprom_data;
330 u32 pps_req_map;
331 int flash_start;
332 u32 utc_tai_offset;
333 u32 ts_window_adjust;
334 u64 fw_cap;
335 struct ptp_ocp_signal signal[4];
336 struct ptp_ocp_sma_connector sma[4];
337 const struct ocp_sma_op *sma_op;
338 };
339
340 #define OCP_REQ_TIMESTAMP BIT(0)
341 #define OCP_REQ_PPS BIT(1)
342
343 struct ocp_resource {
344 unsigned long offset;
345 int size;
346 int irq_vec;
347 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
348 void *extra;
349 unsigned long bp_offset;
350 const char * const name;
351 };
352
353 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
354 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
355 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
356 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
357 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
358 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
359 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
360 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
361 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
362 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
363 struct ptp_perout_request *req);
364 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
365 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
366
367 static const struct ocp_attr_group fb_timecard_groups[];
368
369 struct ptp_ocp_eeprom_map {
370 u16 off;
371 u16 len;
372 u32 bp_offset;
373 const void * const tag;
374 };
375
376 #define EEPROM_ENTRY(addr, member) \
377 .off = addr, \
378 .len = sizeof_field(struct ptp_ocp, member), \
379 .bp_offset = offsetof(struct ptp_ocp, member)
380
381 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
382 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
383 })
384
385 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
386 { EEPROM_ENTRY(0x43, board_id) },
387 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
388 { }
389 };
390
391 #define bp_assign_entry(bp, res, val) ({ \
392 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
393 *(typeof(val) *)addr = val; \
394 })
395
396 #define OCP_RES_LOCATION(member) \
397 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
398
399 #define OCP_MEM_RESOURCE(member) \
400 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
401
402 #define OCP_SERIAL_RESOURCE(member) \
403 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
404
405 #define OCP_I2C_RESOURCE(member) \
406 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
407
408 #define OCP_SPI_RESOURCE(member) \
409 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
410
411 #define OCP_EXT_RESOURCE(member) \
412 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
413
414 /* This is the MSI vector mapping used.
415 * 0: PPS (TS5)
416 * 1: TS0
417 * 2: TS1
418 * 3: GNSS1
419 * 4: GNSS2
420 * 5: MAC
421 * 6: TS2
422 * 7: I2C controller
423 * 8: HWICAP (notused)
424 * 9: SPI Flash
425 * 10: NMEA
426 * 11: Signal Generator 1
427 * 12: Signal Generator 2
428 * 13: Signal Generator 3
429 * 14: Signal Generator 4
430 * 15: TS3
431 * 16: TS4
432 */
433
434 static struct ocp_resource ocp_fb_resource[] = {
435 {
436 OCP_MEM_RESOURCE(reg),
437 .offset = 0x01000000, .size = 0x10000,
438 },
439 {
440 OCP_EXT_RESOURCE(ts0),
441 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
442 .extra = &(struct ptp_ocp_ext_info) {
443 .index = 0,
444 .irq_fcn = ptp_ocp_ts_irq,
445 .enable = ptp_ocp_ts_enable,
446 },
447 },
448 {
449 OCP_EXT_RESOURCE(ts1),
450 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
451 .extra = &(struct ptp_ocp_ext_info) {
452 .index = 1,
453 .irq_fcn = ptp_ocp_ts_irq,
454 .enable = ptp_ocp_ts_enable,
455 },
456 },
457 {
458 OCP_EXT_RESOURCE(ts2),
459 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
460 .extra = &(struct ptp_ocp_ext_info) {
461 .index = 2,
462 .irq_fcn = ptp_ocp_ts_irq,
463 .enable = ptp_ocp_ts_enable,
464 },
465 },
466 {
467 OCP_EXT_RESOURCE(ts3),
468 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
469 .extra = &(struct ptp_ocp_ext_info) {
470 .index = 3,
471 .irq_fcn = ptp_ocp_ts_irq,
472 .enable = ptp_ocp_ts_enable,
473 },
474 },
475 {
476 OCP_EXT_RESOURCE(ts4),
477 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
478 .extra = &(struct ptp_ocp_ext_info) {
479 .index = 4,
480 .irq_fcn = ptp_ocp_ts_irq,
481 .enable = ptp_ocp_ts_enable,
482 },
483 },
484 /* Timestamp for PHC and/or PPS generator */
485 {
486 OCP_EXT_RESOURCE(pps),
487 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
488 .extra = &(struct ptp_ocp_ext_info) {
489 .index = 5,
490 .irq_fcn = ptp_ocp_ts_irq,
491 .enable = ptp_ocp_ts_enable,
492 },
493 },
494 {
495 OCP_EXT_RESOURCE(signal_out[0]),
496 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
497 .extra = &(struct ptp_ocp_ext_info) {
498 .index = 1,
499 .irq_fcn = ptp_ocp_signal_irq,
500 .enable = ptp_ocp_signal_enable,
501 },
502 },
503 {
504 OCP_EXT_RESOURCE(signal_out[1]),
505 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
506 .extra = &(struct ptp_ocp_ext_info) {
507 .index = 2,
508 .irq_fcn = ptp_ocp_signal_irq,
509 .enable = ptp_ocp_signal_enable,
510 },
511 },
512 {
513 OCP_EXT_RESOURCE(signal_out[2]),
514 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
515 .extra = &(struct ptp_ocp_ext_info) {
516 .index = 3,
517 .irq_fcn = ptp_ocp_signal_irq,
518 .enable = ptp_ocp_signal_enable,
519 },
520 },
521 {
522 OCP_EXT_RESOURCE(signal_out[3]),
523 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
524 .extra = &(struct ptp_ocp_ext_info) {
525 .index = 4,
526 .irq_fcn = ptp_ocp_signal_irq,
527 .enable = ptp_ocp_signal_enable,
528 },
529 },
530 {
531 OCP_MEM_RESOURCE(pps_to_ext),
532 .offset = 0x01030000, .size = 0x10000,
533 },
534 {
535 OCP_MEM_RESOURCE(pps_to_clk),
536 .offset = 0x01040000, .size = 0x10000,
537 },
538 {
539 OCP_MEM_RESOURCE(tod),
540 .offset = 0x01050000, .size = 0x10000,
541 },
542 {
543 OCP_MEM_RESOURCE(irig_in),
544 .offset = 0x01070000, .size = 0x10000,
545 },
546 {
547 OCP_MEM_RESOURCE(irig_out),
548 .offset = 0x01080000, .size = 0x10000,
549 },
550 {
551 OCP_MEM_RESOURCE(dcf_in),
552 .offset = 0x01090000, .size = 0x10000,
553 },
554 {
555 OCP_MEM_RESOURCE(dcf_out),
556 .offset = 0x010A0000, .size = 0x10000,
557 },
558 {
559 OCP_MEM_RESOURCE(nmea_out),
560 .offset = 0x010B0000, .size = 0x10000,
561 },
562 {
563 OCP_MEM_RESOURCE(image),
564 .offset = 0x00020000, .size = 0x1000,
565 },
566 {
567 OCP_MEM_RESOURCE(pps_select),
568 .offset = 0x00130000, .size = 0x1000,
569 },
570 {
571 OCP_MEM_RESOURCE(sma_map1),
572 .offset = 0x00140000, .size = 0x1000,
573 },
574 {
575 OCP_MEM_RESOURCE(sma_map2),
576 .offset = 0x00220000, .size = 0x1000,
577 },
578 {
579 OCP_I2C_RESOURCE(i2c_ctrl),
580 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
581 .extra = &(struct ptp_ocp_i2c_info) {
582 .name = "xiic-i2c",
583 .fixed_rate = 50000000,
584 .data_size = sizeof(struct xiic_i2c_platform_data),
585 .data = &(struct xiic_i2c_platform_data) {
586 .num_devices = 2,
587 .devices = (struct i2c_board_info[]) {
588 { I2C_BOARD_INFO("24c02", 0x50) },
589 { I2C_BOARD_INFO("24mac402", 0x58),
590 .platform_data = "mac" },
591 },
592 },
593 },
594 },
595 {
596 OCP_SERIAL_RESOURCE(gnss_port),
597 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
598 },
599 {
600 OCP_SERIAL_RESOURCE(gnss2_port),
601 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
602 },
603 {
604 OCP_SERIAL_RESOURCE(mac_port),
605 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
606 },
607 {
608 OCP_SERIAL_RESOURCE(nmea_port),
609 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
610 },
611 {
612 OCP_SPI_RESOURCE(spi_flash),
613 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
614 .extra = &(struct ptp_ocp_flash_info) {
615 .name = "xilinx_spi", .pci_offset = 0,
616 .data_size = sizeof(struct xspi_platform_data),
617 .data = &(struct xspi_platform_data) {
618 .num_chipselect = 1,
619 .bits_per_word = 8,
620 .num_devices = 1,
621 .devices = &(struct spi_board_info) {
622 .modalias = "spi-nor",
623 },
624 },
625 },
626 },
627 {
628 OCP_MEM_RESOURCE(freq_in[0]),
629 .offset = 0x01200000, .size = 0x10000,
630 },
631 {
632 OCP_MEM_RESOURCE(freq_in[1]),
633 .offset = 0x01210000, .size = 0x10000,
634 },
635 {
636 OCP_MEM_RESOURCE(freq_in[2]),
637 .offset = 0x01220000, .size = 0x10000,
638 },
639 {
640 OCP_MEM_RESOURCE(freq_in[3]),
641 .offset = 0x01230000, .size = 0x10000,
642 },
643 {
644 .setup = ptp_ocp_fb_board_init,
645 },
646 { }
647 };
648
649 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
650 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
651 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
652 { }
653 };
654 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
655
656 static DEFINE_MUTEX(ptp_ocp_lock);
657 static DEFINE_IDR(ptp_ocp_idr);
658
659 struct ocp_selector {
660 const char *name;
661 int value;
662 };
663
664 static const struct ocp_selector ptp_ocp_clock[] = {
665 { .name = "NONE", .value = 0 },
666 { .name = "TOD", .value = 1 },
667 { .name = "IRIG", .value = 2 },
668 { .name = "PPS", .value = 3 },
669 { .name = "PTP", .value = 4 },
670 { .name = "RTC", .value = 5 },
671 { .name = "DCF", .value = 6 },
672 { .name = "REGS", .value = 0xfe },
673 { .name = "EXT", .value = 0xff },
674 { }
675 };
676
677 #define SMA_ENABLE BIT(15)
678 #define SMA_SELECT_MASK ((1U << 15) - 1)
679 #define SMA_DISABLE 0x10000
680
681 static const struct ocp_selector ptp_ocp_sma_in[] = {
682 { .name = "10Mhz", .value = 0x0000 },
683 { .name = "PPS1", .value = 0x0001 },
684 { .name = "PPS2", .value = 0x0002 },
685 { .name = "TS1", .value = 0x0004 },
686 { .name = "TS2", .value = 0x0008 },
687 { .name = "IRIG", .value = 0x0010 },
688 { .name = "DCF", .value = 0x0020 },
689 { .name = "TS3", .value = 0x0040 },
690 { .name = "TS4", .value = 0x0080 },
691 { .name = "FREQ1", .value = 0x0100 },
692 { .name = "FREQ2", .value = 0x0200 },
693 { .name = "FREQ3", .value = 0x0400 },
694 { .name = "FREQ4", .value = 0x0800 },
695 { .name = "None", .value = SMA_DISABLE },
696 { }
697 };
698
699 static const struct ocp_selector ptp_ocp_sma_out[] = {
700 { .name = "10Mhz", .value = 0x0000 },
701 { .name = "PHC", .value = 0x0001 },
702 { .name = "MAC", .value = 0x0002 },
703 { .name = "GNSS1", .value = 0x0004 },
704 { .name = "GNSS2", .value = 0x0008 },
705 { .name = "IRIG", .value = 0x0010 },
706 { .name = "DCF", .value = 0x0020 },
707 { .name = "GEN1", .value = 0x0040 },
708 { .name = "GEN2", .value = 0x0080 },
709 { .name = "GEN3", .value = 0x0100 },
710 { .name = "GEN4", .value = 0x0200 },
711 { .name = "GND", .value = 0x2000 },
712 { .name = "VCC", .value = 0x4000 },
713 { }
714 };
715
716 struct ocp_sma_op {
717 const struct ocp_selector *tbl[2];
718 void (*init)(struct ptp_ocp *bp);
719 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
720 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
721 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
722 };
723
724 static void
ptp_ocp_sma_init(struct ptp_ocp * bp)725 ptp_ocp_sma_init(struct ptp_ocp *bp)
726 {
727 return bp->sma_op->init(bp);
728 }
729
730 static u32
ptp_ocp_sma_get(struct ptp_ocp * bp,int sma_nr)731 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
732 {
733 return bp->sma_op->get(bp, sma_nr);
734 }
735
736 static int
ptp_ocp_sma_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)737 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
738 {
739 return bp->sma_op->set_inputs(bp, sma_nr, val);
740 }
741
742 static int
ptp_ocp_sma_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)743 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
744 {
745 return bp->sma_op->set_output(bp, sma_nr, val);
746 }
747
748 static const char *
ptp_ocp_select_name_from_val(const struct ocp_selector * tbl,int val)749 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
750 {
751 int i;
752
753 for (i = 0; tbl[i].name; i++)
754 if (tbl[i].value == val)
755 return tbl[i].name;
756 return NULL;
757 }
758
759 static int
ptp_ocp_select_val_from_name(const struct ocp_selector * tbl,const char * name)760 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
761 {
762 const char *select;
763 int i;
764
765 for (i = 0; tbl[i].name; i++) {
766 select = tbl[i].name;
767 if (!strncasecmp(name, select, strlen(select)))
768 return tbl[i].value;
769 }
770 return -EINVAL;
771 }
772
773 static ssize_t
ptp_ocp_select_table_show(const struct ocp_selector * tbl,char * buf)774 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
775 {
776 ssize_t count;
777 int i;
778
779 count = 0;
780 for (i = 0; tbl[i].name; i++)
781 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
782 if (count)
783 count--;
784 count += sysfs_emit_at(buf, count, "\n");
785 return count;
786 }
787
788 static int
__ptp_ocp_gettime_locked(struct ptp_ocp * bp,struct timespec64 * ts,struct ptp_system_timestamp * sts)789 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
790 struct ptp_system_timestamp *sts)
791 {
792 u32 ctrl, time_sec, time_ns;
793 int i;
794
795 ptp_read_system_prets(sts);
796
797 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
798 iowrite32(ctrl, &bp->reg->ctrl);
799
800 for (i = 0; i < 100; i++) {
801 ctrl = ioread32(&bp->reg->ctrl);
802 if (ctrl & OCP_CTRL_READ_TIME_DONE)
803 break;
804 }
805 ptp_read_system_postts(sts);
806
807 if (sts && bp->ts_window_adjust) {
808 s64 ns = timespec64_to_ns(&sts->post_ts);
809
810 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
811 }
812
813 time_ns = ioread32(&bp->reg->time_ns);
814 time_sec = ioread32(&bp->reg->time_sec);
815
816 ts->tv_sec = time_sec;
817 ts->tv_nsec = time_ns;
818
819 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
820 }
821
822 static int
ptp_ocp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)823 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
824 struct ptp_system_timestamp *sts)
825 {
826 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
827 unsigned long flags;
828 int err;
829
830 spin_lock_irqsave(&bp->lock, flags);
831 err = __ptp_ocp_gettime_locked(bp, ts, sts);
832 spin_unlock_irqrestore(&bp->lock, flags);
833
834 return err;
835 }
836
837 static void
__ptp_ocp_settime_locked(struct ptp_ocp * bp,const struct timespec64 * ts)838 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
839 {
840 u32 ctrl, time_sec, time_ns;
841 u32 select;
842
843 time_ns = ts->tv_nsec;
844 time_sec = ts->tv_sec;
845
846 select = ioread32(&bp->reg->select);
847 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
848
849 iowrite32(time_ns, &bp->reg->adjust_ns);
850 iowrite32(time_sec, &bp->reg->adjust_sec);
851
852 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
853 iowrite32(ctrl, &bp->reg->ctrl);
854
855 /* restore clock selection */
856 iowrite32(select >> 16, &bp->reg->select);
857 }
858
859 static int
ptp_ocp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)860 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
861 {
862 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
863 unsigned long flags;
864
865 spin_lock_irqsave(&bp->lock, flags);
866 __ptp_ocp_settime_locked(bp, ts);
867 spin_unlock_irqrestore(&bp->lock, flags);
868
869 return 0;
870 }
871
872 static void
__ptp_ocp_adjtime_locked(struct ptp_ocp * bp,u32 adj_val)873 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
874 {
875 u32 select, ctrl;
876
877 select = ioread32(&bp->reg->select);
878 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
879
880 iowrite32(adj_val, &bp->reg->offset_ns);
881 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
882
883 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
884 iowrite32(ctrl, &bp->reg->ctrl);
885
886 /* restore clock selection */
887 iowrite32(select >> 16, &bp->reg->select);
888 }
889
890 static void
ptp_ocp_adjtime_coarse(struct ptp_ocp * bp,s64 delta_ns)891 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
892 {
893 struct timespec64 ts;
894 unsigned long flags;
895 int err;
896
897 spin_lock_irqsave(&bp->lock, flags);
898 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
899 if (likely(!err)) {
900 set_normalized_timespec64(&ts, ts.tv_sec,
901 ts.tv_nsec + delta_ns);
902 __ptp_ocp_settime_locked(bp, &ts);
903 }
904 spin_unlock_irqrestore(&bp->lock, flags);
905 }
906
907 static int
ptp_ocp_adjtime(struct ptp_clock_info * ptp_info,s64 delta_ns)908 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
909 {
910 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
911 unsigned long flags;
912 u32 adj_ns, sign;
913
914 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
915 ptp_ocp_adjtime_coarse(bp, delta_ns);
916 return 0;
917 }
918
919 sign = delta_ns < 0 ? BIT(31) : 0;
920 adj_ns = sign ? -delta_ns : delta_ns;
921
922 spin_lock_irqsave(&bp->lock, flags);
923 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
924 spin_unlock_irqrestore(&bp->lock, flags);
925
926 return 0;
927 }
928
929 static int
ptp_ocp_null_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)930 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
931 {
932 if (scaled_ppm == 0)
933 return 0;
934
935 return -EOPNOTSUPP;
936 }
937
938 static int
ptp_ocp_null_adjphase(struct ptp_clock_info * ptp_info,s32 phase_ns)939 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
940 {
941 return -EOPNOTSUPP;
942 }
943
944 static int
ptp_ocp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)945 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
946 int on)
947 {
948 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
949 struct ptp_ocp_ext_src *ext = NULL;
950 u32 req;
951 int err;
952
953 switch (rq->type) {
954 case PTP_CLK_REQ_EXTTS:
955 req = OCP_REQ_TIMESTAMP;
956 switch (rq->extts.index) {
957 case 0:
958 ext = bp->ts0;
959 break;
960 case 1:
961 ext = bp->ts1;
962 break;
963 case 2:
964 ext = bp->ts2;
965 break;
966 case 3:
967 ext = bp->ts3;
968 break;
969 case 4:
970 ext = bp->ts4;
971 break;
972 case 5:
973 ext = bp->pps;
974 break;
975 }
976 break;
977 case PTP_CLK_REQ_PPS:
978 req = OCP_REQ_PPS;
979 ext = bp->pps;
980 break;
981 case PTP_CLK_REQ_PEROUT:
982 switch (rq->perout.index) {
983 case 0:
984 /* This is a request for 1PPS on an output SMA.
985 * Allow, but assume manual configuration.
986 */
987 if (on && (rq->perout.period.sec != 1 ||
988 rq->perout.period.nsec != 0))
989 return -EINVAL;
990 return 0;
991 case 1:
992 case 2:
993 case 3:
994 case 4:
995 req = rq->perout.index - 1;
996 ext = bp->signal_out[req];
997 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
998 if (err)
999 return err;
1000 break;
1001 }
1002 break;
1003 default:
1004 return -EOPNOTSUPP;
1005 }
1006
1007 err = -ENXIO;
1008 if (ext)
1009 err = ext->info->enable(ext, req, on);
1010
1011 return err;
1012 }
1013
1014 static int
ptp_ocp_verify(struct ptp_clock_info * ptp_info,unsigned pin,enum ptp_pin_function func,unsigned chan)1015 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1016 enum ptp_pin_function func, unsigned chan)
1017 {
1018 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1019 char buf[16];
1020
1021 switch (func) {
1022 case PTP_PF_NONE:
1023 snprintf(buf, sizeof(buf), "IN: None");
1024 break;
1025 case PTP_PF_EXTTS:
1026 /* Allow timestamps, but require sysfs configuration. */
1027 return 0;
1028 case PTP_PF_PEROUT:
1029 /* channel 0 is 1PPS from PHC.
1030 * channels 1..4 are the frequency generators.
1031 */
1032 if (chan)
1033 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1034 else
1035 snprintf(buf, sizeof(buf), "OUT: PHC");
1036 break;
1037 default:
1038 return -EOPNOTSUPP;
1039 }
1040
1041 return ptp_ocp_sma_store(bp, buf, pin + 1);
1042 }
1043
1044 static const struct ptp_clock_info ptp_ocp_clock_info = {
1045 .owner = THIS_MODULE,
1046 .name = KBUILD_MODNAME,
1047 .max_adj = 100000000,
1048 .gettimex64 = ptp_ocp_gettimex,
1049 .settime64 = ptp_ocp_settime,
1050 .adjtime = ptp_ocp_adjtime,
1051 .adjfine = ptp_ocp_null_adjfine,
1052 .adjphase = ptp_ocp_null_adjphase,
1053 .enable = ptp_ocp_enable,
1054 .verify = ptp_ocp_verify,
1055 .pps = true,
1056 .n_ext_ts = 6,
1057 .n_per_out = 5,
1058 };
1059
1060 static void
__ptp_ocp_clear_drift_locked(struct ptp_ocp * bp)1061 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1062 {
1063 u32 ctrl, select;
1064
1065 select = ioread32(&bp->reg->select);
1066 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1067
1068 iowrite32(0, &bp->reg->drift_ns);
1069
1070 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1071 iowrite32(ctrl, &bp->reg->ctrl);
1072
1073 /* restore clock selection */
1074 iowrite32(select >> 16, &bp->reg->select);
1075 }
1076
1077 static void
ptp_ocp_utc_distribute(struct ptp_ocp * bp,u32 val)1078 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1079 {
1080 unsigned long flags;
1081
1082 spin_lock_irqsave(&bp->lock, flags);
1083
1084 bp->utc_tai_offset = val;
1085
1086 if (bp->irig_out)
1087 iowrite32(val, &bp->irig_out->adj_sec);
1088 if (bp->dcf_out)
1089 iowrite32(val, &bp->dcf_out->adj_sec);
1090 if (bp->nmea_out)
1091 iowrite32(val, &bp->nmea_out->adj_sec);
1092
1093 spin_unlock_irqrestore(&bp->lock, flags);
1094 }
1095
1096 static void
ptp_ocp_watchdog(struct timer_list * t)1097 ptp_ocp_watchdog(struct timer_list *t)
1098 {
1099 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1100 unsigned long flags;
1101 u32 status, utc_offset;
1102
1103 status = ioread32(&bp->pps_to_clk->status);
1104
1105 if (status & PPS_STATUS_SUPERV_ERR) {
1106 iowrite32(status, &bp->pps_to_clk->status);
1107 if (!bp->gnss_lost) {
1108 spin_lock_irqsave(&bp->lock, flags);
1109 __ptp_ocp_clear_drift_locked(bp);
1110 spin_unlock_irqrestore(&bp->lock, flags);
1111 bp->gnss_lost = ktime_get_real_seconds();
1112 }
1113
1114 } else if (bp->gnss_lost) {
1115 bp->gnss_lost = 0;
1116 }
1117
1118 /* if GNSS provides correct data we can rely on
1119 * it to get leap second information
1120 */
1121 if (bp->tod) {
1122 status = ioread32(&bp->tod->utc_status);
1123 utc_offset = status & TOD_STATUS_UTC_MASK;
1124 if (status & TOD_STATUS_UTC_VALID &&
1125 utc_offset != bp->utc_tai_offset)
1126 ptp_ocp_utc_distribute(bp, utc_offset);
1127 }
1128
1129 mod_timer(&bp->watchdog, jiffies + HZ);
1130 }
1131
1132 static void
ptp_ocp_estimate_pci_timing(struct ptp_ocp * bp)1133 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1134 {
1135 ktime_t start, end;
1136 ktime_t delay;
1137 u32 ctrl;
1138
1139 ctrl = ioread32(&bp->reg->ctrl);
1140 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1141
1142 iowrite32(ctrl, &bp->reg->ctrl);
1143
1144 start = ktime_get_ns();
1145
1146 ctrl = ioread32(&bp->reg->ctrl);
1147
1148 end = ktime_get_ns();
1149
1150 delay = end - start;
1151 bp->ts_window_adjust = (delay >> 5) * 3;
1152 }
1153
1154 static int
ptp_ocp_init_clock(struct ptp_ocp * bp)1155 ptp_ocp_init_clock(struct ptp_ocp *bp)
1156 {
1157 struct timespec64 ts;
1158 bool sync;
1159 u32 ctrl;
1160
1161 ctrl = OCP_CTRL_ENABLE;
1162 iowrite32(ctrl, &bp->reg->ctrl);
1163
1164 /* NO DRIFT Correction */
1165 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */
1166 iowrite32(0x2000, &bp->reg->servo_offset_p);
1167 iowrite32(0x1000, &bp->reg->servo_offset_i);
1168 iowrite32(0, &bp->reg->servo_drift_p);
1169 iowrite32(0, &bp->reg->servo_drift_i);
1170
1171 /* latch servo values */
1172 ctrl |= OCP_CTRL_ADJUST_SERVO;
1173 iowrite32(ctrl, &bp->reg->ctrl);
1174
1175 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1176 dev_err(&bp->pdev->dev, "clock not enabled\n");
1177 return -ENODEV;
1178 }
1179
1180 ptp_ocp_estimate_pci_timing(bp);
1181
1182 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1183 if (!sync) {
1184 ktime_get_clocktai_ts64(&ts);
1185 ptp_ocp_settime(&bp->ptp_info, &ts);
1186 }
1187
1188 /* If there is a clock supervisor, then enable the watchdog */
1189 if (bp->pps_to_clk) {
1190 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1191 mod_timer(&bp->watchdog, jiffies + HZ);
1192 }
1193
1194 return 0;
1195 }
1196
1197 static void
ptp_ocp_tod_init(struct ptp_ocp * bp)1198 ptp_ocp_tod_init(struct ptp_ocp *bp)
1199 {
1200 u32 ctrl, reg;
1201
1202 ctrl = ioread32(&bp->tod->ctrl);
1203 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1204 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1205 iowrite32(ctrl, &bp->tod->ctrl);
1206
1207 reg = ioread32(&bp->tod->utc_status);
1208 if (reg & TOD_STATUS_UTC_VALID)
1209 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1210 }
1211
1212 static const char *
ptp_ocp_tod_proto_name(const int idx)1213 ptp_ocp_tod_proto_name(const int idx)
1214 {
1215 static const char * const proto_name[] = {
1216 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1217 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1218 };
1219 return proto_name[idx];
1220 }
1221
1222 static const char *
ptp_ocp_tod_gnss_name(int idx)1223 ptp_ocp_tod_gnss_name(int idx)
1224 {
1225 static const char * const gnss_name[] = {
1226 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1227 "Unknown"
1228 };
1229 if (idx >= ARRAY_SIZE(gnss_name))
1230 idx = ARRAY_SIZE(gnss_name) - 1;
1231 return gnss_name[idx];
1232 }
1233
1234 struct ptp_ocp_nvmem_match_info {
1235 struct ptp_ocp *bp;
1236 const void * const tag;
1237 };
1238
1239 static int
ptp_ocp_nvmem_match(struct device * dev,const void * data)1240 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1241 {
1242 const struct ptp_ocp_nvmem_match_info *info = data;
1243
1244 dev = dev->parent;
1245 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1246 return 0;
1247
1248 while ((dev = dev->parent))
1249 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1250 return info->bp == dev_get_drvdata(dev);
1251 return 0;
1252 }
1253
1254 static inline struct nvmem_device *
ptp_ocp_nvmem_device_get(struct ptp_ocp * bp,const void * const tag)1255 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1256 {
1257 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1258
1259 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1260 }
1261
1262 static inline void
ptp_ocp_nvmem_device_put(struct nvmem_device ** nvmemp)1263 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1264 {
1265 if (!IS_ERR_OR_NULL(*nvmemp))
1266 nvmem_device_put(*nvmemp);
1267 *nvmemp = NULL;
1268 }
1269
1270 static void
ptp_ocp_read_eeprom(struct ptp_ocp * bp)1271 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1272 {
1273 const struct ptp_ocp_eeprom_map *map;
1274 struct nvmem_device *nvmem;
1275 const void *tag;
1276 int ret;
1277
1278 if (!bp->i2c_ctrl)
1279 return;
1280
1281 tag = NULL;
1282 nvmem = NULL;
1283
1284 for (map = bp->eeprom_map; map->len; map++) {
1285 if (map->tag != tag) {
1286 tag = map->tag;
1287 ptp_ocp_nvmem_device_put(&nvmem);
1288 }
1289 if (!nvmem) {
1290 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1291 if (IS_ERR(nvmem)) {
1292 ret = PTR_ERR(nvmem);
1293 goto fail;
1294 }
1295 }
1296 ret = nvmem_device_read(nvmem, map->off, map->len,
1297 BP_MAP_ENTRY_ADDR(bp, map));
1298 if (ret != map->len)
1299 goto fail;
1300 }
1301
1302 bp->has_eeprom_data = true;
1303
1304 out:
1305 ptp_ocp_nvmem_device_put(&nvmem);
1306 return;
1307
1308 fail:
1309 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1310 goto out;
1311 }
1312
1313 static int
ptp_ocp_firstchild(struct device * dev,void * data)1314 ptp_ocp_firstchild(struct device *dev, void *data)
1315 {
1316 return 1;
1317 }
1318
1319 static struct device *
ptp_ocp_find_flash(struct ptp_ocp * bp)1320 ptp_ocp_find_flash(struct ptp_ocp *bp)
1321 {
1322 struct device *dev, *last;
1323
1324 last = NULL;
1325 dev = &bp->spi_flash->dev;
1326
1327 while ((dev = device_find_child(dev, NULL, ptp_ocp_firstchild))) {
1328 if (!strcmp("mtd", dev_bus_name(dev)))
1329 break;
1330 put_device(last);
1331 last = dev;
1332 }
1333 put_device(last);
1334
1335 return dev;
1336 }
1337
1338 static int
ptp_ocp_devlink_fw_image(struct devlink * devlink,const struct firmware * fw,const u8 ** data,size_t * size)1339 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1340 const u8 **data, size_t *size)
1341 {
1342 struct ptp_ocp *bp = devlink_priv(devlink);
1343 const struct ptp_ocp_firmware_header *hdr;
1344 size_t offset, length;
1345 u16 crc;
1346
1347 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1348 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1349 devlink_flash_update_status_notify(devlink,
1350 "No firmware header found, flashing raw image",
1351 NULL, 0, 0);
1352 offset = 0;
1353 length = fw->size;
1354 goto out;
1355 }
1356
1357 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1358 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1359 devlink_flash_update_status_notify(devlink,
1360 "Firmware image compatibility check failed",
1361 NULL, 0, 0);
1362 return -EINVAL;
1363 }
1364
1365 offset = sizeof(*hdr);
1366 length = be32_to_cpu(hdr->image_size);
1367 if (length != (fw->size - offset)) {
1368 devlink_flash_update_status_notify(devlink,
1369 "Firmware image size check failed",
1370 NULL, 0, 0);
1371 return -EINVAL;
1372 }
1373
1374 crc = crc16(0xffff, &fw->data[offset], length);
1375 if (be16_to_cpu(hdr->crc) != crc) {
1376 devlink_flash_update_status_notify(devlink,
1377 "Firmware image CRC check failed",
1378 NULL, 0, 0);
1379 return -EINVAL;
1380 }
1381
1382 out:
1383 *data = &fw->data[offset];
1384 *size = length;
1385
1386 return 0;
1387 }
1388
1389 static int
ptp_ocp_devlink_flash(struct devlink * devlink,struct device * dev,const struct firmware * fw)1390 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1391 const struct firmware *fw)
1392 {
1393 struct mtd_info *mtd = dev_get_drvdata(dev);
1394 struct ptp_ocp *bp = devlink_priv(devlink);
1395 size_t off, len, size, resid, wrote;
1396 struct erase_info erase;
1397 size_t base, blksz;
1398 const u8 *data;
1399 int err;
1400
1401 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1402 if (err)
1403 goto out;
1404
1405 off = 0;
1406 base = bp->flash_start;
1407 blksz = 4096;
1408 resid = size;
1409
1410 while (resid) {
1411 devlink_flash_update_status_notify(devlink, "Flashing",
1412 NULL, off, size);
1413
1414 len = min_t(size_t, resid, blksz);
1415 erase.addr = base + off;
1416 erase.len = blksz;
1417
1418 err = mtd_erase(mtd, &erase);
1419 if (err)
1420 goto out;
1421
1422 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1423 if (err)
1424 goto out;
1425
1426 off += blksz;
1427 resid -= len;
1428 }
1429 out:
1430 return err;
1431 }
1432
1433 static int
ptp_ocp_devlink_flash_update(struct devlink * devlink,struct devlink_flash_update_params * params,struct netlink_ext_ack * extack)1434 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1435 struct devlink_flash_update_params *params,
1436 struct netlink_ext_ack *extack)
1437 {
1438 struct ptp_ocp *bp = devlink_priv(devlink);
1439 struct device *dev;
1440 const char *msg;
1441 int err;
1442
1443 dev = ptp_ocp_find_flash(bp);
1444 if (!dev) {
1445 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1446 return -ENODEV;
1447 }
1448
1449 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1450 NULL, 0, 0);
1451
1452 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1453
1454 msg = err ? "Flash error" : "Flash complete";
1455 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1456
1457 put_device(dev);
1458 return err;
1459 }
1460
1461 static int
ptp_ocp_devlink_info_get(struct devlink * devlink,struct devlink_info_req * req,struct netlink_ext_ack * extack)1462 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1463 struct netlink_ext_ack *extack)
1464 {
1465 struct ptp_ocp *bp = devlink_priv(devlink);
1466 const char *fw_image;
1467 char buf[32];
1468 int err;
1469
1470 err = devlink_info_driver_name_put(req, KBUILD_MODNAME);
1471 if (err)
1472 return err;
1473
1474 fw_image = bp->fw_loader ? "loader" : "fw";
1475 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1476 err = devlink_info_version_running_put(req, fw_image, buf);
1477 if (err)
1478 return err;
1479
1480 if (!bp->has_eeprom_data) {
1481 ptp_ocp_read_eeprom(bp);
1482 if (!bp->has_eeprom_data)
1483 return 0;
1484 }
1485
1486 sprintf(buf, "%pM", bp->serial);
1487 err = devlink_info_serial_number_put(req, buf);
1488 if (err)
1489 return err;
1490
1491 err = devlink_info_version_fixed_put(req,
1492 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1493 bp->board_id);
1494 if (err)
1495 return err;
1496
1497 return 0;
1498 }
1499
1500 static const struct devlink_ops ptp_ocp_devlink_ops = {
1501 .flash_update = ptp_ocp_devlink_flash_update,
1502 .info_get = ptp_ocp_devlink_info_get,
1503 };
1504
1505 static void __iomem *
__ptp_ocp_get_mem(struct ptp_ocp * bp,resource_size_t start,int size)1506 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1507 {
1508 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1509
1510 return devm_ioremap_resource(&bp->pdev->dev, &res);
1511 }
1512
1513 static void __iomem *
ptp_ocp_get_mem(struct ptp_ocp * bp,struct ocp_resource * r)1514 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1515 {
1516 resource_size_t start;
1517
1518 start = pci_resource_start(bp->pdev, 0) + r->offset;
1519 return __ptp_ocp_get_mem(bp, start, r->size);
1520 }
1521
1522 static void
ptp_ocp_set_irq_resource(struct resource * res,int irq)1523 ptp_ocp_set_irq_resource(struct resource *res, int irq)
1524 {
1525 struct resource r = DEFINE_RES_IRQ(irq);
1526 *res = r;
1527 }
1528
1529 static void
ptp_ocp_set_mem_resource(struct resource * res,resource_size_t start,int size)1530 ptp_ocp_set_mem_resource(struct resource *res, resource_size_t start, int size)
1531 {
1532 struct resource r = DEFINE_RES_MEM(start, size);
1533 *res = r;
1534 }
1535
1536 static int
ptp_ocp_register_spi(struct ptp_ocp * bp,struct ocp_resource * r)1537 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1538 {
1539 struct ptp_ocp_flash_info *info;
1540 struct pci_dev *pdev = bp->pdev;
1541 struct platform_device *p;
1542 struct resource res[2];
1543 resource_size_t start;
1544 int id;
1545
1546 start = pci_resource_start(pdev, 0) + r->offset;
1547 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1548 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1549
1550 info = r->extra;
1551 id = pci_dev_id(pdev) << 1;
1552 id += info->pci_offset;
1553
1554 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1555 res, 2, info->data,
1556 info->data_size);
1557 if (IS_ERR(p))
1558 return PTR_ERR(p);
1559
1560 bp_assign_entry(bp, r, p);
1561
1562 return 0;
1563 }
1564
1565 static struct platform_device *
ptp_ocp_i2c_bus(struct pci_dev * pdev,struct ocp_resource * r,int id)1566 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1567 {
1568 struct ptp_ocp_i2c_info *info;
1569 struct resource res[2];
1570 resource_size_t start;
1571
1572 info = r->extra;
1573 start = pci_resource_start(pdev, 0) + r->offset;
1574 ptp_ocp_set_mem_resource(&res[0], start, r->size);
1575 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec));
1576
1577 return platform_device_register_resndata(&pdev->dev, info->name,
1578 id, res, 2,
1579 info->data, info->data_size);
1580 }
1581
1582 static int
ptp_ocp_register_i2c(struct ptp_ocp * bp,struct ocp_resource * r)1583 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1584 {
1585 struct pci_dev *pdev = bp->pdev;
1586 struct ptp_ocp_i2c_info *info;
1587 struct platform_device *p;
1588 struct clk_hw *clk;
1589 char buf[32];
1590 int id;
1591
1592 info = r->extra;
1593 id = pci_dev_id(bp->pdev);
1594
1595 sprintf(buf, "AXI.%d", id);
1596 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1597 info->fixed_rate);
1598 if (IS_ERR(clk))
1599 return PTR_ERR(clk);
1600 bp->i2c_clk = clk;
1601
1602 sprintf(buf, "%s.%d", info->name, id);
1603 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1604 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1605 if (IS_ERR(p))
1606 return PTR_ERR(p);
1607
1608 bp_assign_entry(bp, r, p);
1609
1610 return 0;
1611 }
1612
1613 /* The expectation is that this is triggered only on error. */
1614 static irqreturn_t
ptp_ocp_signal_irq(int irq,void * priv)1615 ptp_ocp_signal_irq(int irq, void *priv)
1616 {
1617 struct ptp_ocp_ext_src *ext = priv;
1618 struct signal_reg __iomem *reg = ext->mem;
1619 struct ptp_ocp *bp = ext->bp;
1620 u32 enable, status;
1621 int gen;
1622
1623 gen = ext->info->index - 1;
1624
1625 enable = ioread32(®->enable);
1626 status = ioread32(®->status);
1627
1628 /* disable generator on error */
1629 if (status || !enable) {
1630 iowrite32(0, ®->intr_mask);
1631 iowrite32(0, ®->enable);
1632 bp->signal[gen].running = false;
1633 }
1634
1635 iowrite32(0, ®->intr); /* ack interrupt */
1636
1637 return IRQ_HANDLED;
1638 }
1639
1640 static int
ptp_ocp_signal_set(struct ptp_ocp * bp,int gen,struct ptp_ocp_signal * s)1641 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
1642 {
1643 struct ptp_system_timestamp sts;
1644 struct timespec64 ts;
1645 ktime_t start_ns;
1646 int err;
1647
1648 if (!s->period)
1649 return 0;
1650
1651 if (!s->pulse)
1652 s->pulse = ktime_divns(s->period * s->duty, 100);
1653
1654 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
1655 if (err)
1656 return err;
1657
1658 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
1659 if (!s->start) {
1660 /* roundup() does not work on 32-bit systems */
1661 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
1662 s->start = ktime_add(s->start, s->phase);
1663 }
1664
1665 if (s->duty < 1 || s->duty > 99)
1666 return -EINVAL;
1667
1668 if (s->pulse < 1 || s->pulse > s->period)
1669 return -EINVAL;
1670
1671 if (s->start < start_ns)
1672 return -EINVAL;
1673
1674 bp->signal[gen] = *s;
1675
1676 return 0;
1677 }
1678
1679 static int
ptp_ocp_signal_from_perout(struct ptp_ocp * bp,int gen,struct ptp_perout_request * req)1680 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
1681 struct ptp_perout_request *req)
1682 {
1683 struct ptp_ocp_signal s = { };
1684
1685 s.polarity = bp->signal[gen].polarity;
1686 s.period = ktime_set(req->period.sec, req->period.nsec);
1687 if (!s.period)
1688 return 0;
1689
1690 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
1691 s.pulse = ktime_set(req->on.sec, req->on.nsec);
1692 s.duty = ktime_divns(s.pulse * 100, s.period);
1693 }
1694
1695 if (req->flags & PTP_PEROUT_PHASE)
1696 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
1697 else
1698 s.start = ktime_set(req->start.sec, req->start.nsec);
1699
1700 return ptp_ocp_signal_set(bp, gen, &s);
1701 }
1702
1703 static int
ptp_ocp_signal_enable(void * priv,u32 req,bool enable)1704 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
1705 {
1706 struct ptp_ocp_ext_src *ext = priv;
1707 struct signal_reg __iomem *reg = ext->mem;
1708 struct ptp_ocp *bp = ext->bp;
1709 struct timespec64 ts;
1710 int gen;
1711
1712 gen = ext->info->index - 1;
1713
1714 iowrite32(0, ®->intr_mask);
1715 iowrite32(0, ®->enable);
1716 bp->signal[gen].running = false;
1717 if (!enable)
1718 return 0;
1719
1720 ts = ktime_to_timespec64(bp->signal[gen].start);
1721 iowrite32(ts.tv_sec, ®->start_sec);
1722 iowrite32(ts.tv_nsec, ®->start_ns);
1723
1724 ts = ktime_to_timespec64(bp->signal[gen].period);
1725 iowrite32(ts.tv_sec, ®->period_sec);
1726 iowrite32(ts.tv_nsec, ®->period_ns);
1727
1728 ts = ktime_to_timespec64(bp->signal[gen].pulse);
1729 iowrite32(ts.tv_sec, ®->pulse_sec);
1730 iowrite32(ts.tv_nsec, ®->pulse_ns);
1731
1732 iowrite32(bp->signal[gen].polarity, ®->polarity);
1733 iowrite32(0, ®->repeat_count);
1734
1735 iowrite32(0, ®->intr); /* clear interrupt state */
1736 iowrite32(1, ®->intr_mask); /* enable interrupt */
1737 iowrite32(3, ®->enable); /* valid & enable */
1738
1739 bp->signal[gen].running = true;
1740
1741 return 0;
1742 }
1743
1744 static irqreturn_t
ptp_ocp_ts_irq(int irq,void * priv)1745 ptp_ocp_ts_irq(int irq, void *priv)
1746 {
1747 struct ptp_ocp_ext_src *ext = priv;
1748 struct ts_reg __iomem *reg = ext->mem;
1749 struct ptp_clock_event ev;
1750 u32 sec, nsec;
1751
1752 if (ext == ext->bp->pps) {
1753 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
1754 ev.type = PTP_CLOCK_PPS;
1755 ptp_clock_event(ext->bp->ptp, &ev);
1756 }
1757
1758 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
1759 goto out;
1760 }
1761
1762 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
1763 sec = ioread32(®->time_sec);
1764 nsec = ioread32(®->time_ns);
1765
1766 ev.type = PTP_CLOCK_EXTTS;
1767 ev.index = ext->info->index;
1768 ev.timestamp = sec * NSEC_PER_SEC + nsec;
1769
1770 ptp_clock_event(ext->bp->ptp, &ev);
1771
1772 out:
1773 iowrite32(1, ®->intr); /* write 1 to ack */
1774
1775 return IRQ_HANDLED;
1776 }
1777
1778 static int
ptp_ocp_ts_enable(void * priv,u32 req,bool enable)1779 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
1780 {
1781 struct ptp_ocp_ext_src *ext = priv;
1782 struct ts_reg __iomem *reg = ext->mem;
1783 struct ptp_ocp *bp = ext->bp;
1784
1785 if (ext == bp->pps) {
1786 u32 old_map = bp->pps_req_map;
1787
1788 if (enable)
1789 bp->pps_req_map |= req;
1790 else
1791 bp->pps_req_map &= ~req;
1792
1793 /* if no state change, just return */
1794 if ((!!old_map ^ !!bp->pps_req_map) == 0)
1795 return 0;
1796 }
1797
1798 if (enable) {
1799 iowrite32(1, ®->enable);
1800 iowrite32(1, ®->intr_mask);
1801 iowrite32(1, ®->intr);
1802 } else {
1803 iowrite32(0, ®->intr_mask);
1804 iowrite32(0, ®->enable);
1805 }
1806
1807 return 0;
1808 }
1809
1810 static void
ptp_ocp_unregister_ext(struct ptp_ocp_ext_src * ext)1811 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
1812 {
1813 ext->info->enable(ext, ~0, false);
1814 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
1815 kfree(ext);
1816 }
1817
1818 static int
ptp_ocp_register_ext(struct ptp_ocp * bp,struct ocp_resource * r)1819 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
1820 {
1821 struct pci_dev *pdev = bp->pdev;
1822 struct ptp_ocp_ext_src *ext;
1823 int err;
1824
1825 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
1826 if (!ext)
1827 return -ENOMEM;
1828
1829 ext->mem = ptp_ocp_get_mem(bp, r);
1830 if (IS_ERR(ext->mem)) {
1831 err = PTR_ERR(ext->mem);
1832 goto out;
1833 }
1834
1835 ext->bp = bp;
1836 ext->info = r->extra;
1837 ext->irq_vec = r->irq_vec;
1838
1839 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
1840 ext, "ocp%d.%s", bp->id, r->name);
1841 if (err) {
1842 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
1843 goto out;
1844 }
1845
1846 bp_assign_entry(bp, r, ext);
1847
1848 return 0;
1849
1850 out:
1851 kfree(ext);
1852 return err;
1853 }
1854
1855 static int
ptp_ocp_serial_line(struct ptp_ocp * bp,struct ocp_resource * r)1856 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
1857 {
1858 struct pci_dev *pdev = bp->pdev;
1859 struct uart_8250_port uart;
1860
1861 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
1862 * the serial port device claim and release the pci resource.
1863 */
1864 memset(&uart, 0, sizeof(uart));
1865 uart.port.dev = &pdev->dev;
1866 uart.port.iotype = UPIO_MEM;
1867 uart.port.regshift = 2;
1868 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
1869 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
1870 uart.port.uartclk = 50000000;
1871 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
1872 uart.port.type = PORT_16550A;
1873
1874 return serial8250_register_8250_port(&uart);
1875 }
1876
1877 static int
ptp_ocp_register_serial(struct ptp_ocp * bp,struct ocp_resource * r)1878 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
1879 {
1880 int port;
1881
1882 port = ptp_ocp_serial_line(bp, r);
1883 if (port < 0)
1884 return port;
1885
1886 bp_assign_entry(bp, r, port);
1887
1888 return 0;
1889 }
1890
1891 static int
ptp_ocp_register_mem(struct ptp_ocp * bp,struct ocp_resource * r)1892 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1893 {
1894 void __iomem *mem;
1895
1896 mem = ptp_ocp_get_mem(bp, r);
1897 if (IS_ERR(mem))
1898 return PTR_ERR(mem);
1899
1900 bp_assign_entry(bp, r, mem);
1901
1902 return 0;
1903 }
1904
1905 static void
ptp_ocp_nmea_out_init(struct ptp_ocp * bp)1906 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
1907 {
1908 if (!bp->nmea_out)
1909 return;
1910
1911 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
1912 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
1913 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
1914 }
1915
1916 static void
_ptp_ocp_signal_init(struct ptp_ocp_signal * s,struct signal_reg __iomem * reg)1917 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
1918 {
1919 u32 val;
1920
1921 iowrite32(0, ®->enable); /* disable */
1922
1923 val = ioread32(®->polarity);
1924 s->polarity = val ? true : false;
1925 s->duty = 50;
1926 }
1927
1928 static void
ptp_ocp_signal_init(struct ptp_ocp * bp)1929 ptp_ocp_signal_init(struct ptp_ocp *bp)
1930 {
1931 int i;
1932
1933 for (i = 0; i < 4; i++)
1934 if (bp->signal_out[i])
1935 _ptp_ocp_signal_init(&bp->signal[i],
1936 bp->signal_out[i]->mem);
1937 }
1938
1939 static void
ptp_ocp_attr_group_del(struct ptp_ocp * bp)1940 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
1941 {
1942 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
1943 kfree(bp->attr_group);
1944 }
1945
1946 static int
ptp_ocp_attr_group_add(struct ptp_ocp * bp,const struct ocp_attr_group * attr_tbl)1947 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
1948 const struct ocp_attr_group *attr_tbl)
1949 {
1950 int count, i;
1951 int err;
1952
1953 count = 0;
1954 for (i = 0; attr_tbl[i].cap; i++)
1955 if (attr_tbl[i].cap & bp->fw_cap)
1956 count++;
1957
1958 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
1959 GFP_KERNEL);
1960 if (!bp->attr_group)
1961 return -ENOMEM;
1962
1963 count = 0;
1964 for (i = 0; attr_tbl[i].cap; i++)
1965 if (attr_tbl[i].cap & bp->fw_cap)
1966 bp->attr_group[count++] = attr_tbl[i].group;
1967
1968 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
1969 if (err)
1970 bp->attr_group[0] = NULL;
1971
1972 return err;
1973 }
1974
1975 static void
ptp_ocp_enable_fpga(u32 __iomem * reg,u32 bit,bool enable)1976 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
1977 {
1978 u32 ctrl;
1979 bool on;
1980
1981 ctrl = ioread32(reg);
1982 on = ctrl & bit;
1983 if (on ^ enable) {
1984 ctrl &= ~bit;
1985 ctrl |= enable ? bit : 0;
1986 iowrite32(ctrl, reg);
1987 }
1988 }
1989
1990 static void
ptp_ocp_irig_out(struct ptp_ocp * bp,bool enable)1991 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
1992 {
1993 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
1994 IRIG_M_CTRL_ENABLE, enable);
1995 }
1996
1997 static void
ptp_ocp_irig_in(struct ptp_ocp * bp,bool enable)1998 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
1999 {
2000 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2001 IRIG_S_CTRL_ENABLE, enable);
2002 }
2003
2004 static void
ptp_ocp_dcf_out(struct ptp_ocp * bp,bool enable)2005 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2006 {
2007 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2008 DCF_M_CTRL_ENABLE, enable);
2009 }
2010
2011 static void
ptp_ocp_dcf_in(struct ptp_ocp * bp,bool enable)2012 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2013 {
2014 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2015 DCF_S_CTRL_ENABLE, enable);
2016 }
2017
2018 static void
__handle_signal_outputs(struct ptp_ocp * bp,u32 val)2019 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2020 {
2021 ptp_ocp_irig_out(bp, val & 0x00100010);
2022 ptp_ocp_dcf_out(bp, val & 0x00200020);
2023 }
2024
2025 static void
__handle_signal_inputs(struct ptp_ocp * bp,u32 val)2026 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2027 {
2028 ptp_ocp_irig_in(bp, val & 0x00100010);
2029 ptp_ocp_dcf_in(bp, val & 0x00200020);
2030 }
2031
2032 static u32
ptp_ocp_sma_fb_get(struct ptp_ocp * bp,int sma_nr)2033 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2034 {
2035 u32 __iomem *gpio;
2036 u32 shift;
2037
2038 if (bp->sma[sma_nr - 1].fixed_fcn)
2039 return (sma_nr - 1) & 1;
2040
2041 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2042 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2043 else
2044 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2045 shift = sma_nr & 1 ? 0 : 16;
2046
2047 return (ioread32(gpio) >> shift) & 0xffff;
2048 }
2049
2050 static int
ptp_ocp_sma_fb_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2051 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2052 {
2053 u32 reg, mask, shift;
2054 unsigned long flags;
2055 u32 __iomem *gpio;
2056
2057 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2058 shift = sma_nr & 1 ? 0 : 16;
2059
2060 mask = 0xffff << (16 - shift);
2061
2062 spin_lock_irqsave(&bp->lock, flags);
2063
2064 reg = ioread32(gpio);
2065 reg = (reg & mask) | (val << shift);
2066
2067 __handle_signal_outputs(bp, reg);
2068
2069 iowrite32(reg, gpio);
2070
2071 spin_unlock_irqrestore(&bp->lock, flags);
2072
2073 return 0;
2074 }
2075
2076 static int
ptp_ocp_sma_fb_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2077 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2078 {
2079 u32 reg, mask, shift;
2080 unsigned long flags;
2081 u32 __iomem *gpio;
2082
2083 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2084 shift = sma_nr & 1 ? 0 : 16;
2085
2086 mask = 0xffff << (16 - shift);
2087
2088 spin_lock_irqsave(&bp->lock, flags);
2089
2090 reg = ioread32(gpio);
2091 reg = (reg & mask) | (val << shift);
2092
2093 __handle_signal_inputs(bp, reg);
2094
2095 iowrite32(reg, gpio);
2096
2097 spin_unlock_irqrestore(&bp->lock, flags);
2098
2099 return 0;
2100 }
2101
2102 static void
ptp_ocp_sma_fb_init(struct ptp_ocp * bp)2103 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2104 {
2105 u32 reg;
2106 int i;
2107
2108 /* defaults */
2109 bp->sma[0].mode = SMA_MODE_IN;
2110 bp->sma[1].mode = SMA_MODE_IN;
2111 bp->sma[2].mode = SMA_MODE_OUT;
2112 bp->sma[3].mode = SMA_MODE_OUT;
2113 for (i = 0; i < 4; i++)
2114 bp->sma[i].default_fcn = i & 1;
2115
2116 /* If no SMA1 map, the pin functions and directions are fixed. */
2117 if (!bp->sma_map1) {
2118 for (i = 0; i < 4; i++) {
2119 bp->sma[i].fixed_fcn = true;
2120 bp->sma[i].fixed_dir = true;
2121 }
2122 return;
2123 }
2124
2125 /* If SMA2 GPIO output map is all 1, it is not present.
2126 * This indicates the firmware has fixed direction SMA pins.
2127 */
2128 reg = ioread32(&bp->sma_map2->gpio2);
2129 if (reg == 0xffffffff) {
2130 for (i = 0; i < 4; i++)
2131 bp->sma[i].fixed_dir = true;
2132 } else {
2133 reg = ioread32(&bp->sma_map1->gpio1);
2134 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2135 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2136
2137 reg = ioread32(&bp->sma_map1->gpio2);
2138 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2139 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2140 }
2141 }
2142
2143 static const struct ocp_sma_op ocp_fb_sma_op = {
2144 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2145 .init = ptp_ocp_sma_fb_init,
2146 .get = ptp_ocp_sma_fb_get,
2147 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2148 .set_output = ptp_ocp_sma_fb_set_output,
2149 };
2150
2151 static int
ptp_ocp_fb_set_pins(struct ptp_ocp * bp)2152 ptp_ocp_fb_set_pins(struct ptp_ocp *bp)
2153 {
2154 struct ptp_pin_desc *config;
2155 int i;
2156
2157 config = kzalloc(sizeof(*config) * 4, GFP_KERNEL);
2158 if (!config)
2159 return -ENOMEM;
2160
2161 for (i = 0; i < 4; i++) {
2162 sprintf(config[i].name, "sma%d", i + 1);
2163 config[i].index = i;
2164 }
2165
2166 bp->ptp_info.n_pins = 4;
2167 bp->ptp_info.pin_config = config;
2168
2169 return 0;
2170 }
2171
2172 static void
ptp_ocp_fb_set_version(struct ptp_ocp * bp)2173 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2174 {
2175 u64 cap = OCP_CAP_BASIC;
2176 u32 version;
2177
2178 version = ioread32(&bp->image->version);
2179
2180 /* if lower 16 bits are empty, this is the fw loader. */
2181 if ((version & 0xffff) == 0) {
2182 version = version >> 16;
2183 bp->fw_loader = true;
2184 }
2185
2186 bp->fw_tag = version >> 15;
2187 bp->fw_version = version & 0x7fff;
2188
2189 if (bp->fw_tag) {
2190 /* FPGA firmware */
2191 if (version >= 5)
2192 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2193 } else {
2194 /* SOM firmware */
2195 if (version >= 19)
2196 cap |= OCP_CAP_SIGNAL;
2197 if (version >= 20)
2198 cap |= OCP_CAP_FREQ;
2199 }
2200
2201 bp->fw_cap = cap;
2202 }
2203
2204 /* FB specific board initializers; last "resource" registered. */
2205 static int
ptp_ocp_fb_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2206 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2207 {
2208 int err;
2209
2210 bp->flash_start = 1024 * 4096;
2211 bp->eeprom_map = fb_eeprom_map;
2212 bp->fw_version = ioread32(&bp->image->version);
2213 bp->sma_op = &ocp_fb_sma_op;
2214
2215 ptp_ocp_fb_set_version(bp);
2216
2217 ptp_ocp_tod_init(bp);
2218 ptp_ocp_nmea_out_init(bp);
2219 ptp_ocp_sma_init(bp);
2220 ptp_ocp_signal_init(bp);
2221
2222 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2223 if (err)
2224 return err;
2225
2226 err = ptp_ocp_fb_set_pins(bp);
2227 if (err)
2228 return err;
2229
2230 return ptp_ocp_init_clock(bp);
2231 }
2232
2233 static bool
ptp_ocp_allow_irq(struct ptp_ocp * bp,struct ocp_resource * r)2234 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2235 {
2236 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2237
2238 if (!allow)
2239 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2240 r->irq_vec, r->name);
2241 return allow;
2242 }
2243
2244 static int
ptp_ocp_register_resources(struct ptp_ocp * bp,kernel_ulong_t driver_data)2245 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2246 {
2247 struct ocp_resource *r, *table;
2248 int err = 0;
2249
2250 table = (struct ocp_resource *)driver_data;
2251 for (r = table; r->setup; r++) {
2252 if (!ptp_ocp_allow_irq(bp, r))
2253 continue;
2254 err = r->setup(bp, r);
2255 if (err) {
2256 dev_err(&bp->pdev->dev,
2257 "Could not register %s: err %d\n",
2258 r->name, err);
2259 break;
2260 }
2261 }
2262 return err;
2263 }
2264
2265 static ssize_t
ptp_ocp_show_output(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2266 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2267 int def_val)
2268 {
2269 const char *name;
2270 ssize_t count;
2271
2272 count = sysfs_emit(buf, "OUT: ");
2273 name = ptp_ocp_select_name_from_val(tbl, val);
2274 if (!name)
2275 name = ptp_ocp_select_name_from_val(tbl, def_val);
2276 count += sysfs_emit_at(buf, count, "%s\n", name);
2277 return count;
2278 }
2279
2280 static ssize_t
ptp_ocp_show_inputs(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2281 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2282 int def_val)
2283 {
2284 const char *name;
2285 ssize_t count;
2286 int i;
2287
2288 count = sysfs_emit(buf, "IN: ");
2289 for (i = 0; tbl[i].name; i++) {
2290 if (val & tbl[i].value) {
2291 name = tbl[i].name;
2292 count += sysfs_emit_at(buf, count, "%s ", name);
2293 }
2294 }
2295 if (!val && def_val >= 0) {
2296 name = ptp_ocp_select_name_from_val(tbl, def_val);
2297 count += sysfs_emit_at(buf, count, "%s ", name);
2298 }
2299 if (count)
2300 count--;
2301 count += sysfs_emit_at(buf, count, "\n");
2302 return count;
2303 }
2304
2305 static int
sma_parse_inputs(const struct ocp_selector * const tbl[],const char * buf,enum ptp_ocp_sma_mode * mode)2306 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2307 enum ptp_ocp_sma_mode *mode)
2308 {
2309 int idx, count, dir;
2310 char **argv;
2311 int ret;
2312
2313 argv = argv_split(GFP_KERNEL, buf, &count);
2314 if (!argv)
2315 return -ENOMEM;
2316
2317 ret = -EINVAL;
2318 if (!count)
2319 goto out;
2320
2321 idx = 0;
2322 dir = *mode == SMA_MODE_IN ? 0 : 1;
2323 if (!strcasecmp("IN:", argv[0])) {
2324 dir = 0;
2325 idx++;
2326 }
2327 if (!strcasecmp("OUT:", argv[0])) {
2328 dir = 1;
2329 idx++;
2330 }
2331 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2332
2333 ret = 0;
2334 for (; idx < count; idx++)
2335 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2336 if (ret < 0)
2337 ret = -EINVAL;
2338
2339 out:
2340 argv_free(argv);
2341 return ret;
2342 }
2343
2344 static ssize_t
ptp_ocp_sma_show(struct ptp_ocp * bp,int sma_nr,char * buf,int default_in_val,int default_out_val)2345 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2346 int default_in_val, int default_out_val)
2347 {
2348 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2349 const struct ocp_selector * const *tbl;
2350 u32 val;
2351
2352 tbl = bp->sma_op->tbl;
2353 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2354
2355 if (sma->mode == SMA_MODE_IN) {
2356 if (sma->disabled)
2357 val = SMA_DISABLE;
2358 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2359 }
2360
2361 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2362 }
2363
2364 static ssize_t
sma1_show(struct device * dev,struct device_attribute * attr,char * buf)2365 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2366 {
2367 struct ptp_ocp *bp = dev_get_drvdata(dev);
2368
2369 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2370 }
2371
2372 static ssize_t
sma2_show(struct device * dev,struct device_attribute * attr,char * buf)2373 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2374 {
2375 struct ptp_ocp *bp = dev_get_drvdata(dev);
2376
2377 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2378 }
2379
2380 static ssize_t
sma3_show(struct device * dev,struct device_attribute * attr,char * buf)2381 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2382 {
2383 struct ptp_ocp *bp = dev_get_drvdata(dev);
2384
2385 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2386 }
2387
2388 static ssize_t
sma4_show(struct device * dev,struct device_attribute * attr,char * buf)2389 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2390 {
2391 struct ptp_ocp *bp = dev_get_drvdata(dev);
2392
2393 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2394 }
2395
2396 static int
ptp_ocp_sma_store(struct ptp_ocp * bp,const char * buf,int sma_nr)2397 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
2398 {
2399 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2400 enum ptp_ocp_sma_mode mode;
2401 int val;
2402
2403 mode = sma->mode;
2404 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
2405 if (val < 0)
2406 return val;
2407
2408 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
2409 return -EOPNOTSUPP;
2410
2411 if (sma->fixed_fcn) {
2412 if (val != sma->default_fcn)
2413 return -EOPNOTSUPP;
2414 return 0;
2415 }
2416
2417 sma->disabled = !!(val & SMA_DISABLE);
2418
2419 if (mode != sma->mode) {
2420 if (mode == SMA_MODE_IN)
2421 ptp_ocp_sma_set_output(bp, sma_nr, 0);
2422 else
2423 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
2424 sma->mode = mode;
2425 }
2426
2427 if (!sma->fixed_dir)
2428 val |= SMA_ENABLE; /* add enable bit */
2429
2430 if (sma->disabled)
2431 val = 0;
2432
2433 if (mode == SMA_MODE_IN)
2434 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
2435 else
2436 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
2437
2438 return val;
2439 }
2440
2441 static ssize_t
sma1_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2442 sma1_store(struct device *dev, struct device_attribute *attr,
2443 const char *buf, size_t count)
2444 {
2445 struct ptp_ocp *bp = dev_get_drvdata(dev);
2446 int err;
2447
2448 err = ptp_ocp_sma_store(bp, buf, 1);
2449 return err ? err : count;
2450 }
2451
2452 static ssize_t
sma2_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2453 sma2_store(struct device *dev, struct device_attribute *attr,
2454 const char *buf, size_t count)
2455 {
2456 struct ptp_ocp *bp = dev_get_drvdata(dev);
2457 int err;
2458
2459 err = ptp_ocp_sma_store(bp, buf, 2);
2460 return err ? err : count;
2461 }
2462
2463 static ssize_t
sma3_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2464 sma3_store(struct device *dev, struct device_attribute *attr,
2465 const char *buf, size_t count)
2466 {
2467 struct ptp_ocp *bp = dev_get_drvdata(dev);
2468 int err;
2469
2470 err = ptp_ocp_sma_store(bp, buf, 3);
2471 return err ? err : count;
2472 }
2473
2474 static ssize_t
sma4_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2475 sma4_store(struct device *dev, struct device_attribute *attr,
2476 const char *buf, size_t count)
2477 {
2478 struct ptp_ocp *bp = dev_get_drvdata(dev);
2479 int err;
2480
2481 err = ptp_ocp_sma_store(bp, buf, 4);
2482 return err ? err : count;
2483 }
2484 static DEVICE_ATTR_RW(sma1);
2485 static DEVICE_ATTR_RW(sma2);
2486 static DEVICE_ATTR_RW(sma3);
2487 static DEVICE_ATTR_RW(sma4);
2488
2489 static ssize_t
available_sma_inputs_show(struct device * dev,struct device_attribute * attr,char * buf)2490 available_sma_inputs_show(struct device *dev,
2491 struct device_attribute *attr, char *buf)
2492 {
2493 struct ptp_ocp *bp = dev_get_drvdata(dev);
2494
2495 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
2496 }
2497 static DEVICE_ATTR_RO(available_sma_inputs);
2498
2499 static ssize_t
available_sma_outputs_show(struct device * dev,struct device_attribute * attr,char * buf)2500 available_sma_outputs_show(struct device *dev,
2501 struct device_attribute *attr, char *buf)
2502 {
2503 struct ptp_ocp *bp = dev_get_drvdata(dev);
2504
2505 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
2506 }
2507 static DEVICE_ATTR_RO(available_sma_outputs);
2508
2509 #define EXT_ATTR_RO(_group, _name, _val) \
2510 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
2511 { __ATTR_RO(_name), (void *)_val }
2512 #define EXT_ATTR_RW(_group, _name, _val) \
2513 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
2514 { __ATTR_RW(_name), (void *)_val }
2515 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
2516
2517 /* period [duty [phase [polarity]]] */
2518 static ssize_t
signal_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2519 signal_store(struct device *dev, struct device_attribute *attr,
2520 const char *buf, size_t count)
2521 {
2522 struct dev_ext_attribute *ea = to_ext_attr(attr);
2523 struct ptp_ocp *bp = dev_get_drvdata(dev);
2524 struct ptp_ocp_signal s = { };
2525 int gen = (uintptr_t)ea->var;
2526 int argc, err;
2527 char **argv;
2528
2529 argv = argv_split(GFP_KERNEL, buf, &argc);
2530 if (!argv)
2531 return -ENOMEM;
2532
2533 err = -EINVAL;
2534 s.duty = bp->signal[gen].duty;
2535 s.phase = bp->signal[gen].phase;
2536 s.period = bp->signal[gen].period;
2537 s.polarity = bp->signal[gen].polarity;
2538
2539 switch (argc) {
2540 case 4:
2541 argc--;
2542 err = kstrtobool(argv[argc], &s.polarity);
2543 if (err)
2544 goto out;
2545 fallthrough;
2546 case 3:
2547 argc--;
2548 err = kstrtou64(argv[argc], 0, &s.phase);
2549 if (err)
2550 goto out;
2551 fallthrough;
2552 case 2:
2553 argc--;
2554 err = kstrtoint(argv[argc], 0, &s.duty);
2555 if (err)
2556 goto out;
2557 fallthrough;
2558 case 1:
2559 argc--;
2560 err = kstrtou64(argv[argc], 0, &s.period);
2561 if (err)
2562 goto out;
2563 break;
2564 default:
2565 goto out;
2566 }
2567
2568 err = ptp_ocp_signal_set(bp, gen, &s);
2569 if (err)
2570 goto out;
2571
2572 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
2573
2574 out:
2575 argv_free(argv);
2576 return err ? err : count;
2577 }
2578
2579 static ssize_t
signal_show(struct device * dev,struct device_attribute * attr,char * buf)2580 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
2581 {
2582 struct dev_ext_attribute *ea = to_ext_attr(attr);
2583 struct ptp_ocp *bp = dev_get_drvdata(dev);
2584 struct ptp_ocp_signal *signal;
2585 struct timespec64 ts;
2586 ssize_t count;
2587 int i;
2588
2589 i = (uintptr_t)ea->var;
2590 signal = &bp->signal[i];
2591
2592 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
2593 signal->duty, signal->phase, signal->polarity);
2594
2595 ts = ktime_to_timespec64(signal->start);
2596 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
2597
2598 return count;
2599 }
2600 static EXT_ATTR_RW(signal, signal, 0);
2601 static EXT_ATTR_RW(signal, signal, 1);
2602 static EXT_ATTR_RW(signal, signal, 2);
2603 static EXT_ATTR_RW(signal, signal, 3);
2604
2605 static ssize_t
duty_show(struct device * dev,struct device_attribute * attr,char * buf)2606 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
2607 {
2608 struct dev_ext_attribute *ea = to_ext_attr(attr);
2609 struct ptp_ocp *bp = dev_get_drvdata(dev);
2610 int i = (uintptr_t)ea->var;
2611
2612 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
2613 }
2614 static EXT_ATTR_RO(signal, duty, 0);
2615 static EXT_ATTR_RO(signal, duty, 1);
2616 static EXT_ATTR_RO(signal, duty, 2);
2617 static EXT_ATTR_RO(signal, duty, 3);
2618
2619 static ssize_t
period_show(struct device * dev,struct device_attribute * attr,char * buf)2620 period_show(struct device *dev, struct device_attribute *attr, char *buf)
2621 {
2622 struct dev_ext_attribute *ea = to_ext_attr(attr);
2623 struct ptp_ocp *bp = dev_get_drvdata(dev);
2624 int i = (uintptr_t)ea->var;
2625
2626 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
2627 }
2628 static EXT_ATTR_RO(signal, period, 0);
2629 static EXT_ATTR_RO(signal, period, 1);
2630 static EXT_ATTR_RO(signal, period, 2);
2631 static EXT_ATTR_RO(signal, period, 3);
2632
2633 static ssize_t
phase_show(struct device * dev,struct device_attribute * attr,char * buf)2634 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
2635 {
2636 struct dev_ext_attribute *ea = to_ext_attr(attr);
2637 struct ptp_ocp *bp = dev_get_drvdata(dev);
2638 int i = (uintptr_t)ea->var;
2639
2640 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
2641 }
2642 static EXT_ATTR_RO(signal, phase, 0);
2643 static EXT_ATTR_RO(signal, phase, 1);
2644 static EXT_ATTR_RO(signal, phase, 2);
2645 static EXT_ATTR_RO(signal, phase, 3);
2646
2647 static ssize_t
polarity_show(struct device * dev,struct device_attribute * attr,char * buf)2648 polarity_show(struct device *dev, struct device_attribute *attr,
2649 char *buf)
2650 {
2651 struct dev_ext_attribute *ea = to_ext_attr(attr);
2652 struct ptp_ocp *bp = dev_get_drvdata(dev);
2653 int i = (uintptr_t)ea->var;
2654
2655 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
2656 }
2657 static EXT_ATTR_RO(signal, polarity, 0);
2658 static EXT_ATTR_RO(signal, polarity, 1);
2659 static EXT_ATTR_RO(signal, polarity, 2);
2660 static EXT_ATTR_RO(signal, polarity, 3);
2661
2662 static ssize_t
running_show(struct device * dev,struct device_attribute * attr,char * buf)2663 running_show(struct device *dev, struct device_attribute *attr, char *buf)
2664 {
2665 struct dev_ext_attribute *ea = to_ext_attr(attr);
2666 struct ptp_ocp *bp = dev_get_drvdata(dev);
2667 int i = (uintptr_t)ea->var;
2668
2669 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
2670 }
2671 static EXT_ATTR_RO(signal, running, 0);
2672 static EXT_ATTR_RO(signal, running, 1);
2673 static EXT_ATTR_RO(signal, running, 2);
2674 static EXT_ATTR_RO(signal, running, 3);
2675
2676 static ssize_t
start_show(struct device * dev,struct device_attribute * attr,char * buf)2677 start_show(struct device *dev, struct device_attribute *attr, char *buf)
2678 {
2679 struct dev_ext_attribute *ea = to_ext_attr(attr);
2680 struct ptp_ocp *bp = dev_get_drvdata(dev);
2681 int i = (uintptr_t)ea->var;
2682 struct timespec64 ts;
2683
2684 ts = ktime_to_timespec64(bp->signal[i].start);
2685 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
2686 }
2687 static EXT_ATTR_RO(signal, start, 0);
2688 static EXT_ATTR_RO(signal, start, 1);
2689 static EXT_ATTR_RO(signal, start, 2);
2690 static EXT_ATTR_RO(signal, start, 3);
2691
2692 static ssize_t
seconds_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2693 seconds_store(struct device *dev, struct device_attribute *attr,
2694 const char *buf, size_t count)
2695 {
2696 struct dev_ext_attribute *ea = to_ext_attr(attr);
2697 struct ptp_ocp *bp = dev_get_drvdata(dev);
2698 int idx = (uintptr_t)ea->var;
2699 u32 val;
2700 int err;
2701
2702 err = kstrtou32(buf, 0, &val);
2703 if (err)
2704 return err;
2705 if (val > 0xff)
2706 return -EINVAL;
2707
2708 if (val)
2709 val = (val << 8) | 0x1;
2710
2711 iowrite32(val, &bp->freq_in[idx]->ctrl);
2712
2713 return count;
2714 }
2715
2716 static ssize_t
seconds_show(struct device * dev,struct device_attribute * attr,char * buf)2717 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
2718 {
2719 struct dev_ext_attribute *ea = to_ext_attr(attr);
2720 struct ptp_ocp *bp = dev_get_drvdata(dev);
2721 int idx = (uintptr_t)ea->var;
2722 u32 val;
2723
2724 val = ioread32(&bp->freq_in[idx]->ctrl);
2725 if (val & 1)
2726 val = (val >> 8) & 0xff;
2727 else
2728 val = 0;
2729
2730 return sysfs_emit(buf, "%u\n", val);
2731 }
2732 static EXT_ATTR_RW(freq, seconds, 0);
2733 static EXT_ATTR_RW(freq, seconds, 1);
2734 static EXT_ATTR_RW(freq, seconds, 2);
2735 static EXT_ATTR_RW(freq, seconds, 3);
2736
2737 static ssize_t
frequency_show(struct device * dev,struct device_attribute * attr,char * buf)2738 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
2739 {
2740 struct dev_ext_attribute *ea = to_ext_attr(attr);
2741 struct ptp_ocp *bp = dev_get_drvdata(dev);
2742 int idx = (uintptr_t)ea->var;
2743 u32 val;
2744
2745 val = ioread32(&bp->freq_in[idx]->status);
2746 if (val & FREQ_STATUS_ERROR)
2747 return sysfs_emit(buf, "error\n");
2748 if (val & FREQ_STATUS_OVERRUN)
2749 return sysfs_emit(buf, "overrun\n");
2750 if (val & FREQ_STATUS_VALID)
2751 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
2752 return 0;
2753 }
2754 static EXT_ATTR_RO(freq, frequency, 0);
2755 static EXT_ATTR_RO(freq, frequency, 1);
2756 static EXT_ATTR_RO(freq, frequency, 2);
2757 static EXT_ATTR_RO(freq, frequency, 3);
2758
2759 static ssize_t
serialnum_show(struct device * dev,struct device_attribute * attr,char * buf)2760 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
2761 {
2762 struct ptp_ocp *bp = dev_get_drvdata(dev);
2763
2764 if (!bp->has_eeprom_data)
2765 ptp_ocp_read_eeprom(bp);
2766
2767 return sysfs_emit(buf, "%pM\n", bp->serial);
2768 }
2769 static DEVICE_ATTR_RO(serialnum);
2770
2771 static ssize_t
gnss_sync_show(struct device * dev,struct device_attribute * attr,char * buf)2772 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
2773 {
2774 struct ptp_ocp *bp = dev_get_drvdata(dev);
2775 ssize_t ret;
2776
2777 if (bp->gnss_lost)
2778 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
2779 else
2780 ret = sysfs_emit(buf, "SYNC\n");
2781
2782 return ret;
2783 }
2784 static DEVICE_ATTR_RO(gnss_sync);
2785
2786 static ssize_t
utc_tai_offset_show(struct device * dev,struct device_attribute * attr,char * buf)2787 utc_tai_offset_show(struct device *dev,
2788 struct device_attribute *attr, char *buf)
2789 {
2790 struct ptp_ocp *bp = dev_get_drvdata(dev);
2791
2792 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
2793 }
2794
2795 static ssize_t
utc_tai_offset_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2796 utc_tai_offset_store(struct device *dev,
2797 struct device_attribute *attr,
2798 const char *buf, size_t count)
2799 {
2800 struct ptp_ocp *bp = dev_get_drvdata(dev);
2801 int err;
2802 u32 val;
2803
2804 err = kstrtou32(buf, 0, &val);
2805 if (err)
2806 return err;
2807
2808 ptp_ocp_utc_distribute(bp, val);
2809
2810 return count;
2811 }
2812 static DEVICE_ATTR_RW(utc_tai_offset);
2813
2814 static ssize_t
ts_window_adjust_show(struct device * dev,struct device_attribute * attr,char * buf)2815 ts_window_adjust_show(struct device *dev,
2816 struct device_attribute *attr, char *buf)
2817 {
2818 struct ptp_ocp *bp = dev_get_drvdata(dev);
2819
2820 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
2821 }
2822
2823 static ssize_t
ts_window_adjust_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2824 ts_window_adjust_store(struct device *dev,
2825 struct device_attribute *attr,
2826 const char *buf, size_t count)
2827 {
2828 struct ptp_ocp *bp = dev_get_drvdata(dev);
2829 int err;
2830 u32 val;
2831
2832 err = kstrtou32(buf, 0, &val);
2833 if (err)
2834 return err;
2835
2836 bp->ts_window_adjust = val;
2837
2838 return count;
2839 }
2840 static DEVICE_ATTR_RW(ts_window_adjust);
2841
2842 static ssize_t
irig_b_mode_show(struct device * dev,struct device_attribute * attr,char * buf)2843 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
2844 {
2845 struct ptp_ocp *bp = dev_get_drvdata(dev);
2846 u32 val;
2847
2848 val = ioread32(&bp->irig_out->ctrl);
2849 val = (val >> 16) & 0x07;
2850 return sysfs_emit(buf, "%d\n", val);
2851 }
2852
2853 static ssize_t
irig_b_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2854 irig_b_mode_store(struct device *dev,
2855 struct device_attribute *attr,
2856 const char *buf, size_t count)
2857 {
2858 struct ptp_ocp *bp = dev_get_drvdata(dev);
2859 unsigned long flags;
2860 int err;
2861 u32 reg;
2862 u8 val;
2863
2864 err = kstrtou8(buf, 0, &val);
2865 if (err)
2866 return err;
2867 if (val > 7)
2868 return -EINVAL;
2869
2870 reg = ((val & 0x7) << 16);
2871
2872 spin_lock_irqsave(&bp->lock, flags);
2873 iowrite32(0, &bp->irig_out->ctrl); /* disable */
2874 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
2875 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
2876 spin_unlock_irqrestore(&bp->lock, flags);
2877
2878 return count;
2879 }
2880 static DEVICE_ATTR_RW(irig_b_mode);
2881
2882 static ssize_t
clock_source_show(struct device * dev,struct device_attribute * attr,char * buf)2883 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
2884 {
2885 struct ptp_ocp *bp = dev_get_drvdata(dev);
2886 const char *p;
2887 u32 select;
2888
2889 select = ioread32(&bp->reg->select);
2890 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
2891
2892 return sysfs_emit(buf, "%s\n", p);
2893 }
2894
2895 static ssize_t
clock_source_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2896 clock_source_store(struct device *dev, struct device_attribute *attr,
2897 const char *buf, size_t count)
2898 {
2899 struct ptp_ocp *bp = dev_get_drvdata(dev);
2900 unsigned long flags;
2901 int val;
2902
2903 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
2904 if (val < 0)
2905 return val;
2906
2907 spin_lock_irqsave(&bp->lock, flags);
2908 iowrite32(val, &bp->reg->select);
2909 spin_unlock_irqrestore(&bp->lock, flags);
2910
2911 return count;
2912 }
2913 static DEVICE_ATTR_RW(clock_source);
2914
2915 static ssize_t
available_clock_sources_show(struct device * dev,struct device_attribute * attr,char * buf)2916 available_clock_sources_show(struct device *dev,
2917 struct device_attribute *attr, char *buf)
2918 {
2919 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
2920 }
2921 static DEVICE_ATTR_RO(available_clock_sources);
2922
2923 static ssize_t
clock_status_drift_show(struct device * dev,struct device_attribute * attr,char * buf)2924 clock_status_drift_show(struct device *dev,
2925 struct device_attribute *attr, char *buf)
2926 {
2927 struct ptp_ocp *bp = dev_get_drvdata(dev);
2928 u32 val;
2929 int res;
2930
2931 val = ioread32(&bp->reg->status_drift);
2932 res = (val & ~INT_MAX) ? -1 : 1;
2933 res *= (val & INT_MAX);
2934 return sysfs_emit(buf, "%d\n", res);
2935 }
2936 static DEVICE_ATTR_RO(clock_status_drift);
2937
2938 static ssize_t
clock_status_offset_show(struct device * dev,struct device_attribute * attr,char * buf)2939 clock_status_offset_show(struct device *dev,
2940 struct device_attribute *attr, char *buf)
2941 {
2942 struct ptp_ocp *bp = dev_get_drvdata(dev);
2943 u32 val;
2944 int res;
2945
2946 val = ioread32(&bp->reg->status_offset);
2947 res = (val & ~INT_MAX) ? -1 : 1;
2948 res *= (val & INT_MAX);
2949 return sysfs_emit(buf, "%d\n", res);
2950 }
2951 static DEVICE_ATTR_RO(clock_status_offset);
2952
2953 static ssize_t
tod_correction_show(struct device * dev,struct device_attribute * attr,char * buf)2954 tod_correction_show(struct device *dev,
2955 struct device_attribute *attr, char *buf)
2956 {
2957 struct ptp_ocp *bp = dev_get_drvdata(dev);
2958 u32 val;
2959 int res;
2960
2961 val = ioread32(&bp->tod->adj_sec);
2962 res = (val & ~INT_MAX) ? -1 : 1;
2963 res *= (val & INT_MAX);
2964 return sysfs_emit(buf, "%d\n", res);
2965 }
2966
2967 static ssize_t
tod_correction_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2968 tod_correction_store(struct device *dev, struct device_attribute *attr,
2969 const char *buf, size_t count)
2970 {
2971 struct ptp_ocp *bp = dev_get_drvdata(dev);
2972 unsigned long flags;
2973 int err, res;
2974 u32 val = 0;
2975
2976 err = kstrtos32(buf, 0, &res);
2977 if (err)
2978 return err;
2979 if (res < 0) {
2980 res *= -1;
2981 val |= BIT(31);
2982 }
2983 val |= res;
2984
2985 spin_lock_irqsave(&bp->lock, flags);
2986 iowrite32(val, &bp->tod->adj_sec);
2987 spin_unlock_irqrestore(&bp->lock, flags);
2988
2989 return count;
2990 }
2991 static DEVICE_ATTR_RW(tod_correction);
2992
2993 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
2994 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
2995 &dev_attr_signal##_nr##_signal.attr.attr, \
2996 &dev_attr_signal##_nr##_duty.attr.attr, \
2997 &dev_attr_signal##_nr##_phase.attr.attr, \
2998 &dev_attr_signal##_nr##_period.attr.attr, \
2999 &dev_attr_signal##_nr##_polarity.attr.attr, \
3000 &dev_attr_signal##_nr##_running.attr.attr, \
3001 &dev_attr_signal##_nr##_start.attr.attr, \
3002 NULL, \
3003 }
3004
3005 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3006 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3007 static const struct attribute_group \
3008 fb_timecard_signal##_nr##_group = { \
3009 .name = #_name, \
3010 .attrs = fb_timecard_signal##_nr##_attrs, \
3011 }
3012
3013 DEVICE_SIGNAL_GROUP(gen1, 0);
3014 DEVICE_SIGNAL_GROUP(gen2, 1);
3015 DEVICE_SIGNAL_GROUP(gen3, 2);
3016 DEVICE_SIGNAL_GROUP(gen4, 3);
3017
3018 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3019 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3020 &dev_attr_freq##_nr##_seconds.attr.attr, \
3021 &dev_attr_freq##_nr##_frequency.attr.attr, \
3022 NULL, \
3023 }
3024
3025 #define DEVICE_FREQ_GROUP(_name, _nr) \
3026 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3027 static const struct attribute_group \
3028 fb_timecard_freq##_nr##_group = { \
3029 .name = #_name, \
3030 .attrs = fb_timecard_freq##_nr##_attrs, \
3031 }
3032
3033 DEVICE_FREQ_GROUP(freq1, 0);
3034 DEVICE_FREQ_GROUP(freq2, 1);
3035 DEVICE_FREQ_GROUP(freq3, 2);
3036 DEVICE_FREQ_GROUP(freq4, 3);
3037
3038 static struct attribute *fb_timecard_attrs[] = {
3039 &dev_attr_serialnum.attr,
3040 &dev_attr_gnss_sync.attr,
3041 &dev_attr_clock_source.attr,
3042 &dev_attr_available_clock_sources.attr,
3043 &dev_attr_sma1.attr,
3044 &dev_attr_sma2.attr,
3045 &dev_attr_sma3.attr,
3046 &dev_attr_sma4.attr,
3047 &dev_attr_available_sma_inputs.attr,
3048 &dev_attr_available_sma_outputs.attr,
3049 &dev_attr_clock_status_drift.attr,
3050 &dev_attr_clock_status_offset.attr,
3051 &dev_attr_irig_b_mode.attr,
3052 &dev_attr_utc_tai_offset.attr,
3053 &dev_attr_ts_window_adjust.attr,
3054 &dev_attr_tod_correction.attr,
3055 NULL,
3056 };
3057 static const struct attribute_group fb_timecard_group = {
3058 .attrs = fb_timecard_attrs,
3059 };
3060 static const struct ocp_attr_group fb_timecard_groups[] = {
3061 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3062 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3063 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3064 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3065 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3066 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3067 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3068 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3069 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3070 { },
3071 };
3072
3073 static void
gpio_input_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit,const char * def)3074 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3075 const char *def)
3076 {
3077 int i;
3078
3079 for (i = 0; i < 4; i++) {
3080 if (bp->sma[i].mode != SMA_MODE_IN)
3081 continue;
3082 if (map[i][0] & (1 << bit)) {
3083 sprintf(buf, "sma%d", i + 1);
3084 return;
3085 }
3086 }
3087 if (!def)
3088 def = "----";
3089 strcpy(buf, def);
3090 }
3091
3092 static void
gpio_output_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit)3093 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3094 {
3095 char *ans = buf;
3096 int i;
3097
3098 strcpy(ans, "----");
3099 for (i = 0; i < 4; i++) {
3100 if (bp->sma[i].mode != SMA_MODE_OUT)
3101 continue;
3102 if (map[i][1] & (1 << bit))
3103 ans += sprintf(ans, "sma%d ", i + 1);
3104 }
3105 }
3106
3107 static void
_signal_summary_show(struct seq_file * s,struct ptp_ocp * bp,int nr)3108 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3109 {
3110 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3111 struct ptp_ocp_signal *signal = &bp->signal[nr];
3112 char label[8];
3113 bool on;
3114 u32 val;
3115
3116 if (!signal)
3117 return;
3118
3119 on = signal->running;
3120 sprintf(label, "GEN%d", nr + 1);
3121 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3122 label, on ? " ON" : "OFF",
3123 signal->period, signal->duty, signal->phase,
3124 signal->polarity);
3125
3126 val = ioread32(®->enable);
3127 seq_printf(s, " [%x", val);
3128 val = ioread32(®->status);
3129 seq_printf(s, " %x]", val);
3130
3131 seq_printf(s, " start:%llu\n", signal->start);
3132 }
3133
3134 static void
_frequency_summary_show(struct seq_file * s,int nr,struct frequency_reg __iomem * reg)3135 _frequency_summary_show(struct seq_file *s, int nr,
3136 struct frequency_reg __iomem *reg)
3137 {
3138 char label[8];
3139 bool on;
3140 u32 val;
3141
3142 if (!reg)
3143 return;
3144
3145 sprintf(label, "FREQ%d", nr + 1);
3146 val = ioread32(®->ctrl);
3147 on = val & 1;
3148 val = (val >> 8) & 0xff;
3149 seq_printf(s, "%7s: %s, sec:%u",
3150 label,
3151 on ? " ON" : "OFF",
3152 val);
3153
3154 val = ioread32(®->status);
3155 if (val & FREQ_STATUS_ERROR)
3156 seq_printf(s, ", error");
3157 if (val & FREQ_STATUS_OVERRUN)
3158 seq_printf(s, ", overrun");
3159 if (val & FREQ_STATUS_VALID)
3160 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
3161 seq_printf(s, " reg:%x\n", val);
3162 }
3163
3164 static int
ptp_ocp_summary_show(struct seq_file * s,void * data)3165 ptp_ocp_summary_show(struct seq_file *s, void *data)
3166 {
3167 struct device *dev = s->private;
3168 struct ptp_system_timestamp sts;
3169 struct ts_reg __iomem *ts_reg;
3170 char *buf, *src, *mac_src;
3171 struct timespec64 ts;
3172 struct ptp_ocp *bp;
3173 u16 sma_val[4][2];
3174 u32 ctrl, val;
3175 bool on, map;
3176 int i;
3177
3178 buf = (char *)__get_free_page(GFP_KERNEL);
3179 if (!buf)
3180 return -ENOMEM;
3181
3182 bp = dev_get_drvdata(dev);
3183
3184 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
3185 if (bp->gnss_port != -1)
3186 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1", bp->gnss_port);
3187 if (bp->gnss2_port != -1)
3188 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2", bp->gnss2_port);
3189 if (bp->mac_port != -1)
3190 seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port);
3191 if (bp->nmea_port != -1)
3192 seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port);
3193
3194 memset(sma_val, 0xff, sizeof(sma_val));
3195 if (bp->sma_map1) {
3196 u32 reg;
3197
3198 reg = ioread32(&bp->sma_map1->gpio1);
3199 sma_val[0][0] = reg & 0xffff;
3200 sma_val[1][0] = reg >> 16;
3201
3202 reg = ioread32(&bp->sma_map1->gpio2);
3203 sma_val[2][1] = reg & 0xffff;
3204 sma_val[3][1] = reg >> 16;
3205
3206 reg = ioread32(&bp->sma_map2->gpio1);
3207 sma_val[2][0] = reg & 0xffff;
3208 sma_val[3][0] = reg >> 16;
3209
3210 reg = ioread32(&bp->sma_map2->gpio2);
3211 sma_val[0][1] = reg & 0xffff;
3212 sma_val[1][1] = reg >> 16;
3213 }
3214
3215 sma1_show(dev, NULL, buf);
3216 seq_printf(s, " sma1: %04x,%04x %s",
3217 sma_val[0][0], sma_val[0][1], buf);
3218
3219 sma2_show(dev, NULL, buf);
3220 seq_printf(s, " sma2: %04x,%04x %s",
3221 sma_val[1][0], sma_val[1][1], buf);
3222
3223 sma3_show(dev, NULL, buf);
3224 seq_printf(s, " sma3: %04x,%04x %s",
3225 sma_val[2][0], sma_val[2][1], buf);
3226
3227 sma4_show(dev, NULL, buf);
3228 seq_printf(s, " sma4: %04x,%04x %s",
3229 sma_val[3][0], sma_val[3][1], buf);
3230
3231 if (bp->ts0) {
3232 ts_reg = bp->ts0->mem;
3233 on = ioread32(&ts_reg->enable);
3234 src = "GNSS1";
3235 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
3236 on ? " ON" : "OFF", src);
3237 }
3238
3239 if (bp->ts1) {
3240 ts_reg = bp->ts1->mem;
3241 on = ioread32(&ts_reg->enable);
3242 gpio_input_map(buf, bp, sma_val, 2, NULL);
3243 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
3244 on ? " ON" : "OFF", buf);
3245 }
3246
3247 if (bp->ts2) {
3248 ts_reg = bp->ts2->mem;
3249 on = ioread32(&ts_reg->enable);
3250 gpio_input_map(buf, bp, sma_val, 3, NULL);
3251 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
3252 on ? " ON" : "OFF", buf);
3253 }
3254
3255 if (bp->ts3) {
3256 ts_reg = bp->ts3->mem;
3257 on = ioread32(&ts_reg->enable);
3258 gpio_input_map(buf, bp, sma_val, 6, NULL);
3259 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
3260 on ? " ON" : "OFF", buf);
3261 }
3262
3263 if (bp->ts4) {
3264 ts_reg = bp->ts4->mem;
3265 on = ioread32(&ts_reg->enable);
3266 gpio_input_map(buf, bp, sma_val, 7, NULL);
3267 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
3268 on ? " ON" : "OFF", buf);
3269 }
3270
3271 if (bp->pps) {
3272 ts_reg = bp->pps->mem;
3273 src = "PHC";
3274 on = ioread32(&ts_reg->enable);
3275 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
3276 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
3277 on && map ? " ON" : "OFF", src);
3278
3279 map = !!(bp->pps_req_map & OCP_REQ_PPS);
3280 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
3281 on && map ? " ON" : "OFF", src);
3282 }
3283
3284 if (bp->fw_cap & OCP_CAP_SIGNAL)
3285 for (i = 0; i < 4; i++)
3286 _signal_summary_show(s, bp, i);
3287
3288 if (bp->fw_cap & OCP_CAP_FREQ)
3289 for (i = 0; i < 4; i++)
3290 _frequency_summary_show(s, i, bp->freq_in[i]);
3291
3292 if (bp->irig_out) {
3293 ctrl = ioread32(&bp->irig_out->ctrl);
3294 on = ctrl & IRIG_M_CTRL_ENABLE;
3295 val = ioread32(&bp->irig_out->status);
3296 gpio_output_map(buf, bp, sma_val, 4);
3297 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
3298 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
3299 }
3300
3301 if (bp->irig_in) {
3302 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
3303 val = ioread32(&bp->irig_in->status);
3304 gpio_input_map(buf, bp, sma_val, 4, NULL);
3305 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
3306 on ? " ON" : "OFF", val, buf);
3307 }
3308
3309 if (bp->dcf_out) {
3310 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
3311 val = ioread32(&bp->dcf_out->status);
3312 gpio_output_map(buf, bp, sma_val, 5);
3313 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
3314 on ? " ON" : "OFF", val, buf);
3315 }
3316
3317 if (bp->dcf_in) {
3318 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
3319 val = ioread32(&bp->dcf_in->status);
3320 gpio_input_map(buf, bp, sma_val, 5, NULL);
3321 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
3322 on ? " ON" : "OFF", val, buf);
3323 }
3324
3325 if (bp->nmea_out) {
3326 on = ioread32(&bp->nmea_out->ctrl) & 1;
3327 val = ioread32(&bp->nmea_out->status);
3328 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
3329 on ? " ON" : "OFF", val);
3330 }
3331
3332 /* compute src for PPS1, used below. */
3333 if (bp->pps_select) {
3334 val = ioread32(&bp->pps_select->gpio1);
3335 src = &buf[80];
3336 mac_src = "GNSS1";
3337 if (val & 0x01) {
3338 gpio_input_map(src, bp, sma_val, 0, NULL);
3339 mac_src = src;
3340 } else if (val & 0x02) {
3341 src = "MAC";
3342 } else if (val & 0x04) {
3343 src = "GNSS1";
3344 } else {
3345 src = "----";
3346 mac_src = src;
3347 }
3348 } else {
3349 src = "?";
3350 mac_src = src;
3351 }
3352 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
3353
3354 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
3355 seq_printf(s, "MAC PPS2 src: %s\n", buf);
3356
3357 /* assumes automatic switchover/selection */
3358 val = ioread32(&bp->reg->select);
3359 switch (val >> 16) {
3360 case 0:
3361 sprintf(buf, "----");
3362 break;
3363 case 2:
3364 sprintf(buf, "IRIG");
3365 break;
3366 case 3:
3367 sprintf(buf, "%s via PPS1", src);
3368 break;
3369 case 6:
3370 sprintf(buf, "DCF");
3371 break;
3372 default:
3373 strcpy(buf, "unknown");
3374 break;
3375 }
3376 val = ioread32(&bp->reg->status);
3377 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
3378 val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced");
3379
3380 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
3381 struct timespec64 sys_ts;
3382 s64 pre_ns, post_ns, ns;
3383
3384 pre_ns = timespec64_to_ns(&sts.pre_ts);
3385 post_ns = timespec64_to_ns(&sts.post_ts);
3386 ns = (pre_ns + post_ns) / 2;
3387 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
3388 sys_ts = ns_to_timespec64(ns);
3389
3390 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
3391 ts.tv_sec, ts.tv_nsec, &ts);
3392 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
3393 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
3394 bp->utc_tai_offset);
3395 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
3396 timespec64_to_ns(&ts) - ns,
3397 post_ns - pre_ns);
3398 }
3399
3400 free_page((unsigned long)buf);
3401 return 0;
3402 }
3403 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
3404
3405 static int
ptp_ocp_tod_status_show(struct seq_file * s,void * data)3406 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
3407 {
3408 struct device *dev = s->private;
3409 struct ptp_ocp *bp;
3410 u32 val;
3411 int idx;
3412
3413 bp = dev_get_drvdata(dev);
3414
3415 val = ioread32(&bp->tod->ctrl);
3416 if (!(val & TOD_CTRL_ENABLE)) {
3417 seq_printf(s, "TOD Slave disabled\n");
3418 return 0;
3419 }
3420 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
3421
3422 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
3423 idx += (val >> 16) & 3;
3424 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
3425
3426 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
3427 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
3428
3429 val = ioread32(&bp->tod->version);
3430 seq_printf(s, "TOD Version %d.%d.%d\n",
3431 val >> 24, (val >> 16) & 0xff, val & 0xffff);
3432
3433 val = ioread32(&bp->tod->status);
3434 seq_printf(s, "Status register: 0x%08X\n", val);
3435
3436 val = ioread32(&bp->tod->adj_sec);
3437 idx = (val & ~INT_MAX) ? -1 : 1;
3438 idx *= (val & INT_MAX);
3439 seq_printf(s, "Correction seconds: %d\n", idx);
3440
3441 val = ioread32(&bp->tod->utc_status);
3442 seq_printf(s, "UTC status register: 0x%08X\n", val);
3443 seq_printf(s, "UTC offset: %d valid:%d\n",
3444 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
3445 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
3446 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
3447 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
3448
3449 val = ioread32(&bp->tod->leap);
3450 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
3451
3452 return 0;
3453 }
3454 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
3455
3456 static struct dentry *ptp_ocp_debugfs_root;
3457
3458 static void
ptp_ocp_debugfs_add_device(struct ptp_ocp * bp)3459 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
3460 {
3461 struct dentry *d;
3462
3463 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
3464 bp->debug_root = d;
3465 debugfs_create_file("summary", 0444, bp->debug_root,
3466 &bp->dev, &ptp_ocp_summary_fops);
3467 if (bp->tod)
3468 debugfs_create_file("tod_status", 0444, bp->debug_root,
3469 &bp->dev, &ptp_ocp_tod_status_fops);
3470 }
3471
3472 static void
ptp_ocp_debugfs_remove_device(struct ptp_ocp * bp)3473 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
3474 {
3475 debugfs_remove_recursive(bp->debug_root);
3476 }
3477
3478 static void
ptp_ocp_debugfs_init(void)3479 ptp_ocp_debugfs_init(void)
3480 {
3481 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
3482 }
3483
3484 static void
ptp_ocp_debugfs_fini(void)3485 ptp_ocp_debugfs_fini(void)
3486 {
3487 debugfs_remove_recursive(ptp_ocp_debugfs_root);
3488 }
3489
3490 static void
ptp_ocp_dev_release(struct device * dev)3491 ptp_ocp_dev_release(struct device *dev)
3492 {
3493 struct ptp_ocp *bp = dev_get_drvdata(dev);
3494
3495 mutex_lock(&ptp_ocp_lock);
3496 idr_remove(&ptp_ocp_idr, bp->id);
3497 mutex_unlock(&ptp_ocp_lock);
3498 }
3499
3500 static int
ptp_ocp_device_init(struct ptp_ocp * bp,struct pci_dev * pdev)3501 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
3502 {
3503 int err;
3504
3505 mutex_lock(&ptp_ocp_lock);
3506 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
3507 mutex_unlock(&ptp_ocp_lock);
3508 if (err < 0) {
3509 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
3510 return err;
3511 }
3512 bp->id = err;
3513
3514 bp->ptp_info = ptp_ocp_clock_info;
3515 spin_lock_init(&bp->lock);
3516 bp->gnss_port = -1;
3517 bp->gnss2_port = -1;
3518 bp->mac_port = -1;
3519 bp->nmea_port = -1;
3520 bp->pdev = pdev;
3521
3522 device_initialize(&bp->dev);
3523 dev_set_name(&bp->dev, "ocp%d", bp->id);
3524 bp->dev.class = &timecard_class;
3525 bp->dev.parent = &pdev->dev;
3526 bp->dev.release = ptp_ocp_dev_release;
3527 dev_set_drvdata(&bp->dev, bp);
3528
3529 err = device_add(&bp->dev);
3530 if (err) {
3531 dev_err(&bp->dev, "device add failed: %d\n", err);
3532 goto out;
3533 }
3534
3535 pci_set_drvdata(pdev, bp);
3536
3537 return 0;
3538
3539 out:
3540 ptp_ocp_dev_release(&bp->dev);
3541 put_device(&bp->dev);
3542 return err;
3543 }
3544
3545 static void
ptp_ocp_symlink(struct ptp_ocp * bp,struct device * child,const char * link)3546 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
3547 {
3548 struct device *dev = &bp->dev;
3549
3550 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
3551 dev_err(dev, "%s symlink failed\n", link);
3552 }
3553
3554 static void
ptp_ocp_link_child(struct ptp_ocp * bp,const char * name,const char * link)3555 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
3556 {
3557 struct device *dev, *child;
3558
3559 dev = &bp->pdev->dev;
3560
3561 child = device_find_child_by_name(dev, name);
3562 if (!child) {
3563 dev_err(dev, "Could not find device %s\n", name);
3564 return;
3565 }
3566
3567 ptp_ocp_symlink(bp, child, link);
3568 put_device(child);
3569 }
3570
3571 static int
ptp_ocp_complete(struct ptp_ocp * bp)3572 ptp_ocp_complete(struct ptp_ocp *bp)
3573 {
3574 struct pps_device *pps;
3575 char buf[32];
3576
3577 if (bp->gnss_port != -1) {
3578 sprintf(buf, "ttyS%d", bp->gnss_port);
3579 ptp_ocp_link_child(bp, buf, "ttyGNSS");
3580 }
3581 if (bp->gnss2_port != -1) {
3582 sprintf(buf, "ttyS%d", bp->gnss2_port);
3583 ptp_ocp_link_child(bp, buf, "ttyGNSS2");
3584 }
3585 if (bp->mac_port != -1) {
3586 sprintf(buf, "ttyS%d", bp->mac_port);
3587 ptp_ocp_link_child(bp, buf, "ttyMAC");
3588 }
3589 if (bp->nmea_port != -1) {
3590 sprintf(buf, "ttyS%d", bp->nmea_port);
3591 ptp_ocp_link_child(bp, buf, "ttyNMEA");
3592 }
3593 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
3594 ptp_ocp_link_child(bp, buf, "ptp");
3595
3596 pps = pps_lookup_dev(bp->ptp);
3597 if (pps)
3598 ptp_ocp_symlink(bp, pps->dev, "pps");
3599
3600 ptp_ocp_debugfs_add_device(bp);
3601
3602 return 0;
3603 }
3604
3605 static void
ptp_ocp_phc_info(struct ptp_ocp * bp)3606 ptp_ocp_phc_info(struct ptp_ocp *bp)
3607 {
3608 struct timespec64 ts;
3609 u32 version, select;
3610 bool sync;
3611
3612 version = ioread32(&bp->reg->version);
3613 select = ioread32(&bp->reg->select);
3614 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
3615 version >> 24, (version >> 16) & 0xff, version & 0xffff,
3616 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
3617 ptp_clock_index(bp->ptp));
3618
3619 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
3620 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
3621 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
3622 ts.tv_sec, ts.tv_nsec,
3623 sync ? "in-sync" : "UNSYNCED");
3624 }
3625
3626 static void
ptp_ocp_serial_info(struct device * dev,const char * name,int port,int baud)3627 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
3628 {
3629 if (port != -1)
3630 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
3631 }
3632
3633 static void
ptp_ocp_info(struct ptp_ocp * bp)3634 ptp_ocp_info(struct ptp_ocp *bp)
3635 {
3636 static int nmea_baud[] = {
3637 1200, 2400, 4800, 9600, 19200, 38400,
3638 57600, 115200, 230400, 460800, 921600,
3639 1000000, 2000000
3640 };
3641 struct device *dev = &bp->pdev->dev;
3642 u32 reg;
3643
3644 ptp_ocp_phc_info(bp);
3645
3646 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port, 115200);
3647 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port, 115200);
3648 ptp_ocp_serial_info(dev, "MAC", bp->mac_port, 57600);
3649 if (bp->nmea_out && bp->nmea_port != -1) {
3650 int baud = -1;
3651
3652 reg = ioread32(&bp->nmea_out->uart_baud);
3653 if (reg < ARRAY_SIZE(nmea_baud))
3654 baud = nmea_baud[reg];
3655 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port, baud);
3656 }
3657 }
3658
3659 static void
ptp_ocp_detach_sysfs(struct ptp_ocp * bp)3660 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
3661 {
3662 struct device *dev = &bp->dev;
3663
3664 sysfs_remove_link(&dev->kobj, "ttyGNSS");
3665 sysfs_remove_link(&dev->kobj, "ttyMAC");
3666 sysfs_remove_link(&dev->kobj, "ptp");
3667 sysfs_remove_link(&dev->kobj, "pps");
3668 }
3669
3670 static void
ptp_ocp_detach(struct ptp_ocp * bp)3671 ptp_ocp_detach(struct ptp_ocp *bp)
3672 {
3673 int i;
3674
3675 ptp_ocp_debugfs_remove_device(bp);
3676 ptp_ocp_detach_sysfs(bp);
3677 ptp_ocp_attr_group_del(bp);
3678 if (timer_pending(&bp->watchdog))
3679 del_timer_sync(&bp->watchdog);
3680 if (bp->ts0)
3681 ptp_ocp_unregister_ext(bp->ts0);
3682 if (bp->ts1)
3683 ptp_ocp_unregister_ext(bp->ts1);
3684 if (bp->ts2)
3685 ptp_ocp_unregister_ext(bp->ts2);
3686 if (bp->ts3)
3687 ptp_ocp_unregister_ext(bp->ts3);
3688 if (bp->ts4)
3689 ptp_ocp_unregister_ext(bp->ts4);
3690 if (bp->pps)
3691 ptp_ocp_unregister_ext(bp->pps);
3692 for (i = 0; i < 4; i++)
3693 if (bp->signal_out[i])
3694 ptp_ocp_unregister_ext(bp->signal_out[i]);
3695 if (bp->gnss_port != -1)
3696 serial8250_unregister_port(bp->gnss_port);
3697 if (bp->gnss2_port != -1)
3698 serial8250_unregister_port(bp->gnss2_port);
3699 if (bp->mac_port != -1)
3700 serial8250_unregister_port(bp->mac_port);
3701 if (bp->nmea_port != -1)
3702 serial8250_unregister_port(bp->nmea_port);
3703 if (bp->spi_flash)
3704 platform_device_unregister(bp->spi_flash);
3705 if (bp->i2c_ctrl)
3706 platform_device_unregister(bp->i2c_ctrl);
3707 if (bp->i2c_clk)
3708 clk_hw_unregister_fixed_rate(bp->i2c_clk);
3709 if (bp->n_irqs)
3710 pci_free_irq_vectors(bp->pdev);
3711 if (bp->ptp)
3712 ptp_clock_unregister(bp->ptp);
3713 kfree(bp->ptp_info.pin_config);
3714 device_unregister(&bp->dev);
3715 }
3716
3717 static int
ptp_ocp_probe(struct pci_dev * pdev,const struct pci_device_id * id)3718 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3719 {
3720 struct devlink *devlink;
3721 struct ptp_ocp *bp;
3722 int err;
3723
3724 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
3725 if (!devlink) {
3726 dev_err(&pdev->dev, "devlink_alloc failed\n");
3727 return -ENOMEM;
3728 }
3729
3730 err = pci_enable_device(pdev);
3731 if (err) {
3732 dev_err(&pdev->dev, "pci_enable_device\n");
3733 goto out_free;
3734 }
3735
3736 bp = devlink_priv(devlink);
3737 err = ptp_ocp_device_init(bp, pdev);
3738 if (err)
3739 goto out_disable;
3740
3741 /* compat mode.
3742 * Older FPGA firmware only returns 2 irq's.
3743 * allow this - if not all of the IRQ's are returned, skip the
3744 * extra devices and just register the clock.
3745 */
3746 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
3747 if (err < 0) {
3748 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
3749 goto out;
3750 }
3751 bp->n_irqs = err;
3752 pci_set_master(pdev);
3753
3754 err = ptp_ocp_register_resources(bp, id->driver_data);
3755 if (err)
3756 goto out;
3757
3758 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
3759 if (IS_ERR(bp->ptp)) {
3760 err = PTR_ERR(bp->ptp);
3761 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
3762 bp->ptp = NULL;
3763 goto out;
3764 }
3765
3766 err = ptp_ocp_complete(bp);
3767 if (err)
3768 goto out;
3769
3770 ptp_ocp_info(bp);
3771 devlink_register(devlink);
3772 return 0;
3773
3774 out:
3775 ptp_ocp_detach(bp);
3776 pci_set_drvdata(pdev, NULL);
3777 out_disable:
3778 pci_disable_device(pdev);
3779 out_free:
3780 devlink_free(devlink);
3781 return err;
3782 }
3783
3784 static void
ptp_ocp_remove(struct pci_dev * pdev)3785 ptp_ocp_remove(struct pci_dev *pdev)
3786 {
3787 struct ptp_ocp *bp = pci_get_drvdata(pdev);
3788 struct devlink *devlink = priv_to_devlink(bp);
3789
3790 devlink_unregister(devlink);
3791 ptp_ocp_detach(bp);
3792 pci_set_drvdata(pdev, NULL);
3793 pci_disable_device(pdev);
3794
3795 devlink_free(devlink);
3796 }
3797
3798 static struct pci_driver ptp_ocp_driver = {
3799 .name = KBUILD_MODNAME,
3800 .id_table = ptp_ocp_pcidev_id,
3801 .probe = ptp_ocp_probe,
3802 .remove = ptp_ocp_remove,
3803 };
3804
3805 static int
ptp_ocp_i2c_notifier_call(struct notifier_block * nb,unsigned long action,void * data)3806 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
3807 unsigned long action, void *data)
3808 {
3809 struct device *dev, *child = data;
3810 struct ptp_ocp *bp;
3811 bool add;
3812
3813 switch (action) {
3814 case BUS_NOTIFY_ADD_DEVICE:
3815 case BUS_NOTIFY_DEL_DEVICE:
3816 add = action == BUS_NOTIFY_ADD_DEVICE;
3817 break;
3818 default:
3819 return 0;
3820 }
3821
3822 if (!i2c_verify_adapter(child))
3823 return 0;
3824
3825 dev = child;
3826 while ((dev = dev->parent))
3827 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
3828 goto found;
3829 return 0;
3830
3831 found:
3832 bp = dev_get_drvdata(dev);
3833 if (add)
3834 ptp_ocp_symlink(bp, child, "i2c");
3835 else
3836 sysfs_remove_link(&bp->dev.kobj, "i2c");
3837
3838 return 0;
3839 }
3840
3841 static struct notifier_block ptp_ocp_i2c_notifier = {
3842 .notifier_call = ptp_ocp_i2c_notifier_call,
3843 };
3844
3845 static int __init
ptp_ocp_init(void)3846 ptp_ocp_init(void)
3847 {
3848 const char *what;
3849 int err;
3850
3851 ptp_ocp_debugfs_init();
3852
3853 what = "timecard class";
3854 err = class_register(&timecard_class);
3855 if (err)
3856 goto out;
3857
3858 what = "i2c notifier";
3859 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
3860 if (err)
3861 goto out_notifier;
3862
3863 what = "ptp_ocp driver";
3864 err = pci_register_driver(&ptp_ocp_driver);
3865 if (err)
3866 goto out_register;
3867
3868 return 0;
3869
3870 out_register:
3871 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
3872 out_notifier:
3873 class_unregister(&timecard_class);
3874 out:
3875 ptp_ocp_debugfs_fini();
3876 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
3877 return err;
3878 }
3879
3880 static void __exit
ptp_ocp_fini(void)3881 ptp_ocp_fini(void)
3882 {
3883 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
3884 pci_unregister_driver(&ptp_ocp_driver);
3885 class_unregister(&timecard_class);
3886 ptp_ocp_debugfs_fini();
3887 }
3888
3889 module_init(ptp_ocp_init);
3890 module_exit(ptp_ocp_fini);
3891
3892 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
3893 MODULE_LICENSE("GPL v2");
3894