1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Freescale eSDHC i.MX controller driver for the platform bus.
4 *
5 * derived from the OF-version.
6 *
7 * Copyright (c) 2010 Pengutronix e.K.
8 * Author: Wolfram Sang <kernel@pengutronix.de>
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/io.h>
13 #include <linux/iopoll.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/module.h>
18 #include <linux/slab.h>
19 #include <linux/pm_qos.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/sdio.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/pm_runtime.h>
28 #include "sdhci-pltfm.h"
29 #include "sdhci-esdhc.h"
30 #include "cqhci.h"
31
32 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
33 #define ESDHC_CTRL_D3CD 0x08
34 #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
35 /* VENDOR SPEC register */
36 #define ESDHC_VENDOR_SPEC 0xc0
37 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
38 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
39 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
40 #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2
41 #define ESDHC_DEBUG_SEL_REG 0xc3
42 #define ESDHC_DEBUG_SEL_MASK 0xf
43 #define ESDHC_DEBUG_SEL_CMD_STATE 1
44 #define ESDHC_DEBUG_SEL_DATA_STATE 2
45 #define ESDHC_DEBUG_SEL_TRANS_STATE 3
46 #define ESDHC_DEBUG_SEL_DMA_STATE 4
47 #define ESDHC_DEBUG_SEL_ADMA_STATE 5
48 #define ESDHC_DEBUG_SEL_FIFO_STATE 6
49 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7
50 #define ESDHC_WTMK_LVL 0x44
51 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
52 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
53 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
54 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
55 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
56 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64
57 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128
58 #define ESDHC_MIX_CTRL 0x48
59 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
60 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
61 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
62 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
63 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
64 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
65 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
66 #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
67 /* Bits 3 and 6 are not SDHCI standard definitions */
68 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
69 /* Tuning bits */
70 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
71
72 /* dll control register */
73 #define ESDHC_DLL_CTRL 0x60
74 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
75 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
76
77 /* tune control register */
78 #define ESDHC_TUNE_CTRL_STATUS 0x68
79 #define ESDHC_TUNE_CTRL_STEP 1
80 #define ESDHC_TUNE_CTRL_MIN 0
81 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
82
83 /* strobe dll register */
84 #define ESDHC_STROBE_DLL_CTRL 0x70
85 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
86 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
87 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
89 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
90
91 #define ESDHC_STROBE_DLL_STATUS 0x74
92 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
93 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
94
95 #define ESDHC_VEND_SPEC2 0xc8
96 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
97 #define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN (1 << 4)
98 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN (0 << 4)
99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN (2 << 4)
100 #define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN (1 << 6)
101 #define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK (7 << 4)
102
103 #define ESDHC_TUNING_CTRL 0xcc
104 #define ESDHC_STD_TUNING_EN (1 << 24)
105 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
106 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
107 #define ESDHC_TUNING_START_TAP_MASK 0x7f
108 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7)
109 #define ESDHC_TUNING_STEP_MASK 0x00070000
110 #define ESDHC_TUNING_STEP_SHIFT 16
111
112 /* pinctrl state */
113 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
114 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
115
116 /*
117 * Our interpretation of the SDHCI_HOST_CONTROL register
118 */
119 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
120 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
121 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
122 #define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK)
123
124 /*
125 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
126 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
127 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
128 * Define this macro DMA error INT for fsl eSDHC
129 */
130 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
131
132 /* the address offset of CQHCI */
133 #define ESDHC_CQHCI_ADDR_OFFSET 0x100
134
135 /*
136 * The CMDTYPE of the CMD register (offset 0xE) should be set to
137 * "11" when the STOP CMD12 is issued on imx53 to abort one
138 * open ended multi-blk IO. Otherwise the TC INT wouldn't
139 * be generated.
140 * In exact block transfer, the controller doesn't complete the
141 * operations automatically as required at the end of the
142 * transfer and remains on hold if the abort command is not sent.
143 * As a result, the TC flag is not asserted and SW received timeout
144 * exception. Bit1 of Vendor Spec register is used to fix it.
145 */
146 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
147 /*
148 * The flag tells that the ESDHC controller is an USDHC block that is
149 * integrated on the i.MX6 series.
150 */
151 #define ESDHC_FLAG_USDHC BIT(3)
152 /* The IP supports manual tuning process */
153 #define ESDHC_FLAG_MAN_TUNING BIT(4)
154 /* The IP supports standard tuning process */
155 #define ESDHC_FLAG_STD_TUNING BIT(5)
156 /* The IP has SDHCI_CAPABILITIES_1 register */
157 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
158 /*
159 * The IP has erratum ERR004536
160 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
161 * when reading data from the card
162 * This flag is also set for i.MX25 and i.MX35 in order to get
163 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
164 */
165 #define ESDHC_FLAG_ERR004536 BIT(7)
166 /* The IP supports HS200 mode */
167 #define ESDHC_FLAG_HS200 BIT(8)
168 /* The IP supports HS400 mode */
169 #define ESDHC_FLAG_HS400 BIT(9)
170 /*
171 * The IP has errata ERR010450
172 * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
173 * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
174 */
175 #define ESDHC_FLAG_ERR010450 BIT(10)
176 /* The IP supports HS400ES mode */
177 #define ESDHC_FLAG_HS400_ES BIT(11)
178 /* The IP has Host Controller Interface for Command Queuing */
179 #define ESDHC_FLAG_CQHCI BIT(12)
180 /* need request pmqos during low power */
181 #define ESDHC_FLAG_PMQOS BIT(13)
182 /* The IP state got lost in low power mode */
183 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14)
184 /* The IP lost clock rate in PM_RUNTIME */
185 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15)
186 /*
187 * The IP do not support the ACMD23 feature completely when use ADMA mode.
188 * In ADMA mode, it only use the 16 bit block count of the register 0x4
189 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
190 * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
191 * write operation in RPMB, because RPMB reliable write need to set the bit31
192 * of the CMD23's argument.
193 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
194 * do not has this limitation. so when these SoC use ADMA mode, it need to
195 * disable the ACMD23 feature.
196 */
197 #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
198
199 /* ERR004536 is not applicable for the IP */
200 #define ESDHC_FLAG_SKIP_ERR004536 BIT(17)
201
202 enum wp_types {
203 ESDHC_WP_NONE, /* no WP, neither controller nor gpio */
204 ESDHC_WP_CONTROLLER, /* mmc controller internal WP */
205 ESDHC_WP_GPIO, /* external gpio pin for WP */
206 };
207
208 enum cd_types {
209 ESDHC_CD_NONE, /* no CD, neither controller nor gpio */
210 ESDHC_CD_CONTROLLER, /* mmc controller internal CD */
211 ESDHC_CD_GPIO, /* external gpio pin for CD */
212 ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */
213 };
214
215 /*
216 * struct esdhc_platform_data - platform data for esdhc on i.MX
217 *
218 * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
219 *
220 * @wp_type: type of write_protect method (see wp_types enum above)
221 * @cd_type: type of card_detect method (see cd_types enum above)
222 */
223
224 struct esdhc_platform_data {
225 enum wp_types wp_type;
226 enum cd_types cd_type;
227 int max_bus_width;
228 unsigned int delay_line;
229 unsigned int tuning_step; /* The delay cell steps in tuning procedure */
230 unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */
231 unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */
232 };
233
234 struct esdhc_soc_data {
235 u32 flags;
236 };
237
238 static const struct esdhc_soc_data esdhc_imx25_data = {
239 .flags = ESDHC_FLAG_ERR004536,
240 };
241
242 static const struct esdhc_soc_data esdhc_imx35_data = {
243 .flags = ESDHC_FLAG_ERR004536,
244 };
245
246 static const struct esdhc_soc_data esdhc_imx51_data = {
247 .flags = 0,
248 };
249
250 static const struct esdhc_soc_data esdhc_imx53_data = {
251 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
252 };
253
254 static const struct esdhc_soc_data usdhc_imx6q_data = {
255 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
256 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
257 };
258
259 static const struct esdhc_soc_data usdhc_imx6sl_data = {
260 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
261 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
262 | ESDHC_FLAG_HS200
263 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
264 };
265
266 static const struct esdhc_soc_data usdhc_imx6sll_data = {
267 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
268 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
269 | ESDHC_FLAG_HS400
270 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
271 };
272
273 static const struct esdhc_soc_data usdhc_imx6sx_data = {
274 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
275 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
276 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
277 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
278 };
279
280 static const struct esdhc_soc_data usdhc_imx6ull_data = {
281 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
282 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
283 | ESDHC_FLAG_ERR010450
284 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
285 };
286
287 static const struct esdhc_soc_data usdhc_imx7d_data = {
288 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
289 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
290 | ESDHC_FLAG_HS400
291 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
292 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
293 };
294
295 static struct esdhc_soc_data usdhc_s32g2_data = {
296 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
297 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
298 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
299 | ESDHC_FLAG_SKIP_ERR004536,
300 };
301
302 static struct esdhc_soc_data usdhc_imx7ulp_data = {
303 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
304 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
305 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
306 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
307 };
308 static struct esdhc_soc_data usdhc_imxrt1050_data = {
309 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_HS200 | ESDHC_FLAG_ERR004536,
310 };
311
312 static struct esdhc_soc_data usdhc_imx8qxp_data = {
313 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
314 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
315 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
316 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
317 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
318 };
319
320 static struct esdhc_soc_data usdhc_imx8mm_data = {
321 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
322 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
323 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
324 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
325 };
326
327 struct pltfm_imx_data {
328 u32 scratchpad;
329 struct pinctrl *pinctrl;
330 struct pinctrl_state *pins_100mhz;
331 struct pinctrl_state *pins_200mhz;
332 const struct esdhc_soc_data *socdata;
333 struct esdhc_platform_data boarddata;
334 struct clk *clk_ipg;
335 struct clk *clk_ahb;
336 struct clk *clk_per;
337 unsigned int actual_clock;
338 enum {
339 NO_CMD_PENDING, /* no multiblock command pending */
340 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
341 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
342 } multiblock_status;
343 u32 is_ddr;
344 struct pm_qos_request pm_qos_req;
345 };
346
347 static const struct of_device_id imx_esdhc_dt_ids[] = {
348 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
349 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
350 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
351 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
352 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
353 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
354 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
355 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
356 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
357 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
358 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
359 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
360 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
361 { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
362 { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
363 { /* sentinel */ }
364 };
365 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
366
is_imx25_esdhc(struct pltfm_imx_data * data)367 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
368 {
369 return data->socdata == &esdhc_imx25_data;
370 }
371
is_imx53_esdhc(struct pltfm_imx_data * data)372 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
373 {
374 return data->socdata == &esdhc_imx53_data;
375 }
376
esdhc_is_usdhc(struct pltfm_imx_data * data)377 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
378 {
379 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
380 }
381
esdhc_clrset_le(struct sdhci_host * host,u32 mask,u32 val,int reg)382 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
383 {
384 void __iomem *base = host->ioaddr + (reg & ~0x3);
385 u32 shift = (reg & 0x3) * 8;
386
387 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
388 }
389
390 #define DRIVER_NAME "sdhci-esdhc-imx"
391 #define ESDHC_IMX_DUMP(f, x...) \
392 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
esdhc_dump_debug_regs(struct sdhci_host * host)393 static void esdhc_dump_debug_regs(struct sdhci_host *host)
394 {
395 int i;
396 char *debug_status[7] = {
397 "cmd debug status",
398 "data debug status",
399 "trans debug status",
400 "dma debug status",
401 "adma debug status",
402 "fifo debug status",
403 "async fifo debug status"
404 };
405
406 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
407 for (i = 0; i < 7; i++) {
408 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
409 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
410 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i],
411 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
412 }
413
414 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
415
416 }
417
esdhc_wait_for_card_clock_gate_off(struct sdhci_host * host)418 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
419 {
420 u32 present_state;
421 int ret;
422
423 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
424 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
425 if (ret == -ETIMEDOUT)
426 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
427 }
428
429 /* Enable the auto tuning circuit to check the CMD line and BUS line */
usdhc_auto_tuning_mode_sel(struct sdhci_host * host)430 static inline void usdhc_auto_tuning_mode_sel(struct sdhci_host *host)
431 {
432 u32 buswidth, auto_tune_buswidth;
433
434 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL));
435
436 switch (buswidth) {
437 case ESDHC_CTRL_8BITBUS:
438 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN;
439 break;
440 case ESDHC_CTRL_4BITBUS:
441 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN;
442 break;
443 default: /* 1BITBUS */
444 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
445 break;
446 }
447
448 esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK,
449 auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN,
450 ESDHC_VEND_SPEC2);
451 }
452
esdhc_readl_le(struct sdhci_host * host,int reg)453 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
454 {
455 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
456 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
457 u32 val = readl(host->ioaddr + reg);
458
459 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
460 u32 fsl_prss = val;
461 /* save the least 20 bits */
462 val = fsl_prss & 0x000FFFFF;
463 /* move dat[0-3] bits */
464 val |= (fsl_prss & 0x0F000000) >> 4;
465 /* move cmd line bit */
466 val |= (fsl_prss & 0x00800000) << 1;
467 }
468
469 if (unlikely(reg == SDHCI_CAPABILITIES)) {
470 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
471 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
472 val &= 0xffff0000;
473
474 /* In FSL esdhc IC module, only bit20 is used to indicate the
475 * ADMA2 capability of esdhc, but this bit is messed up on
476 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
477 * don't actually support ADMA2). So set the BROKEN_ADMA
478 * quirk on MX25/35 platforms.
479 */
480
481 if (val & SDHCI_CAN_DO_ADMA1) {
482 val &= ~SDHCI_CAN_DO_ADMA1;
483 val |= SDHCI_CAN_DO_ADMA2;
484 }
485 }
486
487 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
488 if (esdhc_is_usdhc(imx_data)) {
489 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
490 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
491 else
492 /* imx6q/dl does not have cap_1 register, fake one */
493 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
494 | SDHCI_SUPPORT_SDR50
495 | SDHCI_USE_SDR50_TUNING
496 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
497 SDHCI_TUNING_MODE_3);
498
499 /*
500 * Do not advertise faster UHS modes if there are no
501 * pinctrl states for 100MHz/200MHz.
502 */
503 if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
504 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
505 if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
506 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
507 }
508 }
509
510 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
511 val = 0;
512 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
513 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
514 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
515 }
516
517 if (unlikely(reg == SDHCI_INT_STATUS)) {
518 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
519 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
520 val |= SDHCI_INT_ADMA_ERROR;
521 }
522
523 /*
524 * mask off the interrupt we get in response to the manually
525 * sent CMD12
526 */
527 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
528 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
529 val &= ~SDHCI_INT_RESPONSE;
530 writel(SDHCI_INT_RESPONSE, host->ioaddr +
531 SDHCI_INT_STATUS);
532 imx_data->multiblock_status = NO_CMD_PENDING;
533 }
534 }
535
536 return val;
537 }
538
esdhc_writel_le(struct sdhci_host * host,u32 val,int reg)539 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
540 {
541 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
542 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
543 u32 data;
544
545 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
546 reg == SDHCI_INT_STATUS)) {
547 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
548 /*
549 * Clear and then set D3CD bit to avoid missing the
550 * card interrupt. This is an eSDHC controller problem
551 * so we need to apply the following workaround: clear
552 * and set D3CD bit will make eSDHC re-sample the card
553 * interrupt. In case a card interrupt was lost,
554 * re-sample it by the following steps.
555 */
556 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
557 data &= ~ESDHC_CTRL_D3CD;
558 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
559 data |= ESDHC_CTRL_D3CD;
560 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
561 }
562
563 if (val & SDHCI_INT_ADMA_ERROR) {
564 val &= ~SDHCI_INT_ADMA_ERROR;
565 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
566 }
567 }
568
569 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
570 && (reg == SDHCI_INT_STATUS)
571 && (val & SDHCI_INT_DATA_END))) {
572 u32 v;
573 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
574 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
575 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
576
577 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
578 {
579 /* send a manual CMD12 with RESPTYP=none */
580 data = MMC_STOP_TRANSMISSION << 24 |
581 SDHCI_CMD_ABORTCMD << 16;
582 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
583 imx_data->multiblock_status = WAIT_FOR_INT;
584 }
585 }
586
587 writel(val, host->ioaddr + reg);
588 }
589
esdhc_readw_le(struct sdhci_host * host,int reg)590 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
591 {
592 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
593 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
594 u16 ret = 0;
595 u32 val;
596
597 if (unlikely(reg == SDHCI_HOST_VERSION)) {
598 reg ^= 2;
599 if (esdhc_is_usdhc(imx_data)) {
600 /*
601 * The usdhc register returns a wrong host version.
602 * Correct it here.
603 */
604 return SDHCI_SPEC_300;
605 }
606 }
607
608 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
609 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
610 if (val & ESDHC_VENDOR_SPEC_VSELECT)
611 ret |= SDHCI_CTRL_VDD_180;
612
613 if (esdhc_is_usdhc(imx_data)) {
614 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
615 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
616 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
617 /* the std tuning bits is in ACMD12_ERR for imx6sl */
618 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
619 }
620
621 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
622 ret |= SDHCI_CTRL_EXEC_TUNING;
623 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
624 ret |= SDHCI_CTRL_TUNED_CLK;
625
626 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
627
628 return ret;
629 }
630
631 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
632 if (esdhc_is_usdhc(imx_data)) {
633 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
634 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
635 /* Swap AC23 bit */
636 if (m & ESDHC_MIX_CTRL_AC23EN) {
637 ret &= ~ESDHC_MIX_CTRL_AC23EN;
638 ret |= SDHCI_TRNS_AUTO_CMD23;
639 }
640 } else {
641 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
642 }
643
644 return ret;
645 }
646
647 return readw(host->ioaddr + reg);
648 }
649
esdhc_writew_le(struct sdhci_host * host,u16 val,int reg)650 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
651 {
652 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
653 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
654 u32 new_val = 0;
655
656 switch (reg) {
657 case SDHCI_CLOCK_CONTROL:
658 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
659 if (val & SDHCI_CLOCK_CARD_EN)
660 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
661 else
662 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
663 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
664 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
665 esdhc_wait_for_card_clock_gate_off(host);
666 return;
667 case SDHCI_HOST_CONTROL2:
668 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
669 if (val & SDHCI_CTRL_VDD_180)
670 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
671 else
672 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
673 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
674 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
675 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
676 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
677 if (val & SDHCI_CTRL_TUNED_CLK) {
678 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
679 } else {
680 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
681 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
682 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
683 }
684
685 if (val & SDHCI_CTRL_EXEC_TUNING) {
686 v |= ESDHC_MIX_CTRL_EXE_TUNE;
687 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
688 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
689 usdhc_auto_tuning_mode_sel(host);
690 } else {
691 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
692 }
693
694 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
695 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
696 }
697 return;
698 case SDHCI_TRANSFER_MODE:
699 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
700 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
701 && (host->cmd->data->blocks > 1)
702 && (host->cmd->data->flags & MMC_DATA_READ)) {
703 u32 v;
704 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
705 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
706 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
707 }
708
709 if (esdhc_is_usdhc(imx_data)) {
710 u32 wml;
711 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
712 /* Swap AC23 bit */
713 if (val & SDHCI_TRNS_AUTO_CMD23) {
714 val &= ~SDHCI_TRNS_AUTO_CMD23;
715 val |= ESDHC_MIX_CTRL_AC23EN;
716 }
717 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
718 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
719
720 /* Set watermark levels for PIO access to maximum value
721 * (128 words) to accommodate full 512 bytes buffer.
722 * For DMA access restore the levels to default value.
723 */
724 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
725 if (val & SDHCI_TRNS_DMA) {
726 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
727 } else {
728 u8 ctrl;
729 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
730
731 /*
732 * Since already disable DMA mode, so also need
733 * to clear the DMASEL. Otherwise, for standard
734 * tuning, when send tuning command, usdhc will
735 * still prefetch the ADMA script from wrong
736 * DMA address, then we will see IOMMU report
737 * some error which show lack of TLB mapping.
738 */
739 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
740 ctrl &= ~SDHCI_CTRL_DMA_MASK;
741 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
742 }
743 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
744 ESDHC_WTMK_LVL_WR_WML_MASK);
745 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
746 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
747 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
748 } else {
749 /*
750 * Postpone this write, we must do it together with a
751 * command write that is down below.
752 */
753 imx_data->scratchpad = val;
754 }
755 return;
756 case SDHCI_COMMAND:
757 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
758 val |= SDHCI_CMD_ABORTCMD;
759
760 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
761 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
762 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
763
764 if (esdhc_is_usdhc(imx_data))
765 writel(val << 16,
766 host->ioaddr + SDHCI_TRANSFER_MODE);
767 else
768 writel(val << 16 | imx_data->scratchpad,
769 host->ioaddr + SDHCI_TRANSFER_MODE);
770 return;
771 case SDHCI_BLOCK_SIZE:
772 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
773 break;
774 }
775 esdhc_clrset_le(host, 0xffff, val, reg);
776 }
777
esdhc_readb_le(struct sdhci_host * host,int reg)778 static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
779 {
780 u8 ret;
781 u32 val;
782
783 switch (reg) {
784 case SDHCI_HOST_CONTROL:
785 val = readl(host->ioaddr + reg);
786
787 ret = val & SDHCI_CTRL_LED;
788 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
789 ret |= (val & ESDHC_CTRL_4BITBUS);
790 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
791 return ret;
792 }
793
794 return readb(host->ioaddr + reg);
795 }
796
esdhc_writeb_le(struct sdhci_host * host,u8 val,int reg)797 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
798 {
799 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
800 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
801 u32 new_val = 0;
802 u32 mask;
803
804 switch (reg) {
805 case SDHCI_POWER_CONTROL:
806 /*
807 * FSL put some DMA bits here
808 * If your board has a regulator, code should be here
809 */
810 return;
811 case SDHCI_HOST_CONTROL:
812 /* FSL messed up here, so we need to manually compose it. */
813 new_val = val & SDHCI_CTRL_LED;
814 /* ensure the endianness */
815 new_val |= ESDHC_HOST_CONTROL_LE;
816 /* bits 8&9 are reserved on mx25 */
817 if (!is_imx25_esdhc(imx_data)) {
818 /* DMA mode bits are shifted */
819 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
820 }
821
822 /*
823 * Do not touch buswidth bits here. This is done in
824 * esdhc_pltfm_bus_width.
825 * Do not touch the D3CD bit either which is used for the
826 * SDIO interrupt erratum workaround.
827 */
828 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
829
830 esdhc_clrset_le(host, mask, new_val, reg);
831 return;
832 case SDHCI_SOFTWARE_RESET:
833 if (val & SDHCI_RESET_DATA)
834 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
835 break;
836 }
837 esdhc_clrset_le(host, 0xff, val, reg);
838
839 if (reg == SDHCI_SOFTWARE_RESET) {
840 if (val & SDHCI_RESET_ALL) {
841 /*
842 * The esdhc has a design violation to SDHC spec which
843 * tells that software reset should not affect card
844 * detection circuit. But esdhc clears its SYSCTL
845 * register bits [0..2] during the software reset. This
846 * will stop those clocks that card detection circuit
847 * relies on. To work around it, we turn the clocks on
848 * back to keep card detection circuit functional.
849 */
850 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
851 /*
852 * The reset on usdhc fails to clear MIX_CTRL register.
853 * Do it manually here.
854 */
855 if (esdhc_is_usdhc(imx_data)) {
856 /*
857 * the tuning bits should be kept during reset
858 */
859 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
860 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
861 host->ioaddr + ESDHC_MIX_CTRL);
862 imx_data->is_ddr = 0;
863 }
864 } else if (val & SDHCI_RESET_DATA) {
865 /*
866 * The eSDHC DAT line software reset clears at least the
867 * data transfer width on i.MX25, so make sure that the
868 * Host Control register is unaffected.
869 */
870 esdhc_clrset_le(host, 0xff, new_val,
871 SDHCI_HOST_CONTROL);
872 }
873 }
874 }
875
esdhc_pltfm_get_max_clock(struct sdhci_host * host)876 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
877 {
878 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
879
880 return pltfm_host->clock;
881 }
882
esdhc_pltfm_get_min_clock(struct sdhci_host * host)883 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
884 {
885 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
886
887 return pltfm_host->clock / 256 / 16;
888 }
889
esdhc_pltfm_set_clock(struct sdhci_host * host,unsigned int clock)890 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
891 unsigned int clock)
892 {
893 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
894 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
895 unsigned int host_clock = pltfm_host->clock;
896 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
897 int pre_div = 1;
898 int div = 1;
899 int ret;
900 u32 temp, val;
901
902 if (esdhc_is_usdhc(imx_data)) {
903 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
904 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
905 host->ioaddr + ESDHC_VENDOR_SPEC);
906 esdhc_wait_for_card_clock_gate_off(host);
907 }
908
909 if (clock == 0) {
910 host->mmc->actual_clock = 0;
911 return;
912 }
913
914 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
915 if (is_imx53_esdhc(imx_data)) {
916 /*
917 * According to the i.MX53 reference manual, if DLLCTRL[10] can
918 * be set, then the controller is eSDHCv3, else it is eSDHCv2.
919 */
920 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
921 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
922 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
923 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
924 if (temp & BIT(10))
925 pre_div = 2;
926 }
927
928 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
929 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
930 | ESDHC_CLOCK_MASK);
931 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
932
933 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
934 unsigned int max_clock;
935
936 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
937
938 clock = min(clock, max_clock);
939 }
940
941 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
942 pre_div < 256)
943 pre_div *= 2;
944
945 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
946 div++;
947
948 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
949 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
950 clock, host->mmc->actual_clock);
951
952 pre_div >>= 1;
953 div--;
954
955 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
956 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
957 | (div << ESDHC_DIVIDER_SHIFT)
958 | (pre_div << ESDHC_PREDIV_SHIFT));
959 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
960
961 /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
962 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
963 (temp & ESDHC_CLOCK_STABLE), 2, 100);
964 if (ret == -ETIMEDOUT)
965 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
966
967 if (esdhc_is_usdhc(imx_data)) {
968 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
969 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
970 host->ioaddr + ESDHC_VENDOR_SPEC);
971 }
972
973 }
974
esdhc_pltfm_get_ro(struct sdhci_host * host)975 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
976 {
977 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
978 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
979 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
980
981 switch (boarddata->wp_type) {
982 case ESDHC_WP_GPIO:
983 return mmc_gpio_get_ro(host->mmc);
984 case ESDHC_WP_CONTROLLER:
985 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
986 SDHCI_WRITE_PROTECT);
987 case ESDHC_WP_NONE:
988 break;
989 }
990
991 return -ENOSYS;
992 }
993
esdhc_pltfm_set_bus_width(struct sdhci_host * host,int width)994 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
995 {
996 u32 ctrl;
997
998 switch (width) {
999 case MMC_BUS_WIDTH_8:
1000 ctrl = ESDHC_CTRL_8BITBUS;
1001 break;
1002 case MMC_BUS_WIDTH_4:
1003 ctrl = ESDHC_CTRL_4BITBUS;
1004 break;
1005 default:
1006 ctrl = 0;
1007 break;
1008 }
1009
1010 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
1011 SDHCI_HOST_CONTROL);
1012 }
1013
usdhc_execute_tuning(struct mmc_host * mmc,u32 opcode)1014 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1015 {
1016 struct sdhci_host *host = mmc_priv(mmc);
1017
1018 /*
1019 * i.MX uSDHC internally already uses a fixed optimized timing for
1020 * DDR50, normally does not require tuning for DDR50 mode.
1021 */
1022 if (host->timing == MMC_TIMING_UHS_DDR50)
1023 return 0;
1024
1025 return sdhci_execute_tuning(mmc, opcode);
1026 }
1027
esdhc_prepare_tuning(struct sdhci_host * host,u32 val)1028 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
1029 {
1030 u32 reg;
1031 u8 sw_rst;
1032 int ret;
1033
1034 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
1035 mdelay(1);
1036
1037 /* IC suggest to reset USDHC before every tuning command */
1038 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
1039 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
1040 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
1041 if (ret == -ETIMEDOUT)
1042 dev_warn(mmc_dev(host->mmc),
1043 "warning! RESET_ALL never complete before sending tuning command\n");
1044
1045 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1046 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
1047 ESDHC_MIX_CTRL_FBCLK_SEL;
1048 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1049 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1050 dev_dbg(mmc_dev(host->mmc),
1051 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
1052 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
1053 }
1054
esdhc_post_tuning(struct sdhci_host * host)1055 static void esdhc_post_tuning(struct sdhci_host *host)
1056 {
1057 u32 reg;
1058
1059 usdhc_auto_tuning_mode_sel(host);
1060
1061 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1062 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1063 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1064 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1065 }
1066
esdhc_executing_tuning(struct sdhci_host * host,u32 opcode)1067 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1068 {
1069 int min, max, avg, ret;
1070
1071 /* find the mininum delay first which can pass tuning */
1072 min = ESDHC_TUNE_CTRL_MIN;
1073 while (min < ESDHC_TUNE_CTRL_MAX) {
1074 esdhc_prepare_tuning(host, min);
1075 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1076 break;
1077 min += ESDHC_TUNE_CTRL_STEP;
1078 }
1079
1080 /* find the maxinum delay which can not pass tuning */
1081 max = min + ESDHC_TUNE_CTRL_STEP;
1082 while (max < ESDHC_TUNE_CTRL_MAX) {
1083 esdhc_prepare_tuning(host, max);
1084 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1085 max -= ESDHC_TUNE_CTRL_STEP;
1086 break;
1087 }
1088 max += ESDHC_TUNE_CTRL_STEP;
1089 }
1090
1091 /* use average delay to get the best timing */
1092 avg = (min + max) / 2;
1093 esdhc_prepare_tuning(host, avg);
1094 ret = mmc_send_tuning(host->mmc, opcode, NULL);
1095 esdhc_post_tuning(host);
1096
1097 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1098 ret ? "failed" : "passed", avg, ret);
1099
1100 return ret;
1101 }
1102
esdhc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)1103 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1104 {
1105 struct sdhci_host *host = mmc_priv(mmc);
1106 u32 m;
1107
1108 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1109 if (ios->enhanced_strobe)
1110 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1111 else
1112 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1113 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1114 }
1115
esdhc_change_pinstate(struct sdhci_host * host,unsigned int uhs)1116 static int esdhc_change_pinstate(struct sdhci_host *host,
1117 unsigned int uhs)
1118 {
1119 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1120 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1121 struct pinctrl_state *pinctrl;
1122
1123 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1124
1125 if (IS_ERR(imx_data->pinctrl) ||
1126 IS_ERR(imx_data->pins_100mhz) ||
1127 IS_ERR(imx_data->pins_200mhz))
1128 return -EINVAL;
1129
1130 switch (uhs) {
1131 case MMC_TIMING_UHS_SDR50:
1132 case MMC_TIMING_UHS_DDR50:
1133 pinctrl = imx_data->pins_100mhz;
1134 break;
1135 case MMC_TIMING_UHS_SDR104:
1136 case MMC_TIMING_MMC_HS200:
1137 case MMC_TIMING_MMC_HS400:
1138 pinctrl = imx_data->pins_200mhz;
1139 break;
1140 default:
1141 /* back to default state for other legacy timing */
1142 return pinctrl_select_default_state(mmc_dev(host->mmc));
1143 }
1144
1145 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1146 }
1147
1148 /*
1149 * For HS400 eMMC, there is a data_strobe line. This signal is generated
1150 * by the device and used for data output and CRC status response output
1151 * in HS400 mode. The frequency of this signal follows the frequency of
1152 * CLK generated by host. The host receives the data which is aligned to the
1153 * edge of data_strobe line. Due to the time delay between CLK line and
1154 * data_strobe line, if the delay time is larger than one clock cycle,
1155 * then CLK and data_strobe line will be misaligned, read error shows up.
1156 */
esdhc_set_strobe_dll(struct sdhci_host * host)1157 static void esdhc_set_strobe_dll(struct sdhci_host *host)
1158 {
1159 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1160 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1161 u32 strobe_delay;
1162 u32 v;
1163 int ret;
1164
1165 /* disable clock before enabling strobe dll */
1166 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1167 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1168 host->ioaddr + ESDHC_VENDOR_SPEC);
1169 esdhc_wait_for_card_clock_gate_off(host);
1170
1171 /* force a reset on strobe dll */
1172 writel(ESDHC_STROBE_DLL_CTRL_RESET,
1173 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1174 /* clear the reset bit on strobe dll before any setting */
1175 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1176
1177 /*
1178 * enable strobe dll ctrl and adjust the delay target
1179 * for the uSDHC loopback read clock
1180 */
1181 if (imx_data->boarddata.strobe_dll_delay_target)
1182 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1183 else
1184 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1185 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1186 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1187 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1188 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1189
1190 /* wait max 50us to get the REF/SLV lock */
1191 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1192 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1193 if (ret == -ETIMEDOUT)
1194 dev_warn(mmc_dev(host->mmc),
1195 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1196 }
1197
esdhc_reset_tuning(struct sdhci_host * host)1198 static void esdhc_reset_tuning(struct sdhci_host *host)
1199 {
1200 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1201 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1202 u32 ctrl;
1203 int ret;
1204
1205 /* Reset the tuning circuit */
1206 if (esdhc_is_usdhc(imx_data)) {
1207 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1208 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1209 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1210 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1211 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1212 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1213 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1214 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1215 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1216 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1217 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1218 /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
1219 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1220 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
1221 if (ret == -ETIMEDOUT)
1222 dev_warn(mmc_dev(host->mmc),
1223 "Warning! clear execute tuning bit failed\n");
1224 /*
1225 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
1226 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
1227 * will finally make sure the normal data transfer logic correct.
1228 */
1229 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1230 ctrl |= SDHCI_INT_DATA_AVAIL;
1231 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1232 }
1233 }
1234 }
1235
esdhc_set_uhs_signaling(struct sdhci_host * host,unsigned timing)1236 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1237 {
1238 u32 m;
1239 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1240 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1241 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1242
1243 /* disable ddr mode and disable HS400 mode */
1244 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1245 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1246 imx_data->is_ddr = 0;
1247
1248 switch (timing) {
1249 case MMC_TIMING_UHS_SDR12:
1250 case MMC_TIMING_UHS_SDR25:
1251 case MMC_TIMING_UHS_SDR50:
1252 case MMC_TIMING_UHS_SDR104:
1253 case MMC_TIMING_MMC_HS:
1254 case MMC_TIMING_MMC_HS200:
1255 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1256 break;
1257 case MMC_TIMING_UHS_DDR50:
1258 case MMC_TIMING_MMC_DDR52:
1259 m |= ESDHC_MIX_CTRL_DDREN;
1260 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1261 imx_data->is_ddr = 1;
1262 if (boarddata->delay_line) {
1263 u32 v;
1264 v = boarddata->delay_line <<
1265 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1266 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1267 if (is_imx53_esdhc(imx_data))
1268 v <<= 1;
1269 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1270 }
1271 break;
1272 case MMC_TIMING_MMC_HS400:
1273 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1274 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1275 imx_data->is_ddr = 1;
1276 /* update clock after enable DDR for strobe DLL lock */
1277 host->ops->set_clock(host, host->clock);
1278 esdhc_set_strobe_dll(host);
1279 break;
1280 case MMC_TIMING_LEGACY:
1281 default:
1282 esdhc_reset_tuning(host);
1283 break;
1284 }
1285
1286 esdhc_change_pinstate(host, timing);
1287 }
1288
esdhc_reset(struct sdhci_host * host,u8 mask)1289 static void esdhc_reset(struct sdhci_host *host, u8 mask)
1290 {
1291 sdhci_reset(host, mask);
1292
1293 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1294 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1295 }
1296
esdhc_get_max_timeout_count(struct sdhci_host * host)1297 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1298 {
1299 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1300 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1301
1302 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
1303 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1304 }
1305
esdhc_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)1306 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1307 {
1308 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1309 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1310
1311 /* use maximum timeout counter */
1312 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1313 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1314 SDHCI_TIMEOUT_CONTROL);
1315 }
1316
esdhc_cqhci_irq(struct sdhci_host * host,u32 intmask)1317 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1318 {
1319 int cmd_error = 0;
1320 int data_error = 0;
1321
1322 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1323 return intmask;
1324
1325 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1326
1327 return 0;
1328 }
1329
1330 static struct sdhci_ops sdhci_esdhc_ops = {
1331 .read_l = esdhc_readl_le,
1332 .read_w = esdhc_readw_le,
1333 .read_b = esdhc_readb_le,
1334 .write_l = esdhc_writel_le,
1335 .write_w = esdhc_writew_le,
1336 .write_b = esdhc_writeb_le,
1337 .set_clock = esdhc_pltfm_set_clock,
1338 .get_max_clock = esdhc_pltfm_get_max_clock,
1339 .get_min_clock = esdhc_pltfm_get_min_clock,
1340 .get_max_timeout_count = esdhc_get_max_timeout_count,
1341 .get_ro = esdhc_pltfm_get_ro,
1342 .set_timeout = esdhc_set_timeout,
1343 .set_bus_width = esdhc_pltfm_set_bus_width,
1344 .set_uhs_signaling = esdhc_set_uhs_signaling,
1345 .reset = esdhc_reset,
1346 .irq = esdhc_cqhci_irq,
1347 .dump_vendor_regs = esdhc_dump_debug_regs,
1348 };
1349
1350 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1351 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1352 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1353 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1354 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1355 .ops = &sdhci_esdhc_ops,
1356 };
1357
sdhci_esdhc_imx_hwinit(struct sdhci_host * host)1358 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1359 {
1360 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1361 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1362 struct cqhci_host *cq_host = host->mmc->cqe_private;
1363 int tmp;
1364
1365 if (esdhc_is_usdhc(imx_data)) {
1366 /*
1367 * The imx6q ROM code will change the default watermark
1368 * level setting to something insane. Change it back here.
1369 */
1370 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1371
1372 /*
1373 * ROM code will change the bit burst_length_enable setting
1374 * to zero if this usdhc is chosen to boot system. Change
1375 * it back here, otherwise it will impact the performance a
1376 * lot. This bit is used to enable/disable the burst length
1377 * for the external AHB2AXI bridge. It's useful especially
1378 * for INCR transfer because without burst length indicator,
1379 * the AHB2AXI bridge does not know the burst length in
1380 * advance. And without burst length indicator, AHB INCR
1381 * transfer can only be converted to singles on the AXI side.
1382 */
1383 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1384 | ESDHC_BURST_LEN_EN_INCR,
1385 host->ioaddr + SDHCI_HOST_CONTROL);
1386
1387 /*
1388 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1389 * TO1.1, it's harmless for MX6SL
1390 */
1391 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) {
1392 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1393 host->ioaddr + 0x6c);
1394 }
1395
1396 /* disable DLL_CTRL delay line settings */
1397 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1398
1399 /*
1400 * For the case of command with busy, if set the bit
1401 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
1402 * transfer complete interrupt when busy is deasserted.
1403 * When CQHCI use DCMD to send a CMD need R1b respons,
1404 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
1405 * otherwise DCMD will always meet timeout waiting for
1406 * hardware interrupt issue.
1407 */
1408 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1409 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1410 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1411 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1412
1413 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1414 }
1415
1416 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1417 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1418 tmp |= ESDHC_STD_TUNING_EN |
1419 ESDHC_TUNING_START_TAP_DEFAULT;
1420 if (imx_data->boarddata.tuning_start_tap) {
1421 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1422 tmp |= imx_data->boarddata.tuning_start_tap;
1423 }
1424
1425 if (imx_data->boarddata.tuning_step) {
1426 tmp &= ~ESDHC_TUNING_STEP_MASK;
1427 tmp |= imx_data->boarddata.tuning_step
1428 << ESDHC_TUNING_STEP_SHIFT;
1429 }
1430
1431 /* Disable the CMD CRC check for tuning, if not, need to
1432 * add some delay after every tuning command, because
1433 * hardware standard tuning logic will directly go to next
1434 * step once it detect the CMD CRC error, will not wait for
1435 * the card side to finally send out the tuning data, trigger
1436 * the buffer read ready interrupt immediately. If usdhc send
1437 * the next tuning command some eMMC card will stuck, can't
1438 * response, block the tuning procedure or the first command
1439 * after the whole tuning procedure always can't get any response.
1440 */
1441 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1442 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1443 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1444 /*
1445 * ESDHC_STD_TUNING_EN may be configed in bootloader
1446 * or ROM code, so clear this bit here to make sure
1447 * the manual tuning can work.
1448 */
1449 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1450 tmp &= ~ESDHC_STD_TUNING_EN;
1451 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1452 }
1453
1454 /*
1455 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
1456 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
1457 * the 1st linux configure power/clock for the 2nd Linux.
1458 *
1459 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
1460 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
1461 * After we clear the pending interrupt and halt CQCTL, issue gone.
1462 */
1463 if (cq_host) {
1464 tmp = cqhci_readl(cq_host, CQHCI_IS);
1465 cqhci_writel(cq_host, tmp, CQHCI_IS);
1466 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1467 }
1468 }
1469 }
1470
esdhc_cqe_enable(struct mmc_host * mmc)1471 static void esdhc_cqe_enable(struct mmc_host *mmc)
1472 {
1473 struct sdhci_host *host = mmc_priv(mmc);
1474 struct cqhci_host *cq_host = mmc->cqe_private;
1475 u32 reg;
1476 u16 mode;
1477 int count = 10;
1478
1479 /*
1480 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
1481 * the case after tuning, so ensure the buffer is drained.
1482 */
1483 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1484 while (reg & SDHCI_DATA_AVAILABLE) {
1485 sdhci_readl(host, SDHCI_BUFFER);
1486 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1487 if (count-- == 0) {
1488 dev_warn(mmc_dev(host->mmc),
1489 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1490 break;
1491 }
1492 mdelay(1);
1493 }
1494
1495 /*
1496 * Runtime resume will reset the entire host controller, which
1497 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
1498 * Here set DMAEN and BCEN when enable CMDQ.
1499 */
1500 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1501 if (host->flags & SDHCI_REQ_USE_DMA)
1502 mode |= SDHCI_TRNS_DMA;
1503 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1504 mode |= SDHCI_TRNS_BLK_CNT_EN;
1505 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1506
1507 /*
1508 * Though Runtime resume reset the entire host controller,
1509 * but do not impact the CQHCI side, need to clear the
1510 * HALT bit, avoid CQHCI stuck in the first request when
1511 * system resume back.
1512 */
1513 cqhci_writel(cq_host, 0, CQHCI_CTL);
1514 if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
1515 dev_err(mmc_dev(host->mmc),
1516 "failed to exit halt state when enable CQE\n");
1517
1518
1519 sdhci_cqe_enable(mmc);
1520 }
1521
esdhc_sdhci_dumpregs(struct mmc_host * mmc)1522 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1523 {
1524 sdhci_dumpregs(mmc_priv(mmc));
1525 }
1526
1527 static const struct cqhci_host_ops esdhc_cqhci_ops = {
1528 .enable = esdhc_cqe_enable,
1529 .disable = sdhci_cqe_disable,
1530 .dumpregs = esdhc_sdhci_dumpregs,
1531 };
1532
1533 static int
sdhci_esdhc_imx_probe_dt(struct platform_device * pdev,struct sdhci_host * host,struct pltfm_imx_data * imx_data)1534 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1535 struct sdhci_host *host,
1536 struct pltfm_imx_data *imx_data)
1537 {
1538 struct device_node *np = pdev->dev.of_node;
1539 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1540 int ret;
1541
1542 if (of_get_property(np, "fsl,wp-controller", NULL))
1543 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1544
1545 /*
1546 * If we have this property, then activate WP check.
1547 * Retrieveing and requesting the actual WP GPIO will happen
1548 * in the call to mmc_of_parse().
1549 */
1550 if (of_property_read_bool(np, "wp-gpios"))
1551 boarddata->wp_type = ESDHC_WP_GPIO;
1552
1553 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1554 of_property_read_u32(np, "fsl,tuning-start-tap",
1555 &boarddata->tuning_start_tap);
1556
1557 of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1558 &boarddata->strobe_dll_delay_target);
1559 if (of_find_property(np, "no-1-8-v", NULL))
1560 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1561
1562 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1563 boarddata->delay_line = 0;
1564
1565 mmc_of_parse_voltage(host->mmc, &host->ocr_mask);
1566
1567 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1568 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1569 ESDHC_PINCTRL_STATE_100MHZ);
1570 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1571 ESDHC_PINCTRL_STATE_200MHZ);
1572 }
1573
1574 /* call to generic mmc_of_parse to support additional capabilities */
1575 ret = mmc_of_parse(host->mmc);
1576 if (ret)
1577 return ret;
1578
1579 if (mmc_gpio_get_cd(host->mmc) >= 0)
1580 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1581
1582 return 0;
1583 }
1584
sdhci_esdhc_imx_probe(struct platform_device * pdev)1585 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1586 {
1587 struct sdhci_pltfm_host *pltfm_host;
1588 struct sdhci_host *host;
1589 struct cqhci_host *cq_host;
1590 int err;
1591 struct pltfm_imx_data *imx_data;
1592
1593 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1594 sizeof(*imx_data));
1595 if (IS_ERR(host))
1596 return PTR_ERR(host);
1597
1598 pltfm_host = sdhci_priv(host);
1599
1600 imx_data = sdhci_pltfm_priv(pltfm_host);
1601
1602 imx_data->socdata = device_get_match_data(&pdev->dev);
1603
1604 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1605 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1606
1607 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1608 if (IS_ERR(imx_data->clk_ipg)) {
1609 err = PTR_ERR(imx_data->clk_ipg);
1610 goto free_sdhci;
1611 }
1612
1613 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1614 if (IS_ERR(imx_data->clk_ahb)) {
1615 err = PTR_ERR(imx_data->clk_ahb);
1616 goto free_sdhci;
1617 }
1618
1619 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1620 if (IS_ERR(imx_data->clk_per)) {
1621 err = PTR_ERR(imx_data->clk_per);
1622 goto free_sdhci;
1623 }
1624
1625 pltfm_host->clk = imx_data->clk_per;
1626 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1627 err = clk_prepare_enable(imx_data->clk_per);
1628 if (err)
1629 goto free_sdhci;
1630 err = clk_prepare_enable(imx_data->clk_ipg);
1631 if (err)
1632 goto disable_per_clk;
1633 err = clk_prepare_enable(imx_data->clk_ahb);
1634 if (err)
1635 goto disable_ipg_clk;
1636
1637 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1638 if (IS_ERR(imx_data->pinctrl))
1639 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1640
1641 if (esdhc_is_usdhc(imx_data)) {
1642 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1643 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1644
1645 /* GPIO CD can be set as a wakeup source */
1646 host->mmc->caps |= MMC_CAP_CD_WAKE;
1647
1648 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1649 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1650
1651 /* clear tuning bits in case ROM has set it already */
1652 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1653 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1654 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1655
1656 /*
1657 * Link usdhc specific mmc_host_ops execute_tuning function,
1658 * to replace the standard one in sdhci_ops.
1659 */
1660 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1661 }
1662
1663 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1664 sdhci_esdhc_ops.platform_execute_tuning =
1665 esdhc_executing_tuning;
1666
1667 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1668 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1669
1670 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1671 host->mmc->caps2 |= MMC_CAP2_HS400;
1672
1673 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1674 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1675
1676 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1677 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1678 host->mmc_host_ops.hs400_enhanced_strobe =
1679 esdhc_hs400_enhanced_strobe;
1680 }
1681
1682 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1683 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1684 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1685 if (!cq_host) {
1686 err = -ENOMEM;
1687 goto disable_ahb_clk;
1688 }
1689
1690 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1691 cq_host->ops = &esdhc_cqhci_ops;
1692
1693 err = cqhci_init(cq_host, host->mmc, false);
1694 if (err)
1695 goto disable_ahb_clk;
1696 }
1697
1698 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1699 if (err)
1700 goto disable_ahb_clk;
1701
1702 sdhci_esdhc_imx_hwinit(host);
1703
1704 err = sdhci_add_host(host);
1705 if (err)
1706 goto disable_ahb_clk;
1707
1708 /*
1709 * Setup the wakeup capability here, let user to decide
1710 * whether need to enable this wakeup through sysfs interface.
1711 */
1712 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) &&
1713 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ))
1714 device_set_wakeup_capable(&pdev->dev, true);
1715
1716 pm_runtime_set_active(&pdev->dev);
1717 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1718 pm_runtime_use_autosuspend(&pdev->dev);
1719 pm_suspend_ignore_children(&pdev->dev, 1);
1720 pm_runtime_enable(&pdev->dev);
1721
1722 return 0;
1723
1724 disable_ahb_clk:
1725 clk_disable_unprepare(imx_data->clk_ahb);
1726 disable_ipg_clk:
1727 clk_disable_unprepare(imx_data->clk_ipg);
1728 disable_per_clk:
1729 clk_disable_unprepare(imx_data->clk_per);
1730 free_sdhci:
1731 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1732 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1733 sdhci_pltfm_free(pdev);
1734 return err;
1735 }
1736
sdhci_esdhc_imx_remove(struct platform_device * pdev)1737 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1738 {
1739 struct sdhci_host *host = platform_get_drvdata(pdev);
1740 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1741 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1742 int dead;
1743
1744 pm_runtime_get_sync(&pdev->dev);
1745 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1746 pm_runtime_disable(&pdev->dev);
1747 pm_runtime_put_noidle(&pdev->dev);
1748
1749 sdhci_remove_host(host, dead);
1750
1751 clk_disable_unprepare(imx_data->clk_per);
1752 clk_disable_unprepare(imx_data->clk_ipg);
1753 clk_disable_unprepare(imx_data->clk_ahb);
1754
1755 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1756 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1757
1758 sdhci_pltfm_free(pdev);
1759
1760 return 0;
1761 }
1762
1763 #ifdef CONFIG_PM_SLEEP
sdhci_esdhc_suspend(struct device * dev)1764 static int sdhci_esdhc_suspend(struct device *dev)
1765 {
1766 struct sdhci_host *host = dev_get_drvdata(dev);
1767 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1768 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1769 int ret;
1770
1771 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1772 ret = cqhci_suspend(host->mmc);
1773 if (ret)
1774 return ret;
1775 }
1776
1777 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1778 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1779 mmc_retune_timer_stop(host->mmc);
1780 mmc_retune_needed(host->mmc);
1781 }
1782
1783 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1784 mmc_retune_needed(host->mmc);
1785
1786 ret = sdhci_suspend_host(host);
1787 if (ret)
1788 return ret;
1789
1790 ret = pinctrl_pm_select_sleep_state(dev);
1791 if (ret)
1792 return ret;
1793
1794 ret = mmc_gpio_set_cd_wake(host->mmc, true);
1795
1796 return ret;
1797 }
1798
sdhci_esdhc_resume(struct device * dev)1799 static int sdhci_esdhc_resume(struct device *dev)
1800 {
1801 struct sdhci_host *host = dev_get_drvdata(dev);
1802 int ret;
1803
1804 ret = pinctrl_pm_select_default_state(dev);
1805 if (ret)
1806 return ret;
1807
1808 /* re-initialize hw state in case it's lost in low power mode */
1809 sdhci_esdhc_imx_hwinit(host);
1810
1811 ret = sdhci_resume_host(host);
1812 if (ret)
1813 return ret;
1814
1815 if (host->mmc->caps2 & MMC_CAP2_CQE)
1816 ret = cqhci_resume(host->mmc);
1817
1818 if (!ret)
1819 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1820
1821 return ret;
1822 }
1823 #endif
1824
1825 #ifdef CONFIG_PM
sdhci_esdhc_runtime_suspend(struct device * dev)1826 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1827 {
1828 struct sdhci_host *host = dev_get_drvdata(dev);
1829 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1830 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1831 int ret;
1832
1833 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1834 ret = cqhci_suspend(host->mmc);
1835 if (ret)
1836 return ret;
1837 }
1838
1839 ret = sdhci_runtime_suspend_host(host);
1840 if (ret)
1841 return ret;
1842
1843 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1844 mmc_retune_needed(host->mmc);
1845
1846 imx_data->actual_clock = host->mmc->actual_clock;
1847 esdhc_pltfm_set_clock(host, 0);
1848 clk_disable_unprepare(imx_data->clk_per);
1849 clk_disable_unprepare(imx_data->clk_ipg);
1850 clk_disable_unprepare(imx_data->clk_ahb);
1851
1852 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1853 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1854
1855 return ret;
1856 }
1857
sdhci_esdhc_runtime_resume(struct device * dev)1858 static int sdhci_esdhc_runtime_resume(struct device *dev)
1859 {
1860 struct sdhci_host *host = dev_get_drvdata(dev);
1861 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1862 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1863 int err;
1864
1865 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1866 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1867
1868 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1869 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1870
1871 err = clk_prepare_enable(imx_data->clk_ahb);
1872 if (err)
1873 goto remove_pm_qos_request;
1874
1875 err = clk_prepare_enable(imx_data->clk_per);
1876 if (err)
1877 goto disable_ahb_clk;
1878
1879 err = clk_prepare_enable(imx_data->clk_ipg);
1880 if (err)
1881 goto disable_per_clk;
1882
1883 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1884
1885 err = sdhci_runtime_resume_host(host, 0);
1886 if (err)
1887 goto disable_ipg_clk;
1888
1889 if (host->mmc->caps2 & MMC_CAP2_CQE)
1890 err = cqhci_resume(host->mmc);
1891
1892 return err;
1893
1894 disable_ipg_clk:
1895 clk_disable_unprepare(imx_data->clk_ipg);
1896 disable_per_clk:
1897 clk_disable_unprepare(imx_data->clk_per);
1898 disable_ahb_clk:
1899 clk_disable_unprepare(imx_data->clk_ahb);
1900 remove_pm_qos_request:
1901 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1902 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1903 return err;
1904 }
1905 #endif
1906
1907 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1908 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1909 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1910 sdhci_esdhc_runtime_resume, NULL)
1911 };
1912
1913 static struct platform_driver sdhci_esdhc_imx_driver = {
1914 .driver = {
1915 .name = "sdhci-esdhc-imx",
1916 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1917 .of_match_table = imx_esdhc_dt_ids,
1918 .pm = &sdhci_esdhc_pmops,
1919 },
1920 .probe = sdhci_esdhc_imx_probe,
1921 .remove = sdhci_esdhc_imx_remove,
1922 };
1923
1924 module_platform_driver(sdhci_esdhc_imx_driver);
1925
1926 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1927 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1928 MODULE_LICENSE("GPL v2");
1929