1 /*
2 *
3 * Version 3.37
4 *
5 * VIA IDE driver for Linux. Supported southbridges:
6 *
7 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
8 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
9 * vt8235, vt8237
10 *
11 * Copyright (c) 2000-2002 Vojtech Pavlik
12 *
13 * Based on the work of:
14 * Michel Aubry
15 * Jeff Garzik
16 * Andre Hedrick
17 *
18 * Documentation:
19 * Obsolete device documentation publically available from via.com.tw
20 * Current device documentation available under NDA only
21 */
22
23 /*
24 * This program is free software; you can redistribute it and/or modify it
25 * under the terms of the GNU General Public License version 2 as published by
26 * the Free Software Foundation.
27 */
28
29 #include <linux/config.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/ioport.h>
33 #include <linux/blkdev.h>
34 #include <linux/pci.h>
35 #include <linux/init.h>
36 #include <linux/ide.h>
37 #include <asm/io.h>
38
39 #include "ide-timing.h"
40 #include "via82cxxx.h"
41
42 #define VIA_IDE_ENABLE 0x40
43 #define VIA_IDE_CONFIG 0x41
44 #define VIA_FIFO_CONFIG 0x43
45 #define VIA_MISC_1 0x44
46 #define VIA_MISC_2 0x45
47 #define VIA_MISC_3 0x46
48 #define VIA_DRIVE_TIMING 0x48
49 #define VIA_8BIT_TIMING 0x4e
50 #define VIA_ADDRESS_SETUP 0x4c
51 #define VIA_UDMA_TIMING 0x50
52
53 #define VIA_UDMA 0x007
54 #define VIA_UDMA_NONE 0x000
55 #define VIA_UDMA_33 0x001
56 #define VIA_UDMA_66 0x002
57 #define VIA_UDMA_100 0x003
58 #define VIA_UDMA_133 0x004
59 #define VIA_BAD_PREQ 0x010 /* Crashes if PREQ# till DDACK# set */
60 #define VIA_BAD_CLK66 0x020 /* 66 MHz clock doesn't work correctly */
61 #define VIA_SET_FIFO 0x040 /* Needs to have FIFO split set */
62 #define VIA_NO_UNMASK 0x080 /* Doesn't work with IRQ unmasking on */
63 #define VIA_BAD_ID 0x100 /* Has wrong vendor ID (0x1107) */
64 #define VIA_BAD_AST 0x200 /* Don't touch Address Setup Timing */
65
66 /*
67 * VIA SouthBridge chips.
68 */
69
70 static struct via_isa_bridge {
71 char *name;
72 u16 id;
73 u8 rev_min;
74 u8 rev_max;
75 u16 flags;
76 } via_isa_bridges[] = {
77 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
78 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
79 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
80 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
81 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
82 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
83 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
84 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
85 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
86 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
87 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
88 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
89 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
90 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
91 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
92 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
93 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
94 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
95 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
96 { NULL }
97 };
98
99 static struct via_isa_bridge *via_config;
100 static unsigned char via_enabled;
101 static unsigned int via_80w;
102 static unsigned int via_clock;
103 static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
104
105 /*
106 * VIA /proc entry.
107 */
108
109 #if defined(DISPLAY_VIA_TIMINGS) && defined(CONFIG_PROC_FS)
110
111 #include <linux/stat.h>
112 #include <linux/proc_fs.h>
113
114 static u8 via_proc = 0;
115 static unsigned long via_base;
116 static struct pci_dev *bmide_dev, *isa_dev;
117
118 static char *via_control3[] = { "No limit", "64", "128", "192" };
119
120 #define via_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
121 #define via_print_drive(name, format, arg...)\
122 p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
123
124
125 /**
126 * via_get_info - generate via /proc file
127 * @buffer: buffer for data
128 * @addr: set to start of data to use
129 * @offset: current file offset
130 * @count: size of read
131 *
132 * Fills in buffer with the debugging/configuration information for
133 * the VIA chipset tuning and attached drives
134 */
135
via_get_info(char * buffer,char ** addr,off_t offset,int count)136 static int via_get_info(char *buffer, char **addr, off_t offset, int count)
137 {
138 int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
139 uen[4], udma[4], umul[4], active8b[4], recover8b[4];
140 struct pci_dev *dev = bmide_dev;
141 unsigned int v, u, i;
142 int len;
143 u16 c, w;
144 u8 t, x;
145 char *p = buffer;
146
147 via_print("----------VIA BusMastering IDE Configuration"
148 "----------------");
149
150 via_print("Driver Version: 3.37");
151 via_print("South Bridge: VIA %s",
152 via_config->name);
153
154 pci_read_config_byte(isa_dev, PCI_REVISION_ID, &t);
155 pci_read_config_byte(dev, PCI_REVISION_ID, &x);
156 via_print("Revision: ISA %#x IDE %#x", t, x);
157 via_print("Highest DMA rate: %s",
158 via_dma[via_config->flags & VIA_UDMA]);
159
160 via_print("BM-DMA base: %#lx", via_base);
161 via_print("PCI clock: %d.%dMHz",
162 via_clock / 1000, via_clock / 100 % 10);
163
164 pci_read_config_byte(dev, VIA_MISC_1, &t);
165 via_print("Master Read Cycle IRDY: %dws",
166 (t & 64) >> 6);
167 via_print("Master Write Cycle IRDY: %dws",
168 (t & 32) >> 5);
169 via_print("BM IDE Status Register Read Retry: %s",
170 (t & 8) ? "yes" : "no");
171
172 pci_read_config_byte(dev, VIA_MISC_3, &t);
173 via_print("Max DRDY Pulse Width: %s%s",
174 via_control3[(t & 0x03)], (t & 0x03) ? " PCI clocks" : "");
175
176 via_print("-----------------------Primary IDE"
177 "-------Secondary IDE------");
178 via_print("Read DMA FIFO flush: %10s%20s",
179 (t & 0x80) ? "yes" : "no", (t & 0x40) ? "yes" : "no");
180 via_print("End Sector FIFO flush: %10s%20s",
181 (t & 0x20) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
182
183 pci_read_config_byte(dev, VIA_IDE_CONFIG, &t);
184 via_print("Prefetch Buffer: %10s%20s",
185 (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
186 via_print("Post Write Buffer: %10s%20s",
187 (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
188
189 pci_read_config_byte(dev, VIA_IDE_ENABLE, &t);
190 via_print("Enabled: %10s%20s",
191 (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
192
193 c = inb(via_base + 0x02) | (inb(via_base + 0x0a) << 8);
194 via_print("Simplex only: %10s%20s",
195 (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
196
197 via_print("Cable Type: %10s%20s",
198 (via_80w & 1) ? "80w" : "40w", (via_80w & 2) ? "80w" : "40w");
199
200 via_print("-------------------drive0----drive1"
201 "----drive2----drive3-----");
202
203 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
204 pci_read_config_dword(dev, VIA_DRIVE_TIMING, &v);
205 pci_read_config_word(dev, VIA_8BIT_TIMING, &w);
206
207 if (via_config->flags & VIA_UDMA)
208 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
209 else u = 0;
210
211 for (i = 0; i < 4; i++) {
212
213 setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
214 recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
215 active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
216 active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
217 recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
218 udma[i] = ((u >> ((3 - i) << 3)) & 0x7) + 2;
219 umul[i] = ((u >> (((3 - i) & 2) << 3)) & 0x8) ? 1 : 2;
220 uen[i] = ((u >> ((3 - i) << 3)) & 0x20);
221 den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
222
223 speed[i] = 2 * via_clock / (active[i] + recover[i]);
224 cycle[i] = 1000000 * (active[i] + recover[i]) / via_clock;
225
226 if (!uen[i] || !den[i])
227 continue;
228
229 switch (via_config->flags & VIA_UDMA) {
230
231 case VIA_UDMA_33:
232 speed[i] = 2 * via_clock / udma[i];
233 cycle[i] = 1000000 * udma[i] / via_clock;
234 break;
235
236 case VIA_UDMA_66:
237 speed[i] = 4 * via_clock / (udma[i] * umul[i]);
238 cycle[i] = 500000 * (udma[i] * umul[i]) / via_clock;
239 break;
240
241 case VIA_UDMA_100:
242 speed[i] = 6 * via_clock / udma[i];
243 cycle[i] = 333333 * udma[i] / via_clock;
244 break;
245
246 case VIA_UDMA_133:
247 speed[i] = 8 * via_clock / udma[i];
248 cycle[i] = 250000 * udma[i] / via_clock;
249 break;
250 }
251 }
252
253 via_print_drive("Transfer Mode: ", "%10s",
254 den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
255
256 via_print_drive("Address Setup: ", "%8dns",
257 1000000 * setup[i] / via_clock);
258 via_print_drive("Cmd Active: ", "%8dns",
259 1000000 * active8b[i] / via_clock);
260 via_print_drive("Cmd Recovery: ", "%8dns",
261 1000000 * recover8b[i] / via_clock);
262 via_print_drive("Data Active: ", "%8dns",
263 1000000 * active[i] / via_clock);
264 via_print_drive("Data Recovery: ", "%8dns",
265 1000000 * recover[i] / via_clock);
266 via_print_drive("Cycle Time: ", "%8dns",
267 cycle[i]);
268 via_print_drive("Transfer Rate: ", "%4d.%dMB/s",
269 speed[i] / 1000, speed[i] / 100 % 10);
270
271 /* hoping it is less than 4K... */
272 len = (p - buffer) - offset;
273 *addr = buffer + offset;
274
275 return len > count ? count : len;
276 }
277
278 #endif /* DISPLAY_VIA_TIMINGS && CONFIG_PROC_FS */
279
280 /**
281 * via_set_speed - write timing registers
282 * @dev: PCI device
283 * @dn: device
284 * @timing: IDE timing data to use
285 *
286 * via_set_speed writes timing values to the chipset registers
287 */
288
via_set_speed(struct pci_dev * dev,u8 dn,struct ide_timing * timing)289 static void via_set_speed(struct pci_dev *dev, u8 dn, struct ide_timing *timing)
290 {
291 u8 t;
292
293 if (~via_config->flags & VIA_BAD_AST) {
294 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
295 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
296 pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
297 }
298
299 pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
300 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
301
302 pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
303 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
304
305 switch (via_config->flags & VIA_UDMA) {
306 case VIA_UDMA_33: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
307 case VIA_UDMA_66: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
308 case VIA_UDMA_100: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
309 case VIA_UDMA_133: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
310 default: return;
311 }
312
313 pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
314 }
315
316 /**
317 * via_set_drive - configure transfer mode
318 * @drive: Drive to set up
319 * @speed: desired speed
320 *
321 * via_set_drive() computes timing values configures the drive and
322 * the chipset to a desired transfer mode. It also can be called
323 * by upper layers.
324 */
325
via_set_drive(ide_drive_t * drive,u8 speed)326 static int via_set_drive(ide_drive_t *drive, u8 speed)
327 {
328 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
329 struct ide_timing t, p;
330 unsigned int T, UT;
331
332 if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
333 if (ide_config_drive_speed(drive, speed))
334 printk(KERN_WARNING "ide%d: Drive %d didn't "
335 "accept speed setting. Oh, well.\n",
336 drive->dn >> 1, drive->dn & 1);
337
338 T = 1000000000 / via_clock;
339
340 switch (via_config->flags & VIA_UDMA) {
341 case VIA_UDMA_33: UT = T; break;
342 case VIA_UDMA_66: UT = T/2; break;
343 case VIA_UDMA_100: UT = T/3; break;
344 case VIA_UDMA_133: UT = T/4; break;
345 default: UT = T;
346 }
347
348 ide_timing_compute(drive, speed, &t, T, UT);
349
350 if (peer->present) {
351 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
352 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
353 }
354
355 via_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
356
357 if (!drive->init_speed)
358 drive->init_speed = speed;
359 drive->current_speed = speed;
360
361 return 0;
362 }
363
364 /**
365 * via82cxxx_tune_drive - PIO setup
366 * @drive: drive to set up
367 * @pio: mode to use (255 for 'best possible')
368 *
369 * A callback from the upper layers for PIO-only tuning.
370 */
371
via82cxxx_tune_drive(ide_drive_t * drive,u8 pio)372 static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
373 {
374 if (!((via_enabled >> HWIF(drive)->channel) & 1))
375 return;
376
377 if (pio == 255) {
378 via_set_drive(drive,
379 ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
380 return;
381 }
382
383 via_set_drive(drive, XFER_PIO_0 + MIN(pio, 5));
384 }
385
386 /**
387 * via82cxxx_ide_dma_check - set up for DMA if possible
388 * @drive: IDE drive to set up
389 *
390 * Set up the drive for the highest supported speed considering the
391 * driver, controller and cable
392 */
393
via82cxxx_ide_dma_check(ide_drive_t * drive)394 static int via82cxxx_ide_dma_check (ide_drive_t *drive)
395 {
396 u16 w80 = HWIF(drive)->udma_four;
397
398 u16 speed = ide_find_best_mode(drive,
399 XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
400 (via_config->flags & VIA_UDMA ? XFER_UDMA : 0) |
401 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) |
402 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) |
403 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0));
404
405 via_set_drive(drive, speed);
406
407 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
408 return HWIF(drive)->ide_dma_on(drive);
409 return HWIF(drive)->ide_dma_off_quietly(drive);
410 }
411
412 /**
413 * init_chipset_via82cxxx - initialization handler
414 * @dev: PCI device
415 * @name: Name of interface
416 *
417 * The initialization callback. Here we determine the IDE chip type
418 * and initialize its drive independent registers.
419 */
420
init_chipset_via82cxxx(struct pci_dev * dev,const char * name)421 static unsigned int __init init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
422 {
423 struct pci_dev *isa = NULL;
424 u8 t, v;
425 unsigned int u;
426 int i;
427
428 /*
429 * Find the ISA bridge to see how good the IDE is.
430 */
431
432 for (via_config = via_isa_bridges; via_config->id; via_config++)
433 if ((isa = pci_find_device(PCI_VENDOR_ID_VIA +
434 !!(via_config->flags & VIA_BAD_ID),
435 via_config->id, NULL))) {
436
437 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
438 if (t >= via_config->rev_min &&
439 t <= via_config->rev_max)
440 break;
441 }
442
443 if (!via_config->id) {
444 printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
445 return -ENODEV;
446 }
447
448 /*
449 * Check 80-wire cable presence and setup Clk66.
450 */
451
452 switch (via_config->flags & VIA_UDMA) {
453
454 case VIA_UDMA_66:
455 /* Enable Clk66 */
456 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
457 pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
458 for (i = 24; i >= 0; i -= 8)
459 if (((u >> (i & 16)) & 8) &&
460 ((u >> i) & 0x20) &&
461 (((u >> i) & 7) < 2)) {
462 /*
463 * 2x PCI clock and
464 * UDMA w/ < 3T/cycle
465 */
466 via_80w |= (1 << (1 - (i >> 4)));
467 }
468 break;
469
470 case VIA_UDMA_100:
471 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
472 for (i = 24; i >= 0; i -= 8)
473 if (((u >> i) & 0x10) ||
474 (((u >> i) & 0x20) &&
475 (((u >> i) & 7) < 4))) {
476 /* BIOS 80-wire bit or
477 * UDMA w/ < 60ns/cycle
478 */
479 via_80w |= (1 << (1 - (i >> 4)));
480 }
481 break;
482
483 case VIA_UDMA_133:
484 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
485 for (i = 24; i >= 0; i -= 8)
486 if (((u >> i) & 0x10) ||
487 (((u >> i) & 0x20) &&
488 (((u >> i) & 7) < 6))) {
489 /* BIOS 80-wire bit or
490 * UDMA w/ < 60ns/cycle
491 */
492 via_80w |= (1 << (1 - (i >> 4)));
493 }
494 break;
495
496 }
497
498 /* Disable Clk66 */
499 if (via_config->flags & VIA_BAD_CLK66) {
500 /* Would cause trouble on 596a and 686 */
501 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
502 pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
503 }
504
505 /*
506 * Check whether interfaces are enabled.
507 */
508
509 pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
510 via_enabled = ((v & 1) ? 2 : 0) | ((v & 2) ? 1 : 0);
511
512 /*
513 * Set up FIFO sizes and thresholds.
514 */
515
516 pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
517
518 /* Disable PREQ# till DDACK# */
519 if (via_config->flags & VIA_BAD_PREQ) {
520 /* Would crash on 586b rev 41 */
521 t &= 0x7f;
522 }
523
524 /* Fix FIFO split between channels */
525 if (via_config->flags & VIA_SET_FIFO) {
526 t &= (t & 0x9f);
527 switch (via_enabled) {
528 case 1: t |= 0x00; break; /* 16 on primary */
529 case 2: t |= 0x60; break; /* 16 on secondary */
530 case 3: t |= 0x20; break; /* 8 pri 8 sec */
531 }
532 }
533
534 pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
535
536 /*
537 * Determine system bus clock.
538 */
539
540 via_clock = system_bus_clock() * 1000;
541
542 switch (via_clock) {
543 case 33000: via_clock = 33333; break;
544 case 37000: via_clock = 37500; break;
545 case 41000: via_clock = 41666; break;
546 }
547
548 if (via_clock < 20000 || via_clock > 50000) {
549 printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
550 "impossible (%d), using 33 MHz instead.\n", via_clock);
551 printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
552 "to assume 80-wire cable.\n");
553 via_clock = 33333;
554 }
555
556 /*
557 * Print the boot message.
558 */
559
560 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
561 printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s "
562 "controller on pci%s\n",
563 via_config->name, t,
564 via_dma[via_config->flags & VIA_UDMA],
565 dev->slot_name);
566
567 /*
568 * Setup /proc/ide/via entry.
569 */
570
571 #if defined(DISPLAY_VIA_TIMINGS) && defined(CONFIG_PROC_FS)
572 if (!via_proc) {
573 via_base = pci_resource_start(dev, 4);
574 bmide_dev = dev;
575 isa_dev = isa;
576 ide_pci_register_host_proc(&via_procs[0]);
577 via_proc = 1;
578 }
579 #endif /* DISPLAY_VIA_TIMINGS && CONFIG_PROC_FS */
580 return 0;
581 }
582
init_hwif_via82cxxx(ide_hwif_t * hwif)583 static void __init init_hwif_via82cxxx(ide_hwif_t *hwif)
584 {
585 int i;
586
587 hwif->autodma = 0;
588
589 hwif->tuneproc = &via82cxxx_tune_drive;
590 hwif->speedproc = &via_set_drive;
591
592 for (i = 0; i < 2; i++) {
593 hwif->drives[i].io_32bit = 1;
594 hwif->drives[i].unmask = (via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
595 hwif->drives[i].autotune = 1;
596 hwif->drives[i].dn = hwif->channel * 2 + i;
597 }
598
599 if (!hwif->dma_base)
600 return;
601
602 hwif->atapi_dma = 1;
603 hwif->ultra_mask = 0x7f;
604 hwif->mwdma_mask = 0x07;
605 hwif->swdma_mask = 0x07;
606
607 if (!(hwif->udma_four))
608 hwif->udma_four = ((via_enabled & via_80w) >> hwif->channel) & 1;
609 hwif->ide_dma_check = &via82cxxx_ide_dma_check;
610 if (!noautodma)
611 hwif->autodma = 1;
612 hwif->drives[0].autodma = hwif->autodma;
613 hwif->drives[1].autodma = hwif->autodma;
614 }
615
616 /**
617 * init_dma_via82cxxx - set up for IDE DMA
618 * @hwif: IDE interface
619 * @dmabase: DMA base address
620 *
621 * We allow the BM-DMA driver to only work on enabled interfaces.
622 */
623
init_dma_via82cxxx(ide_hwif_t * hwif,unsigned long dmabase)624 static void __init init_dma_via82cxxx(ide_hwif_t *hwif, unsigned long dmabase)
625 {
626 if ((via_enabled >> hwif->channel) & 1)
627 ide_setup_dma(hwif, dmabase, 8);
628 }
629
630 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
631
via_init_one(struct pci_dev * dev,const struct pci_device_id * id)632 static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
633 {
634 ide_pci_device_t *d = &via82cxxx_chipsets[id->driver_data];
635 if (dev->device != d->device)
636 BUG();
637 ide_setup_pci_device(dev, d);
638 MOD_INC_USE_COUNT;
639 return 0;
640 }
641
642 static struct pci_device_id via_pci_tbl[] __devinitdata = {
643 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
644 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
645 { 0, },
646 };
647
648 static struct pci_driver driver = {
649 .name = "VIA IDE",
650 .id_table = via_pci_tbl,
651 .probe = via_init_one,
652 };
653
via_ide_init(void)654 static int via_ide_init(void)
655 {
656 return ide_pci_register_driver(&driver);
657 }
658
via_ide_exit(void)659 static void via_ide_exit(void)
660 {
661 ide_pci_unregister_driver(&driver);
662 }
663
664 module_init(via_ide_init);
665 module_exit(via_ide_exit);
666
667 MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
668 MODULE_DESCRIPTION("PCI driver module for VIA IDE");
669 MODULE_LICENSE("GPL");
670
671 EXPORT_NO_SYMBOLS;
672