1 /* 2 * rocket_int.h --- internal header file for rocket.c 3 * 4 * Written by Theodore Ts'o, Copyright 1997. 5 * 6 * Portions of this file are.... 7 * 8 * Copyright 1994 Comtrol Corporation. All Rights Reserved. 9 * 10 * Erroneously clashing license removed. This file is GPL 11 * (Kurt Robideau, Comtrol Corp, 20030610) 12 * This driver is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This driver is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 */ 22 23 /* 24 * Begin Comtrol-provided headers, et. al. 25 */ 26 27 /* 28 user definitions for Rocket Toolkit 29 30 The following typedefs and defines must be established 31 depending on the platform the toolkit is being used 32 with. 33 34 */ 35 36 /************************************************************ 37 The following sets up the world for use with Linux 38 ************************************************************/ 39 40 #include <asm/io.h> 41 42 typedef unsigned char Byte_t; 43 typedef unsigned int ByteIO_t; 44 45 typedef unsigned int Word_t; 46 typedef unsigned int WordIO_t; 47 48 typedef unsigned long DWord_t; 49 typedef unsigned int DWordIO_t; 50 51 #define sOutB(a, b) outb_p(b, a) 52 #define sOutW(a, b) outw_p(b, a) 53 #define sOutDW(a, b) outl_p(b, a) 54 #define sInB(a) (inb_p(a)) 55 #define sInW(a) (inw_p(a)) 56 57 #define sOutStrW(port, addr, count) outsw(port, addr, count) 58 59 #define sInStrW(port, addr, count) insw(port, addr, count) 60 61 #define CTL_SIZE 4 62 #define AIOP_CTL_SIZE 4 63 #define CHAN_AIOP_SIZE 8 64 #define MAX_PORTS_PER_AIOP 8 65 #define MAX_AIOPS_PER_BOARD 4 66 #define MAX_PORTS_PER_BOARD 32 67 68 /* Bus type ID */ 69 #define isISA 0 70 #define isPCI 1 71 #define isMC 2 72 73 /* Controller ID numbers */ 74 #define CTLID_NULL -1 /* no controller exists */ 75 #define CTLID_0001 0x0001 /* controller release 1 */ 76 77 /* AIOP ID numbers, identifies AIOP type implementing channel */ 78 #define AIOPID_NULL -1 /* no AIOP or channel exists */ 79 #define AIOPID_0001 0x0001 /* AIOP release 1 */ 80 81 #define NULLDEV -1 /* identifies non-existant device */ 82 #define NULLCTL -1 /* identifies non-existant controller */ 83 #define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */ 84 #define NULLAIOP -1 /* identifies non-existant AIOP */ 85 #define NULLCHAN -1 /* identifies non-existant channel */ 86 87 /************************************************************************ 88 Global Register Offsets - Direct Access - Fixed values 89 ************************************************************************/ 90 91 #define _CMD_REG 0x38 /* Command Register 8 Write */ 92 #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */ 93 #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */ 94 #define _UNUSED 0x3B /* Unused 8 */ 95 #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */ 96 #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */ 97 98 /************************************************************************ 99 Channel Register Offsets for 1st channel in AIOP - Direct Access 100 ************************************************************************/ 101 #define _TD0 0x00 /* Transmit Data 16 Write */ 102 #define _RD0 0x00 /* Receive Data 16 Read */ 103 #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */ 104 #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */ 105 #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */ 106 107 /************************************************************************ 108 Tx Control Register Offsets - Indexed - External - Fixed 109 ************************************************************************/ 110 #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */ 111 #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */ 112 #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */ 113 #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */ 114 #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */ 115 #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */ 116 117 /************************************************************************ 118 Memory Controller Register Offsets - Indexed - External - Fixed 119 ************************************************************************/ 120 #define _RX_FIFO 0x000 /* Rx FIFO */ 121 #define _TX_FIFO 0x800 /* Tx FIFO */ 122 #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */ 123 #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */ 124 #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */ 125 #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */ 126 #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */ 127 #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */ 128 129 #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */ 130 #define TXFIFO_SIZE 255 /* size of Tx FIFO */ 131 #define RXFIFO_SIZE 1023 /* size of Rx FIFO */ 132 133 /************************************************************************ 134 Tx Priority Buffer - Indexed - External - Fixed 135 ************************************************************************/ 136 #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */ 137 #define TXP_SIZE 0x20 /* 32 bytes */ 138 139 /************************************************************************ 140 Channel Register Offsets - Indexed - Internal - Fixed 141 ************************************************************************/ 142 143 #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */ 144 #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */ 145 #define _BAUD 0xFF4 /* Baud Rate 16 Write */ 146 #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */ 147 148 #if 0 149 #define CLOCK_PRESC 0x14 /* ?????? new mod 4 (divide by 5) prescale */ 150 151 #define BRD50 9215 152 #define BRD75 6143 153 #define BRD110 4188 154 #define BRD134 3438 155 #define BRD150 3071 156 #define BRD200 2303 157 #define BRD300 1535 158 #define BRD600 767 159 #define BRD1200 383 160 #define BRD1800 255 161 #define BRD2000 229 162 #define BRD2400 191 163 #define BRD3600 127 164 #define BRD4800 95 165 #define BRD7200 63 166 #define BRD9600 47 167 #define BRD14400 31 168 #define BRD19200 23 169 #define BRD38400 11 170 #define BRD57600 7 171 #define BRD76800 5 172 #define BRD115200 3 173 #define BRD230400 1 174 #define BRD460800 0 175 #endif 176 177 #if 0 178 179 /* Old clock prescale definition and baud rates associated with it */ 180 181 #define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */ 182 #define BRD50 4607 183 #define BRD75 3071 184 #define BRD110 2094 185 #define BRD134 1712 186 #define BRD150 1535 187 #define BRD200 1151 188 #define BRD300 767 189 #define BRD600 383 190 #define BRD1200 191 191 #define BRD1800 127 192 #define BRD2000 114 193 #define BRD2400 95 194 #define BRD3600 64 195 #define BRD4800 47 196 #define BRD7200 31 197 #define BRD9600 23 198 #define BRD14400 15 199 #define BRD19200 11 200 #define BRD38400 5 201 #define BRD57600 3 202 #define BRD76800 2 203 #define BRD115200 1 204 #define BRD230400 0 205 206 #endif 207 208 #define STMBREAK 0x08 /* BREAK */ 209 #define STMFRAME 0x04 /* framing error */ 210 #define STMRCVROVR 0x02 /* receiver over run error */ 211 #define STMPARITY 0x01 /* parity error */ 212 #define STMERROR (STMBREAK | STMFRAME | STMPARITY) 213 #define STMBREAKH 0x800 /* BREAK */ 214 #define STMFRAMEH 0x400 /* framing error */ 215 #define STMRCVROVRH 0x200 /* receiver over run error */ 216 #define STMPARITYH 0x100 /* parity error */ 217 #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH) 218 219 #define CTS_ACT 0x20 /* CTS input asserted */ 220 #define DSR_ACT 0x10 /* DSR input asserted */ 221 #define CD_ACT 0x08 /* CD input asserted */ 222 #define TXFIFOMT 0x04 /* Tx FIFO is empty */ 223 #define TXSHRMT 0x02 /* Tx shift register is empty */ 224 #define RDA 0x01 /* Rx data available */ 225 #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */ 226 227 #define STATMODE 0x8000 /* status mode enable bit */ 228 #define RXFOVERFL 0x2000 /* receive FIFO overflow */ 229 #define RX2MATCH 0x1000 /* receive compare byte 2 match */ 230 #define RX1MATCH 0x0800 /* receive compare byte 1 match */ 231 #define RXBREAK 0x0400 /* received BREAK */ 232 #define RXFRAME 0x0200 /* received framing error */ 233 #define RXPARITY 0x0100 /* received parity error */ 234 #define STATERROR (RXBREAK | RXFRAME | RXPARITY) 235 236 #define CTSFC_EN 0x80 /* CTS flow control enable bit */ 237 #define RTSTOG_EN 0x40 /* RTS toggle enable bit */ 238 #define TXINT_EN 0x10 /* transmit interrupt enable */ 239 #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */ 240 #define PARITY_EN 0x04 /* enable parity (0 = no parity) */ 241 #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */ 242 #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */ 243 244 #define SETBREAK 0x10 /* send break condition (must clear) */ 245 #define LOCALLOOP 0x08 /* local loopback set for test */ 246 #define SET_DTR 0x04 /* assert DTR */ 247 #define SET_RTS 0x02 /* assert RTS */ 248 #define TX_ENABLE 0x01 /* enable transmitter */ 249 250 #define RTSFC_EN 0x40 /* RTS flow control enable */ 251 #define RXPROC_EN 0x20 /* receive processor enable */ 252 #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */ 253 #define TRIG_1 0x08 /* trigger level 1 char */ 254 #define TRIG_1_2 0x10 /* trigger level 1/2 */ 255 #define TRIG_7_8 0x18 /* trigger level 7/8 */ 256 #define TRIG_MASK 0x18 /* trigger level mask */ 257 #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */ 258 #define RXINT_EN 0x02 /* Rx interrupt enable */ 259 #define MCINT_EN 0x01 /* modem change interrupt enable */ 260 261 #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */ 262 #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */ 263 #define SRC_INT 0x08 /* special receive condition interrupt */ 264 #define DELTA_CD 0x04 /* CD change interrupt */ 265 #define DELTA_CTS 0x02 /* CTS change interrupt */ 266 #define DELTA_DSR 0x01 /* DSR change interrupt */ 267 268 #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */ 269 #define IGN2_EN 0x08 /* ignore byte 2 enable */ 270 #define IGN1_EN 0x04 /* ignore byte 1 enable */ 271 #define COMP2_EN 0x02 /* compare byte 2 enable */ 272 #define COMP1_EN 0x01 /* compare byte 1 enable */ 273 274 #define RESET_ALL 0x80 /* reset AIOP (all channels) */ 275 #define TXOVERIDE 0x40 /* Transmit software off override */ 276 #define RESETUART 0x20 /* reset channel's UART */ 277 #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */ 278 #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */ 279 280 #define INTSTAT0 0x01 /* AIOP 0 interrupt status */ 281 #define INTSTAT1 0x02 /* AIOP 1 interrupt status */ 282 #define INTSTAT2 0x04 /* AIOP 2 interrupt status */ 283 #define INTSTAT3 0x08 /* AIOP 3 interrupt status */ 284 285 #define INTR_EN 0x08 /* allow interrupts to host */ 286 #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */ 287 288 /************************************************************************** 289 MUDBAC remapped for PCI 290 **************************************************************************/ 291 292 #define _CFG_INT_PCI 0x40 293 #define _PCI_INT_FUNC 0x3A 294 295 #define PCI_STROB 0x2000 /* bit 13 of int aiop register */ 296 #define INTR_EN_PCI 0x0010 /* allow interrupts to host */ 297 298 299 #define CHAN3_EN 0x08 /* enable AIOP 3 */ 300 #define CHAN2_EN 0x04 /* enable AIOP 2 */ 301 #define CHAN1_EN 0x02 /* enable AIOP 1 */ 302 #define CHAN0_EN 0x01 /* enable AIOP 0 */ 303 #define FREQ_DIS 0x00 304 #define FREQ_274HZ 0x60 305 #define FREQ_137HZ 0x50 306 #define FREQ_69HZ 0x40 307 #define FREQ_34HZ 0x30 308 #define FREQ_17HZ 0x20 309 #define FREQ_9HZ 0x10 310 #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */ 311 312 #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */ 313 314 #define RDATASIZE 72 315 #define RREGDATASIZE 52 316 317 /* Controller level information structure */ 318 typedef struct 319 { 320 int CtlID; 321 int CtlNum; 322 int BusType; 323 WordIO_t PCIIO; 324 ByteIO_t MBaseIO; 325 ByteIO_t MReg1IO; 326 ByteIO_t MReg2IO; 327 ByteIO_t MReg3IO; 328 Byte_t MReg2; 329 Byte_t MReg3; 330 int NumAiop; 331 WordIO_t AiopIO[AIOP_CTL_SIZE]; 332 ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE]; 333 int AiopID[AIOP_CTL_SIZE]; 334 int AiopNumChan[AIOP_CTL_SIZE]; 335 } CONTROLLER_T; 336 337 typedef CONTROLLER_T CONTROLLER_t; 338 339 /* Channel level information structure */ 340 typedef struct 341 { 342 CONTROLLER_T *CtlP; 343 int AiopNum; 344 int ChanID; 345 int ChanNum; 346 347 ByteIO_t Cmd; 348 ByteIO_t IntChan; 349 ByteIO_t IntMask; 350 DWordIO_t IndexAddr; 351 WordIO_t IndexData; 352 353 WordIO_t TxRxData; 354 WordIO_t ChanStat; 355 WordIO_t TxRxCount; 356 ByteIO_t IntID; 357 358 Word_t TxFIFO; 359 Word_t TxFIFOPtrs; 360 Word_t RxFIFO; 361 Word_t RxFIFOPtrs; 362 Word_t TxPrioCnt; 363 Word_t TxPrioPtr; 364 Word_t TxPrioBuf; 365 366 Byte_t R[RREGDATASIZE]; 367 368 Byte_t BaudDiv[4]; 369 Byte_t TxControl[4]; 370 Byte_t RxControl[4]; 371 Byte_t TxEnables[4]; 372 Byte_t TxCompare[4]; 373 Byte_t TxReplace1[4]; 374 Byte_t TxReplace2[4]; 375 } CHANNEL_T; 376 377 typedef CHANNEL_T CHANNEL_t; 378 typedef CHANNEL_T * CHANPTR_T; 379 380 /*************************************************************************** 381 Function: sClrBreak 382 Purpose: Stop sending a transmit BREAK signal 383 Call: sClrBreak(ChP) 384 CHANNEL_T *ChP; Ptr to channel structure 385 */ 386 #define sClrBreak(ChP) \ 387 { \ 388 (ChP)->TxControl[3] &= ~SETBREAK; \ 389 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 390 } 391 392 /*************************************************************************** 393 Function: sClrDTR 394 Purpose: Clr the DTR output 395 Call: sClrDTR(ChP) 396 CHANNEL_T *ChP; Ptr to channel structure 397 */ 398 #define sClrDTR(ChP) \ 399 { \ 400 (ChP)->TxControl[3] &= ~SET_DTR; \ 401 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 402 } 403 404 /*************************************************************************** 405 Function: sClrRTS 406 Purpose: Clr the RTS output 407 Call: sClrRTS(ChP) 408 CHANNEL_T *ChP; Ptr to channel structure 409 */ 410 #define sClrRTS(ChP) \ 411 { \ 412 (ChP)->TxControl[3] &= ~SET_RTS; \ 413 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 414 } 415 416 /*************************************************************************** 417 Function: sClrTxXOFF 418 Purpose: Clear any existing transmit software flow control off condition 419 Call: sClrTxXOFF(ChP) 420 CHANNEL_T *ChP; Ptr to channel structure 421 */ 422 #define sClrTxXOFF(ChP) \ 423 { \ 424 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \ 425 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \ 426 } 427 428 /*************************************************************************** 429 Function: sCtlNumToCtlPtr 430 Purpose: Convert a controller number to controller structure pointer 431 Call: sCtlNumToCtlPtr(CtlNum) 432 int CtlNum; Controller number 433 Return: CONTROLLER_T *: Ptr to controller structure 434 */ 435 #define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM] 436 437 /*************************************************************************** 438 Function: sControllerEOI 439 Purpose: Strobe the MUDBAC's End Of Interrupt bit. 440 Call: sControllerEOI(CtlP) 441 CONTROLLER_T *CtlP; Ptr to controller structure 442 */ 443 #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB) 444 445 /*************************************************************************** 446 Function: sPCIControllerEOI 447 Purpose: Strobe the PCI End Of Interrupt bit. 448 Call: sPCIControllerEOI(CtlP) 449 CONTROLLER_T *CtlP; Ptr to controller structure 450 */ 451 #define sPCIControllerEOI(CTLP) sOutW((CTLP)->PCIIO, PCI_STROB) 452 453 /*************************************************************************** 454 Function: sDisAiop 455 Purpose: Disable I/O access to an AIOP 456 Call: sDisAiop(CltP) 457 CONTROLLER_T *CtlP; Ptr to controller structure 458 int AiopNum; Number of AIOP on controller 459 */ 460 #define sDisAiop(CTLP,AIOPNUM) \ 461 { \ 462 (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \ 463 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ 464 } 465 466 /*************************************************************************** 467 Function: sDisCTSFlowCtl 468 Purpose: Disable output flow control using CTS 469 Call: sDisCTSFlowCtl(ChP) 470 CHANNEL_T *ChP; Ptr to channel structure 471 */ 472 #define sDisCTSFlowCtl(ChP) \ 473 { \ 474 (ChP)->TxControl[2] &= ~CTSFC_EN; \ 475 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 476 } 477 478 /*************************************************************************** 479 Function: sDisIXANY 480 Purpose: Disable IXANY Software Flow Control 481 Call: sDisIXANY(ChP) 482 CHANNEL_T *ChP; Ptr to channel structure 483 */ 484 #define sDisIXANY(ChP) \ 485 { \ 486 (ChP)->R[0x0e] = 0x86; \ 487 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ 488 } 489 490 /*************************************************************************** 491 Function: DisParity 492 Purpose: Disable parity 493 Call: sDisParity(ChP) 494 CHANNEL_T *ChP; Ptr to channel structure 495 Comments: Function sSetParity() can be used in place of functions sEnParity(), 496 sDisParity(), sSetOddParity(), and sSetEvenParity(). 497 */ 498 #define sDisParity(ChP) \ 499 { \ 500 (ChP)->TxControl[2] &= ~PARITY_EN; \ 501 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 502 } 503 504 /*************************************************************************** 505 Function: sDisRxFIFO 506 Purpose: Disable Rx FIFO 507 Call: sDisRxFIFO(ChP) 508 CHANNEL_T *ChP; Ptr to channel structure 509 */ 510 #define sDisRxFIFO(ChP) \ 511 { \ 512 (ChP)->R[0x32] = 0x0a; \ 513 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ 514 } 515 516 /*************************************************************************** 517 Function: sDisRxStatusMode 518 Purpose: Disable the Rx status mode 519 Call: sDisRxStatusMode(ChP) 520 CHANNEL_T *ChP; Ptr to channel structure 521 Comments: This takes the channel out of the receive status mode. All 522 subsequent reads of receive data using sReadRxWord() will return 523 two data bytes. 524 */ 525 #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0) 526 527 /*************************************************************************** 528 Function: sDisTransmit 529 Purpose: Disable transmit 530 Call: sDisTransmit(ChP) 531 CHANNEL_T *ChP; Ptr to channel structure 532 This disables movement of Tx data from the Tx FIFO into the 1 byte 533 Tx buffer. Therefore there could be up to a 2 byte latency 534 between the time sDisTransmit() is called and the transmit buffer 535 and transmit shift register going completely empty. 536 */ 537 #define sDisTransmit(ChP) \ 538 { \ 539 (ChP)->TxControl[3] &= ~TX_ENABLE; \ 540 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 541 } 542 543 /*************************************************************************** 544 Function: sDisTxSoftFlowCtl 545 Purpose: Disable Tx Software Flow Control 546 Call: sDisTxSoftFlowCtl(ChP) 547 CHANNEL_T *ChP; Ptr to channel structure 548 */ 549 #define sDisTxSoftFlowCtl(ChP) \ 550 { \ 551 (ChP)->R[0x06] = 0x8a; \ 552 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 553 } 554 555 /*************************************************************************** 556 Function: sEnAiop 557 Purpose: Enable I/O access to an AIOP 558 Call: sEnAiop(CltP) 559 CONTROLLER_T *CtlP; Ptr to controller structure 560 int AiopNum; Number of AIOP on controller 561 */ 562 #define sEnAiop(CTLP,AIOPNUM) \ 563 { \ 564 (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \ 565 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \ 566 } 567 568 /*************************************************************************** 569 Function: sEnCTSFlowCtl 570 Purpose: Enable output flow control using CTS 571 Call: sEnCTSFlowCtl(ChP) 572 CHANNEL_T *ChP; Ptr to channel structure 573 */ 574 #define sEnCTSFlowCtl(ChP) \ 575 { \ 576 (ChP)->TxControl[2] |= CTSFC_EN; \ 577 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 578 } 579 580 /*************************************************************************** 581 Function: sEnIXANY 582 Purpose: Enable IXANY Software Flow Control 583 Call: sEnIXANY(ChP) 584 CHANNEL_T *ChP; Ptr to channel structure 585 */ 586 #define sEnIXANY(ChP) \ 587 { \ 588 (ChP)->R[0x0e] = 0x21; \ 589 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ 590 } 591 592 /*************************************************************************** 593 Function: EnParity 594 Purpose: Enable parity 595 Call: sEnParity(ChP) 596 CHANNEL_T *ChP; Ptr to channel structure 597 Comments: Function sSetParity() can be used in place of functions sEnParity(), 598 sDisParity(), sSetOddParity(), and sSetEvenParity(). 599 600 Warnings: Before enabling parity odd or even parity should be chosen using 601 functions sSetOddParity() or sSetEvenParity(). 602 */ 603 #define sEnParity(ChP) \ 604 { \ 605 (ChP)->TxControl[2] |= PARITY_EN; \ 606 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 607 } 608 609 /*************************************************************************** 610 Function: sEnRxFIFO 611 Purpose: Enable Rx FIFO 612 Call: sEnRxFIFO(ChP) 613 CHANNEL_T *ChP; Ptr to channel structure 614 */ 615 #define sEnRxFIFO(ChP) \ 616 { \ 617 (ChP)->R[0x32] = 0x08; \ 618 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ 619 } 620 621 /*************************************************************************** 622 Function: sEnRxProcessor 623 Purpose: Enable the receive processor 624 Call: sEnRxProcessor(ChP) 625 CHANNEL_T *ChP; Ptr to channel structure 626 Comments: This function is used to start the receive processor. When 627 the channel is in the reset state the receive processor is not 628 running. This is done to prevent the receive processor from 629 executing invalid microcode instructions prior to the 630 downloading of the microcode. 631 632 Warnings: This function must be called after valid microcode has been 633 downloaded to the AIOP, and it must not be called before the 634 microcode has been downloaded. 635 */ 636 #define sEnRxProcessor(ChP) \ 637 { \ 638 (ChP)->RxControl[2] |= RXPROC_EN; \ 639 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 640 } 641 642 /*************************************************************************** 643 Function: sEnRxStatusMode 644 Purpose: Enable the Rx status mode 645 Call: sEnRxStatusMode(ChP) 646 CHANNEL_T *ChP; Ptr to channel structure 647 Comments: This places the channel in the receive status mode. All subsequent 648 reads of receive data using sReadRxWord() will return a data byte 649 in the low word and a status byte in the high word. 650 651 */ 652 #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE) 653 654 /*************************************************************************** 655 Function: sEnTransmit 656 Purpose: Enable transmit 657 Call: sEnTransmit(ChP) 658 CHANNEL_T *ChP; Ptr to channel structure 659 */ 660 #define sEnTransmit(ChP) \ 661 { \ 662 (ChP)->TxControl[3] |= TX_ENABLE; \ 663 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 664 } 665 666 /*************************************************************************** 667 Function: sEnTxSoftFlowCtl 668 Purpose: Enable Tx Software Flow Control 669 Call: sEnTxSoftFlowCtl(ChP) 670 CHANNEL_T *ChP; Ptr to channel structure 671 */ 672 #define sEnTxSoftFlowCtl(ChP) \ 673 { \ 674 (ChP)->R[0x06] = 0xc5; \ 675 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 676 } 677 678 /*************************************************************************** 679 Function: sGetAiopIntStatus 680 Purpose: Get the AIOP interrupt status 681 Call: sGetAiopIntStatus(CtlP,AiopNum) 682 CONTROLLER_T *CtlP; Ptr to controller structure 683 int AiopNum; AIOP number 684 Return: Byte_t: The AIOP interrupt status. Bits 0 through 7 685 represent channels 0 through 7 respectively. If a 686 bit is set that channel is interrupting. 687 */ 688 #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM]) 689 690 /*************************************************************************** 691 Function: sGetAiopNumChan 692 Purpose: Get the number of channels supported by an AIOP 693 Call: sGetAiopNumChan(CtlP,AiopNum) 694 CONTROLLER_T *CtlP; Ptr to controller structure 695 int AiopNum; AIOP number 696 Return: int: The number of channels supported by the AIOP 697 */ 698 #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM] 699 700 /*************************************************************************** 701 Function: sGetChanIntID 702 Purpose: Get a channel's interrupt identification byte 703 Call: sGetChanIntID(ChP) 704 CHANNEL_T *ChP; Ptr to channel structure 705 Return: Byte_t: The channel interrupt ID. Can be any 706 combination of the following flags: 707 RXF_TRIG: Rx FIFO trigger level interrupt 708 TXFIFO_MT: Tx FIFO empty interrupt 709 SRC_INT: Special receive condition interrupt 710 DELTA_CD: CD change interrupt 711 DELTA_CTS: CTS change interrupt 712 DELTA_DSR: DSR change interrupt 713 */ 714 #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR)) 715 716 /*************************************************************************** 717 Function: sGetChanNum 718 Purpose: Get the number of a channel within an AIOP 719 Call: sGetChanNum(ChP) 720 CHANNEL_T *ChP; Ptr to channel structure 721 Return: int: Channel number within AIOP, or NULLCHAN if channel does 722 not exist. 723 */ 724 #define sGetChanNum(ChP) (ChP)->ChanNum 725 726 /*************************************************************************** 727 Function: sGetChanStatus 728 Purpose: Get the channel status 729 Call: sGetChanStatus(ChP) 730 CHANNEL_T *ChP; Ptr to channel structure 731 Return: Word_t: The channel status. Can be any combination of 732 the following flags: 733 LOW BYTE FLAGS 734 CTS_ACT: CTS input asserted 735 DSR_ACT: DSR input asserted 736 CD_ACT: CD input asserted 737 TXFIFOMT: Tx FIFO is empty 738 TXSHRMT: Tx shift register is empty 739 RDA: Rx data available 740 741 HIGH BYTE FLAGS 742 STATMODE: status mode enable bit 743 RXFOVERFL: receive FIFO overflow 744 RX2MATCH: receive compare byte 2 match 745 RX1MATCH: receive compare byte 1 match 746 RXBREAK: received BREAK 747 RXFRAME: received framing error 748 RXPARITY: received parity error 749 Warnings: This function will clear the high byte flags in the Channel 750 Status Register. 751 */ 752 #define sGetChanStatus(ChP) sInW((ChP)->ChanStat) 753 754 /*************************************************************************** 755 Function: sGetChanStatusLo 756 Purpose: Get the low byte only of the channel status 757 Call: sGetChanStatusLo(ChP) 758 CHANNEL_T *ChP; Ptr to channel structure 759 Return: Byte_t: The channel status low byte. Can be any combination 760 of the following flags: 761 CTS_ACT: CTS input asserted 762 DSR_ACT: DSR input asserted 763 CD_ACT: CD input asserted 764 TXFIFOMT: Tx FIFO is empty 765 TXSHRMT: Tx shift register is empty 766 RDA: Rx data available 767 */ 768 #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat) 769 770 /*************************************************************************** 771 Function: sGetControllerIntStatus 772 Purpose: Get the controller interrupt status 773 Call: sGetControllerIntStatus(CtlP) 774 CONTROLLER_T *CtlP; Ptr to controller structure 775 Return: Byte_t: The controller interrupt status in the lower 4 776 bits. Bits 0 through 3 represent AIOP's 0 777 through 3 respectively. If a bit is set that 778 AIOP is interrupting. Bits 4 through 7 will 779 always be cleared. 780 */ 781 #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f) 782 783 /*************************************************************************** 784 Function: sPCIGetControllerIntStatus 785 Purpose: Get the controller interrupt status 786 Call: sPCIGetControllerIntStatus(CtlP) 787 CONTROLLER_T *CtlP; Ptr to controller structure 788 Return: unsigned char: The controller interrupt status in the lower 4 789 bits and bit 4. Bits 0 through 3 represent AIOP's 0 790 through 3 respectively. Bit 4 is set if the int 791 was generated from periodic. If a bit is set the 792 AIOP is interrupting. 793 */ 794 #define sPCIGetControllerIntStatus(CTLP) ((sInW((CTLP)->PCIIO) >> 8) & 0x1f) 795 796 /*************************************************************************** 797 798 Function: sGetRxCnt 799 Purpose: Get the number of data bytes in the Rx FIFO 800 Call: sGetRxCnt(ChP) 801 CHANNEL_T *ChP; Ptr to channel structure 802 Return: int: The number of data bytes in the Rx FIFO. 803 Comments: Byte read of count register is required to obtain Rx count. 804 805 */ 806 #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount) 807 808 /*************************************************************************** 809 Function: sGetTxCnt 810 Purpose: Get the number of data bytes in the Tx FIFO 811 Call: sGetTxCnt(ChP) 812 CHANNEL_T *ChP; Ptr to channel structure 813 Return: Byte_t: The number of data bytes in the Tx FIFO. 814 Comments: Byte read of count register is required to obtain Tx count. 815 816 */ 817 #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount) 818 819 /***************************************************************************** 820 Function: sGetTxRxDataIO 821 Purpose: Get the I/O address of a channel's TxRx Data register 822 Call: sGetTxRxDataIO(ChP) 823 CHANNEL_T *ChP; Ptr to channel structure 824 Return: WordIO_t: I/O address of a channel's TxRx Data register 825 */ 826 #define sGetTxRxDataIO(ChP) (ChP)->TxRxData 827 828 /*************************************************************************** 829 Function: sInitChanDefaults 830 Purpose: Initialize a channel structure to it's default state. 831 Call: sInitChanDefaults(ChP) 832 CHANNEL_T *ChP; Ptr to the channel structure 833 Comments: This function must be called once for every channel structure 834 that exists before any other SSCI calls can be made. 835 836 */ 837 #define sInitChanDefaults(ChP) \ 838 { \ 839 (ChP)->CtlP = NULLCTLPTR; \ 840 (ChP)->AiopNum = NULLAIOP; \ 841 (ChP)->ChanID = AIOPID_NULL; \ 842 (ChP)->ChanNum = NULLCHAN; \ 843 } 844 845 /*************************************************************************** 846 Function: sResetAiopByNum 847 Purpose: Reset the AIOP by number 848 Call: sResetAiopByNum(CTLP,AIOPNUM) 849 CONTROLLER_T CTLP; Ptr to controller structure 850 AIOPNUM; AIOP index 851 */ 852 #define sResetAiopByNum(CTLP,AIOPNUM) \ 853 { \ 854 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \ 855 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \ 856 } 857 858 /*************************************************************************** 859 Function: sSendBreak 860 Purpose: Send a transmit BREAK signal 861 Call: sSendBreak(ChP) 862 CHANNEL_T *ChP; Ptr to channel structure 863 */ 864 #define sSendBreak(ChP) \ 865 { \ 866 (ChP)->TxControl[3] |= SETBREAK; \ 867 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 868 } 869 870 /*************************************************************************** 871 Function: sSetBaud 872 Purpose: Set baud rate 873 Call: sSetBaud(ChP,Divisor) 874 CHANNEL_T *ChP; Ptr to channel structure 875 Word_t Divisor; 16 bit baud rate divisor for channel 876 */ 877 #define sSetBaud(ChP,DIVISOR) \ 878 { \ 879 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ 880 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ 881 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \ 882 } 883 884 /*************************************************************************** 885 Function: sSetData7 886 Purpose: Set data bits to 7 887 Call: sSetData7(ChP) 888 CHANNEL_T *ChP; Ptr to channel structure 889 */ 890 #define sSetData7(ChP) \ 891 { \ 892 (ChP)->TxControl[2] &= ~DATA8BIT; \ 893 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 894 } 895 896 /*************************************************************************** 897 Function: sSetData8 898 Purpose: Set data bits to 8 899 Call: sSetData8(ChP) 900 CHANNEL_T *ChP; Ptr to channel structure 901 */ 902 #define sSetData8(ChP) \ 903 { \ 904 (ChP)->TxControl[2] |= DATA8BIT; \ 905 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 906 } 907 908 /*************************************************************************** 909 Function: sSetDTR 910 Purpose: Set the DTR output 911 Call: sSetDTR(ChP) 912 CHANNEL_T *ChP; Ptr to channel structure 913 */ 914 #define sSetDTR(ChP) \ 915 { \ 916 (ChP)->TxControl[3] |= SET_DTR; \ 917 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 918 } 919 920 /*************************************************************************** 921 Function: sSetEvenParity 922 Purpose: Set even parity 923 Call: sSetEvenParity(ChP) 924 CHANNEL_T *ChP; Ptr to channel structure 925 Comments: Function sSetParity() can be used in place of functions sEnParity(), 926 sDisParity(), sSetOddParity(), and sSetEvenParity(). 927 928 Warnings: This function has no effect unless parity is enabled with function 929 sEnParity(). 930 */ 931 #define sSetEvenParity(ChP) \ 932 { \ 933 (ChP)->TxControl[2] |= EVEN_PAR; \ 934 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 935 } 936 937 /*************************************************************************** 938 Function: sSetOddParity 939 Purpose: Set odd parity 940 Call: sSetOddParity(ChP) 941 CHANNEL_T *ChP; Ptr to channel structure 942 Comments: Function sSetParity() can be used in place of functions sEnParity(), 943 sDisParity(), sSetOddParity(), and sSetEvenParity(). 944 945 Warnings: This function has no effect unless parity is enabled with function 946 sEnParity(). 947 */ 948 #define sSetOddParity(ChP) \ 949 { \ 950 (ChP)->TxControl[2] &= ~EVEN_PAR; \ 951 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 952 } 953 954 /*************************************************************************** 955 Function: sSetRTS 956 Purpose: Set the RTS output 957 Call: sSetRTS(ChP) 958 CHANNEL_T *ChP; Ptr to channel structure 959 */ 960 #define sSetRTS(ChP) \ 961 { \ 962 (ChP)->TxControl[3] |= SET_RTS; \ 963 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 964 } 965 966 /*************************************************************************** 967 Function: sSetRxTrigger 968 Purpose: Set the Rx FIFO trigger level 969 Call: sSetRxProcessor(ChP,Level) 970 CHANNEL_T *ChP; Ptr to channel structure 971 Byte_t Level; Number of characters in Rx FIFO at which the 972 interrupt will be generated. Can be any of the following flags: 973 974 TRIG_NO: no trigger 975 TRIG_1: 1 character in FIFO 976 TRIG_1_2: FIFO 1/2 full 977 TRIG_7_8: FIFO 7/8 full 978 Comments: An interrupt will be generated when the trigger level is reached 979 only if function sEnInterrupt() has been called with flag 980 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification 981 register will be set whenever the trigger level is reached 982 regardless of the setting of RXINT_EN. 983 984 */ 985 #define sSetRxTrigger(ChP,LEVEL) \ 986 { \ 987 (ChP)->RxControl[2] &= ~TRIG_MASK; \ 988 (ChP)->RxControl[2] |= LEVEL; \ 989 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ 990 } 991 992 /*************************************************************************** 993 Function: sSetStop1 994 Purpose: Set stop bits to 1 995 Call: sSetStop1(ChP) 996 CHANNEL_T *ChP; Ptr to channel structure 997 */ 998 #define sSetStop1(ChP) \ 999 { \ 1000 (ChP)->TxControl[2] &= ~STOP2; \ 1001 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 1002 } 1003 1004 /*************************************************************************** 1005 Function: sSetStop2 1006 Purpose: Set stop bits to 2 1007 Call: sSetStop2(ChP) 1008 CHANNEL_T *ChP; Ptr to channel structure 1009 */ 1010 #define sSetStop2(ChP) \ 1011 { \ 1012 (ChP)->TxControl[2] |= STOP2; \ 1013 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ 1014 } 1015 1016 /*************************************************************************** 1017 Function: sSetTxXOFFChar 1018 Purpose: Set the Tx XOFF flow control character 1019 Call: sSetTxXOFFChar(ChP,Ch) 1020 CHANNEL_T *ChP; Ptr to channel structure 1021 Byte_t Ch; The value to set the Tx XOFF character to 1022 */ 1023 #define sSetTxXOFFChar(ChP,CH) \ 1024 { \ 1025 (ChP)->R[0x07] = (CH); \ 1026 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ 1027 } 1028 1029 /*************************************************************************** 1030 Function: sSetTxXONChar 1031 Purpose: Set the Tx XON flow control character 1032 Call: sSetTxXONChar(ChP,Ch) 1033 CHANNEL_T *ChP; Ptr to channel structure 1034 Byte_t Ch; The value to set the Tx XON character to 1035 */ 1036 #define sSetTxXONChar(ChP,CH) \ 1037 { \ 1038 (ChP)->R[0x0b] = (CH); \ 1039 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \ 1040 } 1041 1042 /*************************************************************************** 1043 Function: sStartRxProcessor 1044 Purpose: Start a channel's receive processor 1045 Call: sStartRxProcessor(ChP) 1046 CHANNEL_T *ChP; Ptr to channel structure 1047 Comments: This function is used to start a Rx processor after it was 1048 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It 1049 will restart both the Rx processor and software input flow control. 1050 1051 */ 1052 #define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0]) 1053 1054 /*************************************************************************** 1055 Function: sWriteTxByte 1056 Purpose: Write a transmit data byte to a channel. 1057 ByteIO_t io: Channel transmit register I/O address. This can 1058 be obtained with sGetTxRxDataIO(). 1059 Byte_t Data; The transmit data byte. 1060 Warnings: This function writes the data byte without checking to see if 1061 sMaxTxSize is exceeded in the Tx FIFO. 1062 */ 1063 #define sWriteTxByte(IO,DATA) sOutB(IO,DATA) 1064 1065 int sInitController( CONTROLLER_T *CtlP, 1066 int CtlNum, 1067 ByteIO_t MudbacIO, 1068 ByteIO_t *AiopIOList, 1069 int AiopIOListSize, 1070 int IRQNum, 1071 Byte_t Frequency, 1072 int PeriodicOnly); 1073 1074 int sPCIInitController( CONTROLLER_T *CtlP, 1075 int CtlNum, 1076 ByteIO_t *AiopIOList, 1077 int AiopIOListSize, 1078 int IRQNum, 1079 Byte_t Frequency, 1080 int PeriodicOnly); 1081 1082 int sReadAiopID(ByteIO_t io); 1083 int sReadAiopNumChan(WordIO_t io); 1084 int sInitChan( CONTROLLER_T *CtlP, 1085 CHANNEL_T *ChP, 1086 int AiopNum, 1087 int ChanNum); 1088 Byte_t sGetRxErrStatus(CHANNEL_T *ChP); 1089 void sStopRxProcessor(CHANNEL_T *ChP); 1090 void sStopSWInFlowCtl(CHANNEL_T *ChP); 1091 void sFlushRxFIFO(CHANNEL_T *ChP); 1092 void sFlushTxFIFO(CHANNEL_T *ChP); 1093 int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data); 1094 void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags); 1095 void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags); 1096 1097 extern Byte_t R[RDATASIZE]; 1098 extern CONTROLLER_T sController[CTL_SIZE]; 1099 extern Byte_t sIRQMap[16]; 1100 extern Byte_t sBitMapClrTbl[8]; 1101 extern Byte_t sBitMapSetTbl[8]; 1102 extern int sClockPrescale; 1103 1104 1105 /* 1106 * Begin Linux specific definitions for the Rocketport driver 1107 * 1108 * This code is Copyright Theodore Ts'o, 1995-1997 1109 */ 1110 1111 struct r_port { 1112 int magic; 1113 int line; 1114 int flags; 1115 int count; 1116 int blocked_open; 1117 struct tty_struct *tty; 1118 int board:2; 1119 int aiop:2; 1120 int chan:3; 1121 CONTROLLER_t *ctlp; 1122 CHANNEL_t channel; 1123 int closing_wait; 1124 int close_delay; 1125 int intmask; 1126 int xmit_fifo_room; /* room in xmit fifo */ 1127 unsigned char *xmit_buf; 1128 int xmit_head; 1129 int xmit_tail; 1130 int xmit_cnt; 1131 int session; 1132 int pgrp; 1133 int cd_status; 1134 int ignore_status_mask; 1135 int read_status_mask; 1136 int cps; 1137 struct termios normal_termios; 1138 struct termios callout_termios; 1139 struct tq_struct tqueue; 1140 wait_queue_head_t open_wait; 1141 wait_queue_head_t close_wait; 1142 }; 1143 1144 #define RPORT_MAGIC 0x525001 1145 1146 #define NUM_BOARDS 8 1147 #define MAX_RP_PORTS (32*NUM_BOARDS) 1148 1149 /* 1150 * The size of the xmit buffer is 1 page, or 4096 bytes 1151 */ 1152 #define XMIT_BUF_SIZE 4096 1153 1154 /* number of characters left in xmit buffer before we ask for more */ 1155 #define WAKEUP_CHARS 256 1156 1157 /* Internal flags used only by the rocketport driver */ 1158 #define ROCKET_INITIALIZED 0x80000000 /* Port is active */ 1159 #define ROCKET_CLOSING 0x40000000 /* Serial port is closing */ 1160 #define ROCKET_NORMAL_ACTIVE 0x20000000 /* Normal port is active */ 1161 #define ROCKET_CALLOUT_ACTIVE 0x10000000 /* Callout port is active */ 1162 1163 /* 1164 * tty subtypes 1165 * 1166 */ 1167 #define SERIAL_TYPE_NORMAL 1 1168 #define SERIAL_TYPE_CALLOUT 2 1169 1170 /* 1171 * Assigned major numbers for the Comtrol Rocketport 1172 */ 1173 #define TTY_ROCKET_MAJOR 46 1174 #define CUA_ROCKET_MAJOR 47 1175 1176 /* 1177 * Utility function. 1178 */ 1179 #ifndef MIN 1180 #define MIN(a,b) ((a) < (b) ? (a) : (b)) 1181 #endif 1182 1183 #ifdef PCI_VENDOR_ID_RP 1184 #undef PCI_VENDOR_ID_RP 1185 #undef PCI_DEVICE_ID_RP8OCTA 1186 #undef PCI_DEVICE_ID_RP8INTF 1187 #undef PCI_DEVICE_ID_RP16INTF 1188 #undef PCI_DEVICE_ID_RP32INTF 1189 #endif 1190 1191 #define PCI_VENDOR_ID_RP 0x11fe 1192 #define PCI_DEVICE_ID_RP32INTF 0x0001 1193 #define PCI_DEVICE_ID_RP8INTF 0x0002 1194 #define PCI_DEVICE_ID_RP16INTF 0x0003 1195 #define PCI_DEVICE_ID_RP8OCTA 0x0005 1196 1197 #ifndef PCI_DEVICE_ID_RP4QUAD 1198 #define PCI_DEVICE_ID_RP4QUAD 0x0004 1199 #endif 1200 #ifndef PCI_DEVICE_ID_RP8J 1201 #define PCI_DEVICE_ID_RP8J 0x0006 1202 #endif 1203 #ifndef PCI_DEVICE_ID_RP4J 1204 #define PCI_DEVICE_ID_RP4J 0x0007 1205 #endif 1206 #ifndef PCI_DEVICE_ID_RPP4 1207 #define PCI_DEVICE_ID_RPP4 0x000A 1208 #endif 1209 #ifndef PCI_DEVICE_ID_RPP8 1210 #define PCI_DEVICE_ID_RPP8 0x000B 1211 #endif 1212 #ifndef PCI_DEVICE_ID_RP8M 1213 #define PCI_DEVICE_ID_RP8M 0x000C 1214 #endif 1215 1216