1 /*  D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2 /*
3     Copyright (c) 2001, 2002 by D-Link Corporation
4     Written by Edward Peng.<edward_peng@dlink.com.tw>
5     Created 03-May-2001, base on Linux' sundance.c.
6 
7     This program is free software; you can redistribute it and/or modify
8     it under the terms of the GNU General Public License as published by
9     the Free Software Foundation; either version 2 of the License, or
10     (at your option) any later version.
11 */
12 
13 #ifndef __DL2K_H__
14 #define __DL2K_H__
15 
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/string.h>
19 #include <linux/timer.h>
20 #include <linux/errno.h>
21 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/init.h>
29 #include <linux/ethtool.h>
30 #include <asm/processor.h>	/* Processor type for cache alignment. */
31 #include <asm/bitops.h>
32 #include <asm/io.h>
33 #include <asm/uaccess.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
36 #include <linux/time.h>
37 #ifdef DL2K_COMPAT_WITH_OLD_KERNEL
38 #include "crc32.h"
39 #else
40 #include <linux/crc32.h>
41 #endif
42 
43 
44 
45 #define TX_RING_SIZE	256
46 #define TX_QUEUE_LEN	(TX_RING_SIZE - 10) /* Limit ring entries actually used.*/
47 #define RX_RING_SIZE 	256
48 #define TX_TOTAL_SIZE	TX_RING_SIZE*sizeof(struct netdev_desc)
49 #define RX_TOTAL_SIZE	RX_RING_SIZE*sizeof(struct netdev_desc)
50 
51 /* This driver was written to use PCI memory space, however x86-oriented
52    hardware often uses I/O space accesses. */
53 #ifndef MEM_MAPPING
54 #undef readb
55 #undef readw
56 #undef readl
57 #undef writeb
58 #undef writew
59 #undef writel
60 #define readb inb
61 #define readw inw
62 #define readl inl
63 #define writeb outb
64 #define writew outw
65 #define writel outl
66 #endif
67 
68 /* Offsets to the device registers.
69    Unlike software-only systems, device drivers interact with complex hardware.
70    It's not useful to define symbolic names for every register bit in the
71    device.  The name can only partially document the semantics and make
72    the driver longer and more difficult to read.
73    In general, only the important configuration values or bits changed
74    multiple times should be defined symbolically.
75 */
76 enum dl2x_offsets {
77 	/* I/O register offsets */
78 	DMACtrl = 0x00,
79 	RxDMAStatus = 0x08,
80 	TFDListPtr0 = 0x10,
81 	TFDListPtr1 = 0x14,
82 	TxDMABurstThresh = 0x18,
83 	TxDMAUrgentThresh = 0x19,
84 	TxDMAPollPeriod = 0x1a,
85 	RFDListPtr0 = 0x1c,
86 	RFDListPtr1 = 0x20,
87 	RxDMABurstThresh = 0x24,
88 	RxDMAUrgentThresh = 0x25,
89 	RxDMAPollPeriod = 0x26,
90 	RxDMAIntCtrl = 0x28,
91 	DebugCtrl = 0x2c,
92 	ASICCtrl = 0x30,
93 	FifoCtrl = 0x38,
94 	RxEarlyThresh = 0x3a,
95 	FlowOffThresh = 0x3c,
96 	FlowOnThresh = 0x3e,
97 	TxStartThresh = 0x44,
98 	EepromData = 0x48,
99 	EepromCtrl = 0x4a,
100 	ExpromAddr = 0x4c,
101 	Exprodata = 0x50,
102 	WakeEvent0x51,
103 	CountDown = 0x54,
104 	IntStatusAck = 0x5a,
105 	IntEnable = 0x5c,
106 	IntStatus = 0x5e,
107 	TxStatus = 0x60,
108 	MACCtrl = 0x6c,
109 	VLANTag = 0x70,
110 	PhyCtrl = 0x76,
111 	StationAddr0 = 0x78,
112 	StationAddr1 = 0x7a,
113 	StationAddr2 = 0x7c,
114 	VLANId = 0x80,
115 	MaxFrameSize = 0x86,
116 	ReceiveMode = 0x88,
117 	HashTable0 = 0x8c,
118 	HashTable1 = 0x90,
119 	RmonStatMask = 0x98,
120 	StatMask = 0x9c,
121 	RxJumboFrames = 0xbc,
122 	TCPCheckSumErrors = 0xc0,
123 	IPCheckSumErrors = 0xc2,
124 	UDPCheckSumErrors = 0xc4,
125 	TxJumboFrames = 0xf4,
126 	/* Ethernet MIB statistic register offsets */
127 	OctetRcvOk = 0xa8,
128 	McstOctetRcvOk = 0xac,
129 	BcstOctetRcvOk = 0xb0,
130 	FramesRcvOk = 0xb4,
131 	McstFramesRcvdOk = 0xb8,
132 	BcstFramesRcvdOk = 0xbe,
133 	MacControlFramesRcvd = 0xc6,
134 	FrameTooLongErrors = 0xc8,
135 	InRangeLengthErrors = 0xca,
136 	FramesCheckSeqErrors = 0xcc,
137 	FramesLostRxErrors = 0xce,
138 	OctetXmtOk = 0xd0,
139 	McstOctetXmtOk = 0xd4,
140 	BcstOctetXmtOk = 0xd8,
141 	FramesXmtOk = 0xdc,
142 	McstFramesXmtdOk = 0xe0,
143 	FramesWDeferredXmt = 0xe4,
144 	LateCollisions = 0xe8,
145 	MultiColFrames = 0xec,
146 	SingleColFrames = 0xf0,
147 	BcstFramesXmtdOk = 0xf6,
148 	CarrierSenseErrors = 0xf8,
149 	MacControlFramesXmtd = 0xfa,
150 	FramesAbortXSColls = 0xfc,
151 	FramesWEXDeferal = 0xfe,
152 	/* RMON statistic register offsets */
153 	EtherStatsCollisions = 0x100,
154 	EtherStatsOctetsTransmit = 0x104,
155 	EtherStatsPktsTransmit = 0x108,
156 	EtherStatsPkts64OctetTransmit = 0x10c,
157 	EtherStats65to127OctetsTransmit = 0x110,
158 	EtherStatsPkts128to255OctetsTransmit = 0x114,
159 	EtherStatsPkts256to511OctetsTransmit = 0x118,
160 	EtherStatsPkts512to1023OctetsTransmit = 0x11c,
161 	EtherStatsPkts1024to1518OctetsTransmit = 0x120,
162 	EtherStatsCRCAlignErrors = 0x124,
163 	EtherStatsUndersizePkts = 0x128,
164 	EtherStatsFragments = 0x12c,
165 	EtherStatsJabbers = 0x130,
166 	EtherStatsOctets = 0x134,
167 	EtherStatsPkts = 0x138,
168 	EtherStats64Octets = 0x13c,
169 	EtherStatsPkts65to127Octets = 0x140,
170 	EtherStatsPkts128to255Octets = 0x144,
171 	EtherStatsPkts256to511Octets = 0x148,
172 	EtherStatsPkts512to1023Octets = 0x14c,
173 	EtherStatsPkts1024to1518Octets = 0x150,
174 };
175 
176 /* Bits in the interrupt status/mask registers. */
177 enum IntStatus_bits {
178 	InterruptStatus = 0x0001,
179 	HostError = 0x0002,
180 	MACCtrlFrame = 0x0008,
181 	TxComplete = 0x0004,
182 	RxComplete = 0x0010,
183 	RxEarly = 0x0020,
184 	IntRequested = 0x0040,
185 	UpdateStats = 0x0080,
186 	LinkEvent = 0x0100,
187 	TxDMAComplete = 0x0200,
188 	RxDMAComplete = 0x0400,
189 	RFDListEnd = 0x0800,
190 	RxDMAPriority = 0x1000,
191 };
192 
193 /* Bits in the ReceiveMode register. */
194 enum ReceiveMode_bits {
195 	ReceiveUnicast = 0x0001,
196 	ReceiveMulticast = 0x0002,
197 	ReceiveBroadcast = 0x0004,
198 	ReceiveAllFrames = 0x0008,
199 	ReceiveMulticastHash = 0x0010,
200 	ReceiveIPMulticast = 0x0020,
201 	ReceiveVLANMatch = 0x0100,
202 	ReceiveVLANHash = 0x0200,
203 };
204 /* Bits in MACCtrl. */
205 enum MACCtrl_bits {
206 	DuplexSelect = 0x20,
207 	TxFlowControlEnable = 0x80,
208 	RxFlowControlEnable = 0x0100,
209 	RcvFCS = 0x200,
210 	AutoVLANtagging = 0x1000,
211 	AutoVLANuntagging = 0x2000,
212 	StatsEnable = 0x00200000,
213 	StatsDisable = 0x00400000,
214 	StatsEnabled = 0x00800000,
215 	TxEnable = 0x01000000,
216 	TxDisable = 0x02000000,
217 	TxEnabled = 0x04000000,
218 	RxEnable = 0x08000000,
219 	RxDisable = 0x10000000,
220 	RxEnabled = 0x20000000,
221 };
222 
223 enum ASICCtrl_LoWord_bits {
224 	PhyMedia = 0x0080,
225 };
226 
227 enum ASICCtrl_HiWord_bits {
228 	GlobalReset = 0x0001,
229 	RxReset = 0x0002,
230 	TxReset = 0x0004,
231 	DMAReset = 0x0008,
232 	FIFOReset = 0x0010,
233 	NetworkReset = 0x0020,
234 	HostReset = 0x0040,
235 	ResetBusy = 0x0400,
236 };
237 
238 /* Transmit Frame Control bits */
239 enum TFC_bits {
240 	DwordAlign = 0x00000000,
241 	WordAlignDisable = 0x00030000,
242 	WordAlign = 0x00020000,
243 	TCPChecksumEnable = 0x00040000,
244 	UDPChecksumEnable = 0x00080000,
245 	IPChecksumEnable = 0x00100000,
246 	FCSAppendDisable = 0x00200000,
247 	TxIndicate = 0x00400000,
248 	TxDMAIndicate = 0x00800000,
249 	FragCountShift = 24,
250 	VLANTagInsert = 0x0000000010000000,
251 	TFDDone = 0x80000000,
252 	VIDShift = 32,
253 	UsePriorityShift = 48,
254 };
255 
256 /* Receive Frames Status bits */
257 enum RFS_bits {
258 	RxFIFOOverrun = 0x00010000,
259 	RxRuntFrame = 0x00020000,
260 	RxAlignmentError = 0x00040000,
261 	RxFCSError = 0x00080000,
262 	RxOverSizedFrame = 0x00100000,
263 	RxLengthError = 0x00200000,
264 	VLANDetected = 0x00400000,
265 	TCPDetected = 0x00800000,
266 	TCPError = 0x01000000,
267 	UDPDetected = 0x02000000,
268 	UDPError = 0x04000000,
269 	IPDetected = 0x08000000,
270 	IPError = 0x10000000,
271 	FrameStart = 0x20000000,
272 	FrameEnd = 0x40000000,
273 	RFDDone = 0x80000000,
274 	TCIShift = 32,
275 	RFS_Errors = 0x003f0000,
276 };
277 
278 #define MII_RESET_TIME_OUT		10000
279 /* MII register */
280 enum _mii_reg {
281 	MII_BMCR = 0,
282 	MII_BMSR = 1,
283 	MII_PHY_ID1 = 2,
284 	MII_PHY_ID2 = 3,
285 	MII_ANAR = 4,
286 	MII_ANLPAR = 5,
287 	MII_ANER = 6,
288 	MII_ANNPT = 7,
289 	MII_ANLPRNP = 8,
290 	MII_MSCR = 9,
291 	MII_MSSR = 10,
292 	MII_ESR = 15,
293 	MII_PHY_SCR = 16,
294 };
295 /* PCS register */
296 enum _pcs_reg {
297 	PCS_BMCR = 0,
298 	PCS_BMSR = 1,
299 	PCS_ANAR = 4,
300 	PCS_ANLPAR = 5,
301 	PCS_ANER = 6,
302 	PCS_ANNPT = 7,
303 	PCS_ANLPRNP = 8,
304 	PCS_ESR = 15,
305 };
306 
307 /* Basic Mode Control Register */
308 typedef union t_MII_BMCR {
309 	u16 image;
310 	struct {
311 		u16 _bit_5_0:6;	// bit 5:0
312 		u16 speed1000:1;	// bit 6
313 		u16 col_test_enable:1;	// bit 7
314 		u16 duplex_mode:1;	// bit 8
315 		u16 restart_an:1;	// bit 9
316 		u16 isolate:1;	// bit 10
317 		u16 power_down:1;	// bit 11
318 		u16 an_enable:1;	// bit 12
319 		u16 speed100:1;	// bit 13
320 		u16 loopback:1;	// bit 14
321 		u16 reset:1;	// bit 15
322 	} bits;
323 } BMCR_t, *PBMCR_t;
324 
325 enum _mii_bmcr {
326 	MII_BMCR_RESET = 0x8000,
327 	MII_BMCR_LOOP_BACK = 0x4000,
328 	MII_BMCR_SPEED_LSB = 0x2000,
329 	MII_BMCR_AN_ENABLE = 0x1000,
330 	MII_BMCR_POWER_DOWN = 0x0800,
331 	MII_BMCR_ISOLATE = 0x0400,
332 	MII_BMCR_RESTART_AN = 0x0200,
333 	MII_BMCR_DUPLEX_MODE = 0x0100,
334 	MII_BMCR_COL_TEST = 0x0080,
335 	MII_BMCR_SPEED_MSB = 0x0040,
336 	MII_BMCR_SPEED_RESERVED = 0x003f,
337 	MII_BMCR_SPEED_10 = 0,
338 	MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB,
339 	MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB,
340 };
341 
342 /* Basic Mode Status Register */
343 typedef union t_MII_BMSR {
344 	u16 image;
345 	struct {
346 		u16 ext_capability:1;	// bit 0
347 		u16 japper_detect:1;	// bit 1
348 		u16 link_status:1;	// bit 2
349 		u16 an_ability:1;	// bit 3
350 		u16 remote_fault:1;	// bit 4
351 		u16 an_complete:1;	// bit 5
352 		u16 preamble_supp:1;	// bit 6
353 		u16 _bit_7:1;	// bit 7
354 		u16 ext_status:1;	// bit 8
355 		u16 media_100BT2_HD:1;	// bit 9
356 		u16 media_100BT2_FD:1;	// bit 10
357 		u16 media_10BT_HD:1;	// bit 11
358 		u16 media_10BT_FD:1;	// bit 12
359 		u16 media_100BX_HD:1;	// bit 13
360 		u16 media_100BX_FD:1;	// bit 14
361 		u16 media_100BT4:1;	// bit 15
362 	} bits;
363 } BMSR_t, *PBMSR_t;
364 
365 enum _mii_bmsr {
366 	MII_BMSR_100BT4 = 0x8000,
367 	MII_BMSR_100BX_FD = 0x4000,
368 	MII_BMSR_100BX_HD = 0x2000,
369 	MII_BMSR_10BT_FD = 0x1000,
370 	MII_BMSR_10BT_HD = 0x0800,
371 	MII_BMSR_100BT2_FD = 0x0400,
372 	MII_BMSR_100BT2_HD = 0x0200,
373 	MII_BMSR_EXT_STATUS = 0x0100,
374 	MII_BMSR_PREAMBLE_SUPP = 0x0040,
375 	MII_BMSR_AN_COMPLETE = 0x0020,
376 	MII_BMSR_REMOTE_FAULT = 0x0010,
377 	MII_BMSR_AN_ABILITY = 0x0008,
378 	MII_BMSR_LINK_STATUS = 0x0004,
379 	MII_BMSR_JABBER_DETECT = 0x0002,
380 	MII_BMSR_EXT_CAP = 0x0001,
381 };
382 
383 /* ANAR */
384 typedef union t_MII_ANAR {
385 	u16 image;
386 	struct {
387 		u16 selector:5;	// bit 4:0
388 		u16 media_10BT_HD:1;	// bit 5
389 		u16 media_10BT_FD:1;	// bit 6
390 		u16 media_100BX_HD:1;	// bit 7
391 		u16 media_100BX_FD:1;	// bit 8
392 		u16 media_100BT4:1;	// bit 9
393 		u16 pause:1;	// bit 10
394 		u16 asymmetric:1;	// bit 11
395 		u16 _bit12:1;	// bit 12
396 		u16 remote_fault:1;	// bit 13
397 		u16 _bit14:1;	// bit 14
398 		u16 next_page:1;	// bit 15
399 	} bits;
400 } ANAR_t, *PANAR_t;
401 
402 enum _mii_anar {
403 	MII_ANAR_NEXT_PAGE = 0x8000,
404 	MII_ANAR_REMOTE_FAULT = 0x4000,
405 	MII_ANAR_ASYMMETRIC = 0x0800,
406 	MII_ANAR_PAUSE = 0x0400,
407 	MII_ANAR_100BT4 = 0x0200,
408 	MII_ANAR_100BX_FD = 0x0100,
409 	MII_ANAR_100BX_HD = 0x0080,
410 	MII_ANAR_10BT_FD = 0x0020,
411 	MII_ANAR_10BT_HD = 0x0010,
412 	MII_ANAR_SELECTOR = 0x001f,
413 	MII_IEEE8023_CSMACD = 0x0001,
414 };
415 
416 /* ANLPAR */
417 typedef union t_MII_ANLPAR {
418 	u16 image;
419 	struct {
420 		u16 selector:5;	// bit 4:0
421 		u16 media_10BT_HD:1;	// bit 5
422 		u16 media_10BT_FD:1;	// bit 6
423 		u16 media_100BX_HD:1;	// bit 7
424 		u16 media_100BX_FD:1;	// bit 8
425 		u16 media_100BT4:1;	// bit 9
426 		u16 pause:1;	// bit 10
427 		u16 asymmetric:1;	// bit 11
428 		u16 _bit12:1;	// bit 12
429 		u16 remote_fault:1;	// bit 13
430 		u16 _bit14:1;	// bit 14
431 		u16 next_page:1;	// bit 15
432 	} bits;
433 } ANLPAR_t, *PANLPAR_t;
434 
435 enum _mii_anlpar {
436 	MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE,
437 	MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT,
438 	MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC,
439 	MII_ANLPAR_PAUSE = MII_ANAR_PAUSE,
440 	MII_ANLPAR_100BT4 = MII_ANAR_100BT4,
441 	MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD,
442 	MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD,
443 	MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD,
444 	MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD,
445 	MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR,
446 };
447 
448 /* Auto-Negotiation Expansion Register */
449 typedef union t_MII_ANER {
450 	u16 image;
451 	struct {
452 		u16 lp_negotiable:1;	// bit 0
453 		u16 page_received:1;	// bit 1
454 		u16 nextpagable:1;	// bit 2
455 		u16 lp_nextpagable:1;	// bit 3
456 		u16 pdetect_fault:1;	// bit 4
457 		u16 _bit15_5:11;	// bit 15:5
458 	} bits;
459 } ANER_t, *PANER_t;
460 
461 enum _mii_aner {
462 	MII_ANER_PAR_DETECT_FAULT = 0x0010,
463 	MII_ANER_LP_NEXTPAGABLE = 0x0008,
464 	MII_ANER_NETXTPAGABLE = 0x0004,
465 	MII_ANER_PAGE_RECEIVED = 0x0002,
466 	MII_ANER_LP_NEGOTIABLE = 0x0001,
467 };
468 
469 /* MASTER-SLAVE Control Register */
470 typedef union t_MII_MSCR {
471 	u16 image;
472 	struct {
473 		u16 _bit_7_0:8;	// bit 7:0
474 		u16 media_1000BT_HD:1;	// bit 8
475 		u16 media_1000BT_FD:1;	// bit 9
476 		u16 port_type:1;	// bit 10
477 		u16 cfg_value:1;	// bit 11
478 		u16 cfg_enable:1;	// bit 12
479 		u16 test_mode:3;	// bit 15:13
480 	} bits;
481 } MSCR_t, *PMSCR_t;
482 
483 enum _mii_mscr {
484 	MII_MSCR_TEST_MODE = 0xe000,
485 	MII_MSCR_CFG_ENABLE = 0x1000,
486 	MII_MSCR_CFG_VALUE = 0x0800,
487 	MII_MSCR_PORT_VALUE = 0x0400,
488 	MII_MSCR_1000BT_FD = 0x0200,
489 	MII_MSCR_1000BT_HD = 0X0100,
490 };
491 
492 /* MASTER-SLAVE Status Register */
493 typedef union t_MII_MSSR {
494 	u16 image;
495 	struct {
496 		u16 idle_err_count:8;	// bit 7:0
497 		u16 _bit_9_8:2;	// bit 9:8
498 		u16 lp_1000BT_HD:1;	// bit 10
499 		u16 lp_1000BT_FD:1;	// bit 11
500 		u16 remote_rcv_status:1;	// bit 12
501 		u16 local_rcv_status:1;	// bit 13
502 		u16 cfg_resolution:1;	// bit 14
503 		u16 cfg_fault:1;	// bit 15
504 	} bits;
505 } MSSR_t, *PMSSR_t;
506 
507 enum _mii_mssr {
508 	MII_MSSR_CFG_FAULT = 0x8000,
509 	MII_MSSR_CFG_RES = 0x4000,
510 	MII_MSSR_LOCAL_RCV_STATUS = 0x2000,
511 	MII_MSSR_REMOTE_RCVR = 0x1000,
512 	MII_MSSR_LP_1000BT_HD = 0x0800,
513 	MII_MSSR_LP_1000BT_FD = 0x0400,
514 	MII_MSSR_IDLE_ERR_COUNT = 0x00ff,
515 };
516 
517 /* IEEE Extened Status Register */
518 typedef union t_MII_ESR {
519 	u16 image;
520 	struct {
521 		u16 _bit_11_0:12;	// bit 11:0
522 		u16 media_1000BT_HD:1;	// bit 12
523 		u16 media_1000BT_FD:1;	// bit 13
524 		u16 media_1000BX_HD:1;	// bit 14
525 		u16 media_1000BX_FD:1;	// bit 15
526 	} bits;
527 } ESR_t, *PESR_t;
528 
529 enum _mii_esr {
530 	MII_ESR_1000BX_FD = 0x8000,
531 	MII_ESR_1000BX_HD = 0x4000,
532 	MII_ESR_1000BT_FD = 0x2000,
533 	MII_ESR_1000BT_HD = 0x1000,
534 };
535 /* PHY Specific Control Register */
536 typedef union t_MII_PHY_SCR {
537 	u16 image;
538 	struct {
539 		u16 disable_jabber:1;	// bit 0
540 		u16 polarity_reversal:1;	// bit 1
541 		u16 SEQ_test:1;	// bit 2
542 		u16 _bit_3:1;	// bit 3
543 		u16 disable_CLK125:1;	// bit 4
544 		u16 mdi_crossover_mode:2;	// bit 6:5
545 		u16 enable_ext_dist:1;	// bit 7
546 		u16 _bit_8_9:2;	// bit 9:8
547 		u16 force_link:1;	// bit 10
548 		u16 assert_CRS:1;	// bit 11
549 		u16 rcv_fifo_depth:2;	// bit 13:12
550 		u16 xmit_fifo_depth:2;	// bit 15:14
551 	} bits;
552 } PHY_SCR_t, *PPHY_SCR_t;
553 
554 typedef enum t_MII_ADMIN_STATUS {
555 	adm_reset,
556 	adm_operational,
557 	adm_loopback,
558 	adm_power_down,
559 	adm_isolate
560 } MII_ADMIN_t, *PMII_ADMIN_t;
561 
562 /* Physical Coding Sublayer Management (PCS) */
563 /* PCS control and status registers bitmap as the same as MII */
564 /* PCS Extended Status register bitmap as the same as MII */
565 /* PCS ANAR */
566 typedef union t_PCS_ANAR {
567 	u16 image;
568 	struct {
569 		u16 _bit_4_0:5;		// bit 4:0
570 		u16 full_duplex:1;	// bit 5
571 		u16 half_duplex:1;	// bit 6
572 		u16 asymmetric:1;	// bit 7
573 		u16 pause:1;		// bit 8
574 		u16 _bit_11_9:3;	// bit 11:9
575 		u16 remote_fault:2;	// bit 13:12
576 		u16 _bit_14:1;		// bit 14
577 		u16 next_page:1;	// bit 15
578 	} bits;
579 } ANAR_PCS_t, *PANAR_PCS_t;
580 
581 enum _pcs_anar {
582 	PCS_ANAR_NEXT_PAGE = 0x8000,
583 	PCS_ANAR_REMOTE_FAULT = 0x3000,
584 	PCS_ANAR_ASYMMETRIC = 0x0100,
585 	PCS_ANAR_PAUSE = 0x0080,
586 	PCS_ANAR_HALF_DUPLEX = 0x0040,
587 	PCS_ANAR_FULL_DUPLEX = 0x0020,
588 };
589 /* PCS ANLPAR */
590 typedef union t_PCS_ANLPAR {
591 	u16 image;
592 	struct {
593 		u16 _bit_4_0:5;		// bit 4:0
594 		u16 full_duplex:1;	// bit 5
595 		u16 half_duplex:1;	// bit 6
596 		u16 asymmetric:1;	// bit 7
597 		u16 pause:1;		// bit 8
598 		u16 _bit_11_9:3;	// bit 11:9
599 		u16 remote_fault:2;	// bit 13:12
600 		u16 _bit_14:1;		// bit 14
601 		u16 next_page:1;	// bit 15
602 	} bits;
603 } ANLPAR_PCS_t, *PANLPAR_PCS_t;
604 
605 enum _pcs_anlpar {
606 	PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE,
607 	PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
608 	PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC,
609 	PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE,
610 	PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX,
611 	PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX,
612 };
613 
614 typedef struct t_SROM {
615 	u16 config_param;	/* 0x00 */
616 	u16 asic_ctrl;		/* 0x02 */
617 	u16 sub_vendor_id;	/* 0x04 */
618 	u16 sub_system_id;	/* 0x06 */
619 	u16 reserved1[12];	/* 0x08-0x1f */
620 	u8 mac_addr[6];		/* 0x20-0x25 */
621 	u8 reserved2[10];	/* 0x26-0x2f */
622 	u8 sib[204];		/* 0x30-0xfb */
623 	u32 crc;		/* 0xfc-0xff */
624 } SROM_t, *PSROM_t;
625 
626 /* Ioctl custom data */
627 struct ioctl_data {
628 	char signature[10];
629 	int cmd;
630 	int len;
631 	char *data;
632 };
633 
634 struct mii_data {
635 	__u16 reserved;
636 	__u16 reg_num;
637 	__u16 in_value;
638 	__u16 out_value;
639 };
640 
641 /* The Rx and Tx buffer descriptors. */
642 struct netdev_desc {
643 	u64 next_desc;
644 	u64 status;
645 	u64 fraginfo;
646 };
647 
648 #define PRIV_ALIGN	15	/* Required alignment mask */
649 /* Use  __attribute__((aligned (L1_CACHE_BYTES)))  to maintain alignment
650    within the structure. */
651 struct netdev_private {
652 	/* Descriptor rings first for alignment. */
653 	struct netdev_desc *rx_ring;
654 	struct netdev_desc *tx_ring;
655 	struct sk_buff *rx_skbuff[RX_RING_SIZE];
656 	struct sk_buff *tx_skbuff[TX_RING_SIZE];
657 	dma_addr_t tx_ring_dma;
658 	dma_addr_t rx_ring_dma;
659 	struct pci_dev *pdev;
660 	spinlock_t tx_lock;
661 	spinlock_t rx_lock;
662 	struct net_device_stats stats;
663 	unsigned int rx_buf_sz;		/* Based on MTU+slack. */
664 	unsigned int speed;		/* Operating speed */
665 	struct tasklet_struct tx_tasklet;
666 	struct tasklet_struct rx_tasklet;
667 	unsigned int vlan;		/* VLAN Id */
668 	unsigned int chip_id;		/* PCI table chip id */
669 	unsigned int rx_coalesce; 	/* Maximum frames each RxDMAComplete intr */
670 	unsigned int rx_timeout; 	/* Wait time between RxDMAComplete intr */
671 	unsigned int tx_coalesce;	/* Maximum frames each tx interrupt */
672 	unsigned int full_duplex:1;	/* Full-duplex operation requested. */
673 	unsigned int an_enable:2;	/* Auto-Negotiated Enable */
674 	unsigned int jumbo:1;		/* Jumbo frame enable */
675 	unsigned int coalesce:1;	/* Rx coalescing enable */
676 	unsigned int tx_flow:1;		/* Tx flow control enable */
677 	unsigned int rx_flow:1;		/* Rx flow control enable */
678 	unsigned int phy_media:1;	/* 1: fiber, 0: copper */
679 	unsigned int link_status:1;	/* Current link status */
680 	unsigned char pci_rev_id;	/* PCI revision ID */
681 	struct netdev_desc *last_tx;	/* Last Tx descriptor used. */
682 	unsigned long cur_rx, old_rx;	/* Producer/consumer ring indices */
683 	unsigned long cur_tx, old_tx;
684 	unsigned long cur_task;
685 	atomic_t tx_desc_lock;
686 	int budget;
687 	struct timer_list timer;
688 	int wake_polarity;
689 	char name[256];		/* net device description */
690 	u8 duplex_polarity;
691 	u16 mcast_filter[4];
692 	u16 advertising;	/* NWay media advertisement */
693 	u16 negotiate;		/* Negotiated media */
694 	int phy_addr;		/* PHY addresses. */
695 };
696 
697 /* The station address location in the EEPROM. */
698 #ifdef MEM_MAPPING
699 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
700 #else
701 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO  | PCI_ADDR0)
702 #endif
703 /* The struct pci_device_id consist of:
704         vendor, device          Vendor and device ID to match (or PCI_ANY_ID)
705         subvendor, subdevice    Subsystem vendor and device ID to match (or PCI_ANY_ID)
706         class                   Device class to match. The class_mask tells which bits
707         class_mask              of the class are honored during the comparison.
708         driver_data             Data private to the driver.
709 */
710 static struct pci_device_id rio_pci_tbl[] __devinitdata = {
711 	{0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
712 	{0,}
713 };
714 MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
715 #define TX_TIMEOUT  (4*HZ)
716 #define PACKET_SIZE		1536
717 #define MAX_JUMBO		8000
718 #define RIO_IO_SIZE             340
719 #define DEFAULT_RXC		5
720 #define DEFAULT_RXT		750
721 #define DEFAULT_TXC		1
722 #define MAX_TXC			8
723 #define RX_BUDGET		RX_RING_SIZE/2
724 #endif				/* __DL2K_H__ */
725