1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_
14 #define ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_
15 
16 /*
17  *****************************************
18  *   DCORE0_TPC0_CFG_KERNEL_TENSOR_0
19  *   (Prototype: TPC_TENSOR)
20  *****************************************
21  */
22 
23 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0x400B000
24 
25 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0x400B004
26 
27 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0x400B008
28 
29 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0x400B00C
30 
31 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0x400B010
32 
33 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0x400B014
34 
35 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0x400B018
36 
37 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0x400B01C
38 
39 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0x400B020
40 
41 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0x400B024
42 
43 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0x400B028
44 
45 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0x400B02C
46 
47 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0x400B030
48 
49 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0x400B034
50 
51 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE 0x400B038
52 
53 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x400B03C
54 
55 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x400B040
56 
57 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x400B044
58 
59 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x400B048
60 
61 #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x400B04C
62 
63 #endif /* ASIC_REG_DCORE0_TPC0_CFG_KERNEL_TENSOR_0_REGS_H_ */
64