1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ 14 #define ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_HMMU0_MMU 19 * (Prototype: MMU) 20 ***************************************** 21 */ 22 23 /* DCORE0_HMMU0_MMU_MMU_ENABLE */ 24 #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_SHIFT 0 25 #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_MASK 0x1 26 27 /* DCORE0_HMMU0_MMU_FORCE_ORDERING */ 28 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_SHIFT 0 29 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_MASK 0x1 30 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_SHIFT 1 31 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_MASK 0x2 32 33 /* DCORE0_HMMU0_MMU_FEATURE_ENABLE */ 34 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0 35 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1 36 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1 37 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2 38 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2 39 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4 40 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3 41 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8 42 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4 43 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10 44 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5 45 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20 46 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_SHIFT 6 47 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_EV_MMU_OR_STLB_MASK 0x40 48 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_SHIFT 7 49 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_TRACE_CLKH_EQUAL_CLKL_MASK 0x80 50 51 /* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7 */ 52 #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_SHIFT 0 53 #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_38_7_R_MASK 0xFFFFFFFF 54 55 /* DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39 */ 56 #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_SHIFT 0 57 #define DCORE0_HMMU0_MMU_VA_ORDERING_MASK_64_39_R_MASK 0x3FFFFFF 58 59 /* DCORE0_HMMU0_MMU_LOG2_DDR_SIZE */ 60 #define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_SHIFT 0 61 #define DCORE0_HMMU0_MMU_LOG2_DDR_SIZE_R_MASK 0xFF 62 63 /* DCORE0_HMMU0_MMU_SCRAMBLER */ 64 #define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_SHIFT 0 65 #define DCORE0_HMMU0_MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F 66 #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6 67 #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40 68 #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7 69 #define DCORE0_HMMU0_MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80 70 #define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_SHIFT 8 71 #define DCORE0_HMMU0_MMU_SCRAMBLER_DDR_CH_LSB_BIT_LOCATION_MASK 0x7F00 72 73 /* DCORE0_HMMU0_MMU_MEM_INIT_BUSY */ 74 #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_SHIFT 0 75 #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_DATA_MASK 0x3 76 #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_SHIFT 2 77 #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI0_MASK 0x4 78 #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_SHIFT 3 79 #define DCORE0_HMMU0_MMU_MEM_INIT_BUSY_OBI1_MASK 0x8 80 81 /* DCORE0_HMMU0_MMU_SPI_SEI_MASK */ 82 #define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_SHIFT 0 83 #define DCORE0_HMMU0_MMU_SPI_SEI_MASK_R_MASK 0x7FFFF 84 85 /* DCORE0_HMMU0_MMU_SPI_SEI_CAUSE */ 86 #define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_SHIFT 0 87 #define DCORE0_HMMU0_MMU_SPI_SEI_CAUSE_R_MASK 0x7FFFF 88 89 /* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE */ 90 #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_SHIFT 0 91 #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF 92 93 /* DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA */ 94 #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 95 #define DCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF 96 97 /* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE */ 98 #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_SHIFT 0 99 #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_63_32_MASK 0xFFFFFFFF 100 101 /* DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA */ 102 #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 103 #define DCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF 104 105 /* DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID */ 106 #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_SHIFT 0 107 #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_PAGE_ERR_VALID_ENTRY_MASK 0x1 108 #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_SHIFT 1 109 #define DCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID_ACCESS_ERR_VALID_ENTRY_MASK 0x2 110 111 /* DCORE0_HMMU0_MMU_INTERRUPT_CLR */ 112 #define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_SHIFT 0 113 #define DCORE0_HMMU0_MMU_INTERRUPT_CLR_R_MASK 0xFFFFFFFF 114 115 /* DCORE0_HMMU0_MMU_INTERRUPT_MASK */ 116 #define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_SHIFT 0 117 #define DCORE0_HMMU0_MMU_INTERRUPT_MASK_R_MASK 0xFF 118 119 /* DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM */ 120 #define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_SHIFT 0 121 #define DCORE0_HMMU0_MMU_DBG_MEM_WRAP_RM_R_MASK 0x3FFFFFFF 122 123 /* DCORE0_HMMU0_MMU_SPI_CAUSE_CLR */ 124 #define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_SHIFT 0 125 #define DCORE0_HMMU0_MMU_SPI_CAUSE_CLR_CLR_MASK 0x1 126 127 /* DCORE0_HMMU0_MMU_PIPE_CREDIT */ 128 #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_SHIFT 0 129 #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_CREDIT_MASK 0xF 130 #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_SHIFT 7 131 #define DCORE0_HMMU0_MMU_PIPE_CREDIT_READ_FORCE_FULL_MASK 0x80 132 #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_SHIFT 8 133 #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_CREDIT_MASK 0xF00 134 #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_SHIFT 15 135 #define DCORE0_HMMU0_MMU_PIPE_CREDIT_WRITE_FORCE_FULL_MASK 0x8000 136 137 /* DCORE0_HMMU0_MMU_MMU_BYPASS */ 138 #define DCORE0_HMMU0_MMU_MMU_BYPASS_R_SHIFT 0 139 #define DCORE0_HMMU0_MMU_MMU_BYPASS_R_MASK 0x1 140 141 /* DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE */ 142 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_SHIFT 0 143 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP5_PAGE_SIZE_MASK 0xF 144 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_SHIFT 4 145 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK 0xF0 146 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_SHIFT 8 147 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP3_PAGE_SIZE_MASK 0xF00 148 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_SHIFT 12 149 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP2_PAGE_SIZE_MASK 0xF000 150 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_SHIFT 16 151 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_MASK 0xF0000 152 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_SHIFT 20 153 #define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK 0x100000 154 155 /* DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG */ 156 #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_SHIFT 0 157 #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_MASK 0x1FF 158 #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_SHIFT 10 159 #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MIN_MASK 0x7FC00 160 #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_SHIFT 20 161 #define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MAX_MASK 0x1FF00000 162 163 /* DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT */ 164 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_SHIFT 0 165 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_WRITE_CRED_MASK 0x1FF 166 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_SHIFT 9 167 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_READ_CRED_MASK 0x3FE00 168 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_SHIFT 18 169 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_TOTAL_MASK 0x7FC0000 170 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_SHIFT 27 171 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_WRITE_MASK 0x8000000 172 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_SHIFT 28 173 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_READ_MASK 0x10000000 174 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_SHIFT 29 175 #define DCORE0_HMMU0_MMU_CORE_SEP_SLICE_CRDT_FORCE_FULL_TOTAL_MASK 0x20000000 176 177 /* DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT */ 178 #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_SHIFT 18 179 #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_TOTAL_MASK 0x7FC0000 180 #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_SHIFT 29 181 #define DCORE0_HMMU0_MMU_TOTAL_SLICE_CREDIT_FORCE_FULL_TOTAL_MASK 0x20000000 182 183 /* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB */ 184 #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_SHIFT 0 185 #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_LSB_PAGE_FAULT_ID_31_0_MASK 0xFFFFFFFF 186 187 /* DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB */ 188 #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_SHIFT 0 189 #define DCORE0_HMMU0_MMU_PAGE_FAULT_ID_MSB_PAGE_FAULT_ID_42_32_MASK 0x7FF 190 191 /* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB */ 192 #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_SHIFT 0 193 #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_LSB_PAGE_ACCESS_ID_31_0_MASK 0xFFFFFFFF 194 195 /* DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB */ 196 #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_SHIFT 0 197 #define DCORE0_HMMU0_MMU_PAGE_ACCESS_ID_MSB_PAGE_ACCESS_ID_42_32_MASK 0x7FF 198 199 /* DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE */ 200 #define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_SHIFT 0 201 #define DCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE_ENABLE_MASK 0x1 202 203 /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32 */ 204 #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_SHIFT 0 205 #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_SEC_MIN_63_32_MASK 0xFFFFFFFF 206 207 /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0 */ 208 #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_SHIFT 0 209 #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_SEC_MIN_31_0_MASK 0xFFFFFFFF 210 211 /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32 */ 212 #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_SHIFT 0 213 #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_SEC_MAX_63_32_MASK 0xFFFFFFFF 214 215 /* DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0 */ 216 #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_SHIFT 0 217 #define DCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_SEC_MAX_31_0_MASK 0xFFFFFFFF 218 219 /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32 */ 220 #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_SHIFT 0 221 #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_PRIV_MIN_63_32_MASK 0xFFFFFFFF 222 223 /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0 */ 224 #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_SHIFT 0 225 #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_PRIV_MIN_31_0_MASK 0xFFFFFFFF 226 227 /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32 */ 228 #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_SHIFT 0 229 #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_PRIV_MAX_63_32_MASK 0xFFFFFFFF 230 231 /* DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0 */ 232 #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_SHIFT 0 233 #define DCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_PRIV_MAX_31_0_MASK 0xFFFFFFFF 234 235 /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 */ 236 #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_SHIFT 0 237 #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_MASK 0xFFFFFFFF 238 239 /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 */ 240 #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_SHIFT 0 241 #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_MASK 0xFFFFFFFF 242 243 /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 */ 244 #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_SHIFT 0 245 #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_MASK 0xFFFFFFFF 246 247 /* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 */ 248 #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_SHIFT 0 249 #define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_MASK 0xFFFFFFFF 250 251 /* DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD */ 252 #define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_SHIFT 0 253 #define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_MASK 0x1 254 255 /* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0 */ 256 #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_SHIFT 0 257 #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_31_0_R_MASK 0xFFFFFFFF 258 259 /* DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32 */ 260 #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_SHIFT 0 261 #define DCORE0_HMMU0_MMU_RAZWI_WRITE_ID_42_32_R_MASK 0x7FF 262 263 /* DCORE0_HMMU0_MMU_RAZWI_READ_VLD */ 264 #define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_SHIFT 0 265 #define DCORE0_HMMU0_MMU_RAZWI_READ_VLD_R_MASK 0x1 266 267 /* DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0 */ 268 #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_SHIFT 0 269 #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_31_0_R_MASK 0xFFFFFFFF 270 271 /* DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32 */ 272 #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_SHIFT 0 273 #define DCORE0_HMMU0_MMU_RAZWI_READ_ID_42_32_R_MASK 0x7FF 274 275 /* DCORE0_HMMU0_MMU_MMU_SRC_NUM */ 276 #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_SHIFT 0 277 #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_OVERRIDE_SRC_NUM_EN_MASK 0x1 278 #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_SHIFT 1 279 #define DCORE0_HMMU0_MMU_MMU_SRC_NUM_SRC_NUM_MASK 0x1E 280 281 /* DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB */ 282 #define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_SHIFT 0 283 #define DCORE0_HMMU0_MMU_RAZWI_ADDR_LSB_ADDR_MASK 0xFFFFFFFF 284 285 /* DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB */ 286 #define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_SHIFT 0 287 #define DCORE0_HMMU0_MMU_RAZWI_ADDR_MSB_ADDR_MASK 0xFFFFFFFF 288 289 #endif /* ASIC_REG_DCORE0_HMMU0_MMU_MASKS_H_ */ 290