1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ 14 #define ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_EDMA0_CORE 19 * (Prototype: DMA_CORE) 20 ***************************************** 21 */ 22 23 /* DCORE0_EDMA0_CORE_CFG_0 */ 24 #define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT 0 25 #define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x1 26 27 /* DCORE0_EDMA0_CORE_CFG_1 */ 28 #define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT 0 29 #define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x1 30 #define DCORE0_EDMA0_CORE_CFG_1_FLUSH_SHIFT 1 31 #define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK 0x2 32 33 /* DCORE0_EDMA0_CORE_PROT */ 34 #define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT 0 35 #define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x1 36 #define DCORE0_EDMA0_CORE_PROT_ERR_VAL_SHIFT 1 37 #define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK 0x2 38 39 /* DCORE0_EDMA0_CORE_CKG */ 40 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT 0 41 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1 42 #define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_SHIFT 1 43 #define DCORE0_EDMA0_CORE_CKG_LBW_RBUF_KDMA_MASK 0x2 44 #define DCORE0_EDMA0_CORE_CKG_TE_SHIFT 2 45 #define DCORE0_EDMA0_CORE_CKG_TE_MASK 0x4 46 47 /* DCORE0_EDMA0_CORE_RD_GLBL */ 48 #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_SHIFT 0 49 #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1 50 #define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_SHIFT 4 51 #define DCORE0_EDMA0_CORE_RD_GLBL_HBW_FORCE_MISS_MASK 0x10 52 #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_SHIFT 5 53 #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_FORCE_MISS_MASK 0x20 54 55 /* DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND */ 56 #define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_SHIFT 0 57 #define DCORE0_EDMA0_CORE_RD_HBW_MAX_OUTSTAND_VAL_MASK 0xFFF 58 59 /* DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE */ 60 #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_SHIFT 0 61 #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_DATA_MASK 0xFFF 62 #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_SHIFT 16 63 #define DCORE0_EDMA0_CORE_RD_HBW_MAX_SIZE_MD_MASK 0xFFF0000 64 65 /* DCORE0_EDMA0_CORE_RD_HBW_ARCACHE */ 66 #define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_SHIFT 0 67 #define DCORE0_EDMA0_CORE_RD_HBW_ARCACHE_VAL_MASK 0xF 68 69 /* DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS */ 70 #define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_SHIFT 0 71 #define DCORE0_EDMA0_CORE_RD_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF 72 73 /* DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG */ 74 #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 75 #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF 76 #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_SHIFT 16 77 #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 78 #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_SHIFT 31 79 #define DCORE0_EDMA0_CORE_RD_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 80 81 /* DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND */ 82 #define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_SHIFT 0 83 #define DCORE0_EDMA0_CORE_RD_LBW_MAX_OUTSTAND_VAL_MASK 0xFFF 84 85 /* DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE */ 86 #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_SHIFT 0 87 #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_DATA_MASK 0xFFF 88 #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_SHIFT 16 89 #define DCORE0_EDMA0_CORE_RD_LBW_MAX_SIZE_MD_MASK 0xFFF0000 90 91 /* DCORE0_EDMA0_CORE_RD_LBW_ARCACHE */ 92 #define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_SHIFT 0 93 #define DCORE0_EDMA0_CORE_RD_LBW_ARCACHE_VAL_MASK 0xF 94 95 /* DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS */ 96 #define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_SHIFT 0 97 #define DCORE0_EDMA0_CORE_RD_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF 98 99 /* DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG */ 100 #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 101 #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF 102 #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_SHIFT 16 103 #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 104 #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_SHIFT 31 105 #define DCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 106 107 /* DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND */ 108 #define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_SHIFT 0 109 #define DCORE0_EDMA0_CORE_WR_HBW_MAX_OUTSTAND_VAL_MASK 0xFFFF 110 111 /* DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID */ 112 #define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_SHIFT 0 113 #define DCORE0_EDMA0_CORE_WR_HBW_MAX_AWID_VAL_MASK 0x3FFF 114 115 /* DCORE0_EDMA0_CORE_WR_HBW_AWCACHE */ 116 #define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_SHIFT 0 117 #define DCORE0_EDMA0_CORE_WR_HBW_AWCACHE_VAL_MASK 0xF 118 119 /* DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS */ 120 #define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_SHIFT 0 121 #define DCORE0_EDMA0_CORE_WR_HBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF 122 123 /* DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG */ 124 #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_SHIFT 0 125 #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_TOUT_MASK 0xFF 126 #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_SHIFT 16 127 #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 128 #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_SHIFT 31 129 #define DCORE0_EDMA0_CORE_WR_HBW_RATE_LIM_CFG_EN_MASK 0x80000000 130 131 /* DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND */ 132 #define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_SHIFT 0 133 #define DCORE0_EDMA0_CORE_WR_LBW_MAX_OUTSTAND_VAL_MASK 0xFFFF 134 135 /* DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID */ 136 #define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_SHIFT 0 137 #define DCORE0_EDMA0_CORE_WR_LBW_MAX_AWID_VAL_MASK 0x7F 138 139 /* DCORE0_EDMA0_CORE_WR_LBW_AWCACHE */ 140 #define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_SHIFT 0 141 #define DCORE0_EDMA0_CORE_WR_LBW_AWCACHE_VAL_MASK 0xF 142 143 /* DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS */ 144 #define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_SHIFT 0 145 #define DCORE0_EDMA0_CORE_WR_LBW_INFLIGHTS_VAL_MASK 0xFFFFFFFF 146 147 /* DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG */ 148 #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_SHIFT 0 149 #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_TOUT_MASK 0xFF 150 #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_SHIFT 16 151 #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_SAT_MASK 0xFF0000 152 #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_SHIFT 31 153 #define DCORE0_EDMA0_CORE_WR_LBW_RATE_LIM_CFG_EN_MASK 0x80000000 154 155 /* DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND */ 156 #define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_SHIFT 0 157 #define DCORE0_EDMA0_CORE_WR_COMP_MAX_OUTSTAND_VAL_MASK 0x1F 158 159 /* DCORE0_EDMA0_CORE_WR_COMP_AWUSER */ 160 #define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_SHIFT 0 161 #define DCORE0_EDMA0_CORE_WR_COMP_AWUSER_VAL_MASK 0xFFFFFFFF 162 163 /* DCORE0_EDMA0_CORE_ERR_CFG */ 164 #define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_SHIFT 0 165 #define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1 166 #define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_SHIFT 1 167 #define DCORE0_EDMA0_CORE_ERR_CFG_STOP_ON_ERR_MASK 0x2 168 169 /* DCORE0_EDMA0_CORE_ERR_CAUSE */ 170 #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_SHIFT 0 171 #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1 172 #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_SHIFT 1 173 #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_WR_ERR_MASK 0x2 174 #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_SHIFT 2 175 #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_MSG_WR_ERR_MASK 0x4 176 #define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_SHIFT 3 177 #define DCORE0_EDMA0_CORE_ERR_CAUSE_DESC_OVF_MASK 0x8 178 #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_SHIFT 4 179 #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_RD_ERR_MASK 0x10 180 #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_SHIFT 5 181 #define DCORE0_EDMA0_CORE_ERR_CAUSE_LBW_WR_ERR_MASK 0x20 182 #define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_SHIFT 6 183 #define DCORE0_EDMA0_CORE_ERR_CAUSE_TE_DESC_FIFO_OVFL_MASK 0x40 184 #define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_SHIFT 7 185 #define DCORE0_EDMA0_CORE_ERR_CAUSE_LIN_DMA_COMMIT_CFG_ERR_MASK 0x80 186 187 /* DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO */ 188 #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_SHIFT 0 189 #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_LO_VAL_MASK 0xFFFFFFFF 190 191 /* DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI */ 192 #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_SHIFT 0 193 #define DCORE0_EDMA0_CORE_ERRMSG_ADDR_HI_VAL_MASK 0xFFFFFFFF 194 195 /* DCORE0_EDMA0_CORE_ERRMSG_WDATA */ 196 #define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_SHIFT 0 197 #define DCORE0_EDMA0_CORE_ERRMSG_WDATA_VAL_MASK 0xFFFFFFFF 198 199 /* DCORE0_EDMA0_CORE_STS0 */ 200 #define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_SHIFT 0 201 #define DCORE0_EDMA0_CORE_STS0_RD_REQ_CNT_MASK 0x7FFF 202 #define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_SHIFT 16 203 #define DCORE0_EDMA0_CORE_STS0_WR_REQ_CNT_MASK 0x7FFF0000 204 #define DCORE0_EDMA0_CORE_STS0_BUSY_SHIFT 31 205 #define DCORE0_EDMA0_CORE_STS0_BUSY_MASK 0x80000000 206 207 /* DCORE0_EDMA0_CORE_STS1 */ 208 #define DCORE0_EDMA0_CORE_STS1_IS_HALT_SHIFT 0 209 #define DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK 0x1 210 211 /* DCORE0_EDMA0_CORE_STS_RD_CTX_SEL */ 212 #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_SHIFT 0 213 #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_VAL_MASK 0x7 214 #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_SHIFT 8 215 #define DCORE0_EDMA0_CORE_STS_RD_CTX_SEL_STRIDE_MASK 0x100 216 217 /* DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE */ 218 #define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_SHIFT 0 219 #define DCORE0_EDMA0_CORE_STS_RD_CTX_SIZE_VAL_MASK 0xFFFFFFFF 220 221 /* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO */ 222 #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_SHIFT 0 223 #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF 224 225 /* DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI */ 226 #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_SHIFT 0 227 #define DCORE0_EDMA0_CORE_STS_RD_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF 228 229 /* DCORE0_EDMA0_CORE_STS_RD_CTX_ID */ 230 #define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_SHIFT 0 231 #define DCORE0_EDMA0_CORE_STS_RD_CTX_ID_VAL_MASK 0xFFFF 232 233 /* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO */ 234 #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_SHIFT 0 235 #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_LO_VAL_MASK 0xFFFFFFFF 236 237 /* DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI */ 238 #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_SHIFT 0 239 #define DCORE0_EDMA0_CORE_STS_RD_HB_AXI_ADDR_HI_VAL_MASK 0xFFFFFFFF 240 241 /* DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR */ 242 #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_SHIFT 0 243 #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF 244 #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_SHIFT 30 245 #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_RDY_MASK 0x40000000 246 #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_SHIFT 31 247 #define DCORE0_EDMA0_CORE_STS_RD_LB_AXI_ADDR_VLD_MASK 0x80000000 248 249 /* DCORE0_EDMA0_CORE_STS_WR_CTX_SEL */ 250 #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_SHIFT 0 251 #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_VAL_MASK 0x7 252 #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_SHIFT 8 253 #define DCORE0_EDMA0_CORE_STS_WR_CTX_SEL_STRIDE_MASK 0x100 254 255 /* DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE */ 256 #define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_SHIFT 0 257 #define DCORE0_EDMA0_CORE_STS_WR_CTX_SIZE_VAL_MASK 0xFFFFFFFF 258 259 /* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO */ 260 #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_SHIFT 0 261 #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_LO_VAL_MASK 0xFFFFFFFF 262 263 /* DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI */ 264 #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_SHIFT 0 265 #define DCORE0_EDMA0_CORE_STS_WR_CTX_BASE_HI_VAL_MASK 0xFFFFFFFF 266 267 /* DCORE0_EDMA0_CORE_STS_WR_CTX_ID */ 268 #define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_SHIFT 0 269 #define DCORE0_EDMA0_CORE_STS_WR_CTX_ID_VAL_MASK 0xFFFFFFFF 270 271 /* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO */ 272 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_SHIFT 0 273 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VAL_MASK 0x3FFFF 274 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_SHIFT 30 275 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_RDY_MASK 0x40000000 276 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_SHIFT 31 277 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_LO_VLD_MASK 0x80000000 278 279 /* DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI */ 280 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_SHIFT 0 281 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VAL_MASK 0x3FFFF 282 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_SHIFT 30 283 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_RDY_MASK 0x40000000 284 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_SHIFT 31 285 #define DCORE0_EDMA0_CORE_STS_WR_HB_AXI_ADDR_HI_VLD_MASK 0x80000000 286 287 /* DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR */ 288 #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_SHIFT 0 289 #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VAL_MASK 0x3FFFFFF 290 #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_SHIFT 30 291 #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_RDY_MASK 0x40000000 292 #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_SHIFT 31 293 #define DCORE0_EDMA0_CORE_STS_WR_LB_AXI_ADDR_VLD_MASK 0x80000000 294 295 /* DCORE0_EDMA0_CORE_PWRLP_CFG */ 296 #define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_SHIFT 0 297 #define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1 298 #define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_SHIFT 4 299 #define DCORE0_EDMA0_CORE_PWRLP_CFG_CLR_MASK 0x10 300 301 /* DCORE0_EDMA0_CORE_PWRLP_STS */ 302 #define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_SHIFT 0 303 #define DCORE0_EDMA0_CORE_PWRLP_STS_RLVL_MASK 0x7F 304 #define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_SHIFT 8 305 #define DCORE0_EDMA0_CORE_PWRLP_STS_WLVL_MASK 0x7F00 306 #define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_SHIFT 16 307 #define DCORE0_EDMA0_CORE_PWRLP_STS_RCNT_MASK 0x7F0000 308 #define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_SHIFT 23 309 #define DCORE0_EDMA0_CORE_PWRLP_STS_WCNT_MASK 0x3F800000 310 #define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_SHIFT 30 311 #define DCORE0_EDMA0_CORE_PWRLP_STS_RFULL_MASK 0x40000000 312 #define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_SHIFT 31 313 #define DCORE0_EDMA0_CORE_PWRLP_STS_WFULL_MASK 0x80000000 314 315 /* DCORE0_EDMA0_CORE_DBG_DESC_CNT */ 316 #define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_SHIFT 0 317 #define DCORE0_EDMA0_CORE_DBG_DESC_CNT_VAL_MASK 0xFFFFFFFF 318 319 /* DCORE0_EDMA0_CORE_DBG_STS */ 320 #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_SHIFT 0 321 #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1 322 #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_SHIFT 1 323 #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_FULL_MASK 0x2 324 #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_SHIFT 2 325 #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_FULL_MASK 0x4 326 #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_SHIFT 3 327 #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_EMPTY_MASK 0x8 328 #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_SHIFT 4 329 #define DCORE0_EDMA0_CORE_DBG_STS_WR_CTX_EMPTY_MASK 0x10 330 #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_SHIFT 5 331 #define DCORE0_EDMA0_CORE_DBG_STS_WR_COMP_EMPTY_MASK 0x20 332 #define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_SHIFT 6 333 #define DCORE0_EDMA0_CORE_DBG_STS_TE_EMPTY_MASK 0x40 334 #define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_SHIFT 7 335 #define DCORE0_EDMA0_CORE_DBG_STS_TE_BUSY_MASK 0x80 336 #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_SHIFT 8 337 #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_EMPTY_MASK 0x100 338 #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_SHIFT 9 339 #define DCORE0_EDMA0_CORE_DBG_STS_GSKT_FULL_MASK 0x200 340 #define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_SHIFT 10 341 #define DCORE0_EDMA0_CORE_DBG_STS_RD_AGU_CS_MASK 0x400 342 #define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_SHIFT 11 343 #define DCORE0_EDMA0_CORE_DBG_STS_WR_AGU_CS_MASK 0x800 344 345 /* DCORE0_EDMA0_CORE_DBG_BUF_STS */ 346 #define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_SHIFT 0 347 #define DCORE0_EDMA0_CORE_DBG_BUF_STS_HBW_FULLNESS_MASK 0xFFF 348 #define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_SHIFT 16 349 #define DCORE0_EDMA0_CORE_DBG_BUF_STS_LBW_FULLNESS_MASK 0xFFF0000 350 351 /* DCORE0_EDMA0_CORE_DBG_RD_DESC_ID */ 352 #define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_SHIFT 0 353 #define DCORE0_EDMA0_CORE_DBG_RD_DESC_ID_VAL_MASK 0xFFFF 354 355 /* DCORE0_EDMA0_CORE_DBG_WR_DESC_ID */ 356 #define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_SHIFT 0 357 #define DCORE0_EDMA0_CORE_DBG_WR_DESC_ID_VAL_MASK 0xFFFF 358 359 /* DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE */ 360 #define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_SHIFT 0 361 #define DCORE0_EDMA0_CORE_APB_DMA_LBW_BASE_VAL_MASK 0xFFFF 362 363 /* DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE */ 364 #define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_SHIFT 0 365 #define DCORE0_EDMA0_CORE_APB_MSTR_IF_LBW_BASE_VAL_MASK 0xFFFF 366 367 /* DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG */ 368 #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_SHIFT 0 369 #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_Y_X_FORCE_MASK 0x1FF 370 #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_SHIFT 9 371 #define DCORE0_EDMA0_CORE_E2E_CRED_ASYNC_CFG_FORCE_EN_MASK 0x200 372 373 /* DCORE0_EDMA0_CORE_DBG_APB_ENABLER */ 374 #define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_SHIFT 0 375 #define DCORE0_EDMA0_CORE_DBG_APB_ENABLER_DIS_MASK 0x1 376 377 /* DCORE0_EDMA0_CORE_L2H_CMPR_LO */ 378 #define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_SHIFT 20 379 #define DCORE0_EDMA0_CORE_L2H_CMPR_LO_VAL_MASK 0xFFF00000 380 381 /* DCORE0_EDMA0_CORE_L2H_CMPR_HI */ 382 #define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_SHIFT 0 383 #define DCORE0_EDMA0_CORE_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF 384 385 /* DCORE0_EDMA0_CORE_L2H_MASK_LO */ 386 #define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_SHIFT 20 387 #define DCORE0_EDMA0_CORE_L2H_MASK_LO_VAL_MASK 0xFFF00000 388 389 /* DCORE0_EDMA0_CORE_L2H_MASK_HI */ 390 #define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_SHIFT 0 391 #define DCORE0_EDMA0_CORE_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF 392 393 /* DCORE0_EDMA0_CORE_IDLE_IND_MASK */ 394 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_SHIFT 0 395 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_MASK 0x1 396 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_SHIFT 1 397 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_MASK 0x2 398 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_SHIFT 2 399 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_MASK 0x4 400 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_SHIFT 3 401 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_MASK 0x8 402 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_SHIFT 8 403 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_DESC_CNT_STS_MASK 0x1F00 404 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_SHIFT 16 405 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_COMP_CNT_STS_MASK 0x1F0000 406 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_SHIFT 24 407 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_INSTAGE_EMPTY_MASK 0x1000000 408 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_SHIFT 25 409 #define DCORE0_EDMA0_CORE_IDLE_IND_MASK_CORE_IDLE_STS_MASK 0x2000000 410 411 /* DCORE0_EDMA0_CORE_APB_ENABLER */ 412 #define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_SHIFT 0 413 #define DCORE0_EDMA0_CORE_APB_ENABLER_DIS_MASK 0x1 414 415 #endif /* ASIC_REG_DCORE0_EDMA0_CORE_MASKS_H_ */ 416