1 /*
2 * Cobalt Qube/Raq PCI support
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
10 */
11
12 #include <linux/config.h>
13 #include <linux/types.h>
14 #include <linux/pci.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17
18 #include <asm/pci.h>
19 #include <asm/io.h>
20 #include <asm/gt64120/gt64120.h>
21 #include <asm/cobalt/cobalt.h>
22
23 #ifdef CONFIG_PCI
24
25 int cobalt_board_id;
26
qube_expansion_slot_bist(struct pci_dev * dev)27 static void qube_expansion_slot_bist(struct pci_dev *dev)
28 {
29 unsigned char ctrl;
30 int timeout = 100000;
31
32 pci_read_config_byte(dev, PCI_BIST, &ctrl);
33 if(!(ctrl & PCI_BIST_CAPABLE))
34 return;
35
36 pci_write_config_byte(dev, PCI_BIST, ctrl|PCI_BIST_START);
37 do {
38 pci_read_config_byte(dev, PCI_BIST, &ctrl);
39 if(!(ctrl & PCI_BIST_START))
40 break;
41 } while(--timeout > 0);
42 if((timeout <= 0) || (ctrl & PCI_BIST_CODE_MASK))
43 printk("PCI: Expansion slot card failed BIST with code %x\n",
44 (ctrl & PCI_BIST_CODE_MASK));
45 }
46
qube_expansion_slot_fixup(struct pci_dev * dev)47 static void qube_expansion_slot_fixup(struct pci_dev *dev)
48 {
49 unsigned short pci_cmd;
50 unsigned long ioaddr_base = 0x10108000; /* It's magic, ask Doug. */
51 unsigned long memaddr_base = 0x12001000;
52 int i;
53
54 /* Enable bits in COMMAND so driver can talk to it. */
55 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
56 pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
57 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
58
59 /* Give it a working IRQ. */
60 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_QUBE_SLOT_IRQ);
61 dev->irq = COBALT_QUBE_SLOT_IRQ;
62
63 ioaddr_base += 0x2000 * PCI_FUNC(dev->devfn);
64 memaddr_base += 0x2000 * PCI_FUNC(dev->devfn);
65
66 /* Fixup base addresses, we only support I/O at the moment. */
67 for(i = 0; i <= 5; i++) {
68 unsigned int regaddr = (PCI_BASE_ADDRESS_0 + (i * 4));
69 unsigned int rval, mask, size, alignme, aspace;
70 unsigned long *basep = &ioaddr_base;
71
72 /* Check type first, punt if non-IO. */
73 pci_read_config_dword(dev, regaddr, &rval);
74 aspace = (rval & PCI_BASE_ADDRESS_SPACE);
75 if(aspace != PCI_BASE_ADDRESS_SPACE_IO)
76 basep = &memaddr_base;
77
78 /* Figure out how much it wants, if anything. */
79 pci_write_config_dword(dev, regaddr, 0xffffffff);
80 pci_read_config_dword(dev, regaddr, &rval);
81
82 /* Unused? */
83 if(rval == 0)
84 continue;
85
86 rval &= PCI_BASE_ADDRESS_IO_MASK;
87 mask = (~rval << 1) | 0x1;
88 size = (mask & rval) & 0xffffffff;
89 alignme = size;
90 if(alignme < 0x400)
91 alignme = 0x400;
92 rval = ((*basep + (alignme - 1)) & ~(alignme - 1));
93 *basep = (rval + size);
94 pci_write_config_dword(dev, regaddr, rval | aspace);
95 dev->resource[i].start = rval;
96 dev->resource[i].end = *basep - 1;
97 if(aspace == PCI_BASE_ADDRESS_SPACE_IO) {
98 dev->resource[i].start -= 0x10000000;
99 dev->resource[i].end -= 0x10000000;
100 }
101 }
102 qube_expansion_slot_bist(dev);
103 }
104
qube_raq_via_bmIDE_fixup(struct pci_dev * dev)105 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
106 {
107 unsigned short cfgword;
108 unsigned char lt;
109
110 /* Enable Bus Mastering and fast back to back. */
111 pci_read_config_word(dev, PCI_COMMAND, &cfgword);
112 cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
113 pci_write_config_word(dev, PCI_COMMAND, cfgword);
114
115 /* Enable both ide interfaces. ROM only enables primary one. */
116 pci_write_config_byte(dev, 0x40, 0xb);
117
118 /* Set latency timer to reasonable value. */
119 pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
120 if(lt < 64)
121 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
122 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
123 }
124
qube_raq_tulip_fixup(struct pci_dev * dev)125 static void qube_raq_tulip_fixup(struct pci_dev *dev)
126 {
127 unsigned short pci_cmd;
128
129 /* Fixup the first tulip located at device PCICONF_ETH0 */
130 if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH0) {
131 /* Setup the first Tulip */
132 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
133 COBALT_ETH0_IRQ);
134 dev->irq = COBALT_ETH0_IRQ;
135
136 dev->resource[0].start = 0x100000;
137 dev->resource[0].end = 0x10007f;
138
139 dev->resource[1].start = 0x12000000;
140 dev->resource[1].end = dev->resource[1].start + 0x3ff;
141 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, dev->resource[1].start);
142
143 /* Fixup the second tulip located at device PCICONF_ETH1 */
144 } else if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH1) {
145
146 /* Enable the second Tulip device. */
147 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
148 pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER);
149 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
150
151 /* Give it it's IRQ. */
152 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
153 COBALT_ETH1_IRQ);
154 dev->irq = COBALT_ETH1_IRQ;
155
156 /* And finally, a usable I/O space allocation, right after what
157 * the first Tulip uses.
158 */
159 dev->resource[0].start = 0x101000;
160 dev->resource[0].end = 0x10107f;
161
162 dev->resource[1].start = 0x12000400;
163 dev->resource[1].end = dev->resource[1].start + 0x3ff;
164 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, dev->resource[1].start);
165 }
166 }
167
qube_raq_scsi_fixup(struct pci_dev * dev)168 static void qube_raq_scsi_fixup(struct pci_dev *dev)
169 {
170 unsigned short pci_cmd;
171
172 /*
173 * Tell the SCSI device that we expect an interrupt at
174 * IRQ 7 and not the default 0.
175 */
176 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_SCSI_IRQ);
177 dev->irq = COBALT_SCSI_IRQ;
178
179 if (cobalt_board_id == COBALT_BRD_ID_RAQ2) {
180
181 /* Enable the device. */
182 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
183
184 pci_cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
185 | PCI_COMMAND_INVALIDATE);
186 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
187
188 /* Give it it's RAQ IRQ. */
189 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_RAQ_SCSI_IRQ);
190 dev->irq = COBALT_RAQ_SCSI_IRQ;
191
192 /* And finally, a usable I/O space allocation, right after what
193 * the second Tulip uses.
194 */
195 dev->resource[0].start = 0x102000;
196 dev->resource[0].end = dev->resource[0].start + 0xff;
197 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x10102000);
198
199 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x00002000);
200 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0x00100000);
201 }
202 }
203
qube_raq_galileo_fixup(struct pci_dev * dev)204 static void qube_raq_galileo_fixup(struct pci_dev *dev)
205 {
206 unsigned short galileo_id;
207
208 /* Fix PCI latency-timer and cache-line-size values in Galileo
209 * host bridge.
210 */
211 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
212 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
213
214 /* On all machines prior to Q2, we had the STOP line disconnected
215 * from Galileo to VIA on PCI. The new Galileo does not function
216 * correctly unless we have it connected.
217 *
218 * Therefore we must set the disconnect/retry cycle values to
219 * something sensible when using the new Galileo.
220 */
221 pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
222 galileo_id &= 0xff; /* mask off class info */
223 if (galileo_id >= 0x10) {
224 /* New Galileo, assumes PCI stop line to VIA is connected. */
225 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
226 } else if (galileo_id == 0x1 || galileo_id == 0x2) {
227 signed int timeo;
228 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
229 timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
230 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
231 GALILEO_OUTL(0xffff, GT_PCI0_TOR_OFS);
232 }
233 }
234
235 static void
qube_pcibios_fixup(struct pci_dev * dev)236 qube_pcibios_fixup(struct pci_dev *dev)
237 {
238 if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_PCISLOT) {
239 unsigned int tmp;
240
241 /* See if there is a device in the expansion slot, if so
242 * discover its resources and fixup whatever we need to
243 */
244 pci_read_config_dword(dev, PCI_VENDOR_ID, &tmp);
245 if(tmp != 0xffffffff && tmp != 0x00000000)
246 qube_expansion_slot_fixup(dev);
247 }
248 }
249
250 struct pci_fixup pcibios_fixups[] = {
251 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, qube_raq_via_bmIDE_fixup },
252 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, qube_raq_tulip_fixup },
253 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_GALILEO, PCI_ANY_ID, qube_raq_galileo_fixup },
254 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, qube_raq_scsi_fixup },
255 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, qube_pcibios_fixup }
256 };
257
258
pci_range_ck(struct pci_dev * dev)259 static __inline__ int pci_range_ck(struct pci_dev *dev)
260 {
261 if ((dev->bus->number == 0)
262 && ((PCI_SLOT (dev->devfn) == 0)
263 || ((PCI_SLOT (dev->devfn) > 6)
264 && (PCI_SLOT (dev->devfn) <= 12))))
265 return 0; /* OK device number */
266
267 return -1; /* NOT ok device number */
268 }
269
270 #define PCI_CFG_SET(dev,where) \
271 GALILEO_OUTL((0x80000000 | (((dev)->devfn) << 8) | \
272 (where)), GT_PCI0_CFGADDR_OFS)
273
qube_pci_read_config_dword(struct pci_dev * dev,int where,u32 * val)274 static int qube_pci_read_config_dword (struct pci_dev *dev,
275 int where,
276 u32 *val)
277 {
278 if (where & 0x3)
279 return PCIBIOS_BAD_REGISTER_NUMBER;
280 if (pci_range_ck (dev)) {
281 *val = 0xFFFFFFFF;
282 return PCIBIOS_DEVICE_NOT_FOUND;
283 }
284 PCI_CFG_SET(dev, where);
285 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
286 return PCIBIOS_SUCCESSFUL;
287 }
288
qube_pci_read_config_word(struct pci_dev * dev,int where,u16 * val)289 static int qube_pci_read_config_word (struct pci_dev *dev,
290 int where,
291 u16 *val)
292 {
293 if (where & 0x1)
294 return PCIBIOS_BAD_REGISTER_NUMBER;
295 if (pci_range_ck (dev)) {
296 *val = 0xffff;
297 return PCIBIOS_DEVICE_NOT_FOUND;
298 }
299 PCI_CFG_SET(dev, (where & ~0x3));
300 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) >> ((where & 3) * 8);
301 return PCIBIOS_SUCCESSFUL;
302 }
303
qube_pci_read_config_byte(struct pci_dev * dev,int where,u8 * val)304 static int qube_pci_read_config_byte (struct pci_dev *dev,
305 int where,
306 u8 *val)
307 {
308 if (pci_range_ck (dev)) {
309 *val = 0xff;
310 return PCIBIOS_DEVICE_NOT_FOUND;
311 }
312 PCI_CFG_SET(dev, (where & ~0x3));
313 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) >> ((where & 3) * 8);
314 return PCIBIOS_SUCCESSFUL;
315 }
316
qube_pci_write_config_dword(struct pci_dev * dev,int where,u32 val)317 static int qube_pci_write_config_dword (struct pci_dev *dev,
318 int where,
319 u32 val)
320 {
321 if(where & 0x3)
322 return PCIBIOS_BAD_REGISTER_NUMBER;
323 if (pci_range_ck (dev))
324 return PCIBIOS_DEVICE_NOT_FOUND;
325 PCI_CFG_SET(dev, where);
326 GALILEO_OUTL(val, GT_PCI0_CFGDATA_OFS);
327 return PCIBIOS_SUCCESSFUL;
328 }
329
330 static int
qube_pci_write_config_word(struct pci_dev * dev,int where,u16 val)331 qube_pci_write_config_word (struct pci_dev *dev,
332 int where,
333 u16 val)
334 {
335 unsigned long tmp;
336
337 if (where & 0x1)
338 return PCIBIOS_BAD_REGISTER_NUMBER;
339 if (pci_range_ck (dev))
340 return PCIBIOS_DEVICE_NOT_FOUND;
341 PCI_CFG_SET(dev, (where & ~0x3));
342 tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
343 tmp &= ~(0xffff << ((where & 0x3) * 8));
344 tmp |= (val << ((where & 0x3) * 8));
345 GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS);
346 return PCIBIOS_SUCCESSFUL;
347 }
348
349 static int
qube_pci_write_config_byte(struct pci_dev * dev,int where,u8 val)350 qube_pci_write_config_byte (struct pci_dev *dev,
351 int where,
352 u8 val)
353 {
354 unsigned long tmp;
355
356 if (pci_range_ck (dev))
357 return PCIBIOS_DEVICE_NOT_FOUND;
358 PCI_CFG_SET(dev, (where & ~0x3));
359 tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
360 tmp &= ~(0xff << ((where & 0x3) * 8));
361 tmp |= (val << ((where & 0x3) * 8));
362 GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS);
363 return PCIBIOS_SUCCESSFUL;
364 }
365
366
367 struct pci_ops qube_pci_ops = {
368 qube_pci_read_config_byte,
369 qube_pci_read_config_word,
370 qube_pci_read_config_dword,
371 qube_pci_write_config_byte,
372 qube_pci_write_config_word,
373 qube_pci_write_config_dword
374 };
375
pcibios_init(void)376 void __init pcibios_init(void)
377 {
378 struct pci_dev dev;
379
380 printk("PCI: Probing PCI hardware\n");
381
382 /* Read the cobalt id register out of the PCI config space */
383 dev.devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
384 PCI_CFG_SET(&dev, (VIA_COBALT_BRD_ID_REG & ~0x3));
385 cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS) >> ((VIA_COBALT_BRD_ID_REG & 3) * 8);
386 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
387
388 printk("Cobalt Board ID: %d\n", cobalt_board_id);
389
390 ioport_resource.start = 0x00000000;
391 ioport_resource.end = 0x0fffffff;
392
393 iomem_resource.start = 0x01000000;
394 iomem_resource.end = 0xffffffff;
395
396 pci_scan_bus(0, &qube_pci_ops, NULL);
397 }
398
pcibios_fixup_bus(struct pci_bus * bus)399 void __init pcibios_fixup_bus(struct pci_bus *bus)
400 {
401 /* We don't have sub-busses to fixup here */
402 }
403
pcibios_assign_all_busses(void)404 unsigned int __init pcibios_assign_all_busses(void)
405 {
406 return 1;
407 }
408
409 #endif /* CONFIG_PCI */
410