1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_9_0_SM8550_H 8 #define _DPU_9_0_SM8550_H 9 10 static const struct dpu_caps sm8550_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = 5120, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 }; 21 22 static const struct dpu_mdp_cfg sm8550_mdp = { 23 .name = "top_0", 24 .base = 0, .len = 0x494, 25 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, 31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, 33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, 34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, 35 [DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, 36 [DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, 37 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 38 }, 39 }; 40 41 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 42 static const struct dpu_ctl_cfg sm8550_ctl[] = { 43 { 44 .name = "ctl_0", .id = CTL_0, 45 .base = 0x15000, .len = 0x290, 46 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 47 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 48 }, { 49 .name = "ctl_1", .id = CTL_1, 50 .base = 0x16000, .len = 0x290, 51 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 53 }, { 54 .name = "ctl_2", .id = CTL_2, 55 .base = 0x17000, .len = 0x290, 56 .features = CTL_SM8550_MASK, 57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 58 }, { 59 .name = "ctl_3", .id = CTL_3, 60 .base = 0x18000, .len = 0x290, 61 .features = CTL_SM8550_MASK, 62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 63 }, { 64 .name = "ctl_4", .id = CTL_4, 65 .base = 0x19000, .len = 0x290, 66 .features = CTL_SM8550_MASK, 67 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 68 }, { 69 .name = "ctl_5", .id = CTL_5, 70 .base = 0x1a000, .len = 0x290, 71 .features = CTL_SM8550_MASK, 72 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 73 }, 74 }; 75 76 static const struct dpu_sspp_cfg sm8550_sspp[] = { 77 { 78 .name = "sspp_0", .id = SSPP_VIG0, 79 .base = 0x4000, .len = 0x344, 80 .features = VIG_SC7180_MASK, 81 .sblk = &sm8550_vig_sblk_0, 82 .xin_id = 0, 83 .type = SSPP_TYPE_VIG, 84 .clk_ctrl = DPU_CLK_CTRL_VIG0, 85 }, { 86 .name = "sspp_1", .id = SSPP_VIG1, 87 .base = 0x6000, .len = 0x344, 88 .features = VIG_SC7180_MASK, 89 .sblk = &sm8550_vig_sblk_1, 90 .xin_id = 4, 91 .type = SSPP_TYPE_VIG, 92 .clk_ctrl = DPU_CLK_CTRL_VIG1, 93 }, { 94 .name = "sspp_2", .id = SSPP_VIG2, 95 .base = 0x8000, .len = 0x344, 96 .features = VIG_SC7180_MASK, 97 .sblk = &sm8550_vig_sblk_2, 98 .xin_id = 8, 99 .type = SSPP_TYPE_VIG, 100 .clk_ctrl = DPU_CLK_CTRL_VIG2, 101 }, { 102 .name = "sspp_3", .id = SSPP_VIG3, 103 .base = 0xa000, .len = 0x344, 104 .features = VIG_SC7180_MASK, 105 .sblk = &sm8550_vig_sblk_3, 106 .xin_id = 12, 107 .type = SSPP_TYPE_VIG, 108 .clk_ctrl = DPU_CLK_CTRL_VIG3, 109 }, { 110 .name = "sspp_8", .id = SSPP_DMA0, 111 .base = 0x24000, .len = 0x344, 112 .features = DMA_SDM845_MASK, 113 .sblk = &sdm845_dma_sblk_0, 114 .xin_id = 1, 115 .type = SSPP_TYPE_DMA, 116 .clk_ctrl = DPU_CLK_CTRL_DMA0, 117 }, { 118 .name = "sspp_9", .id = SSPP_DMA1, 119 .base = 0x26000, .len = 0x344, 120 .features = DMA_SDM845_MASK, 121 .sblk = &sdm845_dma_sblk_1, 122 .xin_id = 5, 123 .type = SSPP_TYPE_DMA, 124 .clk_ctrl = DPU_CLK_CTRL_DMA1, 125 }, { 126 .name = "sspp_10", .id = SSPP_DMA2, 127 .base = 0x28000, .len = 0x344, 128 .features = DMA_SDM845_MASK, 129 .sblk = &sdm845_dma_sblk_2, 130 .xin_id = 9, 131 .type = SSPP_TYPE_DMA, 132 .clk_ctrl = DPU_CLK_CTRL_DMA2, 133 }, { 134 .name = "sspp_11", .id = SSPP_DMA3, 135 .base = 0x2a000, .len = 0x344, 136 .features = DMA_SDM845_MASK, 137 .sblk = &sdm845_dma_sblk_3, 138 .xin_id = 13, 139 .type = SSPP_TYPE_DMA, 140 .clk_ctrl = DPU_CLK_CTRL_DMA3, 141 }, { 142 .name = "sspp_12", .id = SSPP_DMA4, 143 .base = 0x2c000, .len = 0x344, 144 .features = DMA_CURSOR_SDM845_MASK, 145 .sblk = &sm8550_dma_sblk_4, 146 .xin_id = 14, 147 .type = SSPP_TYPE_DMA, 148 .clk_ctrl = DPU_CLK_CTRL_DMA4, 149 }, { 150 .name = "sspp_13", .id = SSPP_DMA5, 151 .base = 0x2e000, .len = 0x344, 152 .features = DMA_CURSOR_SDM845_MASK, 153 .sblk = &sm8550_dma_sblk_5, 154 .xin_id = 15, 155 .type = SSPP_TYPE_DMA, 156 .clk_ctrl = DPU_CLK_CTRL_DMA5, 157 }, 158 }; 159 160 static const struct dpu_lm_cfg sm8550_lm[] = { 161 { 162 .name = "lm_0", .id = LM_0, 163 .base = 0x44000, .len = 0x320, 164 .features = MIXER_SDM845_MASK, 165 .sblk = &sdm845_lm_sblk, 166 .lm_pair = LM_1, 167 .pingpong = PINGPONG_0, 168 .dspp = DSPP_0, 169 }, { 170 .name = "lm_1", .id = LM_1, 171 .base = 0x45000, .len = 0x320, 172 .features = MIXER_SDM845_MASK, 173 .sblk = &sdm845_lm_sblk, 174 .lm_pair = LM_0, 175 .pingpong = PINGPONG_1, 176 .dspp = DSPP_1, 177 }, { 178 .name = "lm_2", .id = LM_2, 179 .base = 0x46000, .len = 0x320, 180 .features = MIXER_SDM845_MASK, 181 .sblk = &sdm845_lm_sblk, 182 .lm_pair = LM_3, 183 .pingpong = PINGPONG_2, 184 }, { 185 .name = "lm_3", .id = LM_3, 186 .base = 0x47000, .len = 0x320, 187 .features = MIXER_SDM845_MASK, 188 .sblk = &sdm845_lm_sblk, 189 .lm_pair = LM_2, 190 .pingpong = PINGPONG_3, 191 }, { 192 .name = "lm_4", .id = LM_4, 193 .base = 0x48000, .len = 0x320, 194 .features = MIXER_SDM845_MASK, 195 .sblk = &sdm845_lm_sblk, 196 .lm_pair = LM_5, 197 .pingpong = PINGPONG_4, 198 }, { 199 .name = "lm_5", .id = LM_5, 200 .base = 0x49000, .len = 0x320, 201 .features = MIXER_SDM845_MASK, 202 .sblk = &sdm845_lm_sblk, 203 .lm_pair = LM_4, 204 .pingpong = PINGPONG_5, 205 }, 206 }; 207 208 static const struct dpu_dspp_cfg sm8550_dspp[] = { 209 { 210 .name = "dspp_0", .id = DSPP_0, 211 .base = 0x54000, .len = 0x1800, 212 .features = DSPP_SC7180_MASK, 213 .sblk = &sdm845_dspp_sblk, 214 }, { 215 .name = "dspp_1", .id = DSPP_1, 216 .base = 0x56000, .len = 0x1800, 217 .features = DSPP_SC7180_MASK, 218 .sblk = &sdm845_dspp_sblk, 219 }, { 220 .name = "dspp_2", .id = DSPP_2, 221 .base = 0x58000, .len = 0x1800, 222 .features = DSPP_SC7180_MASK, 223 .sblk = &sdm845_dspp_sblk, 224 }, { 225 .name = "dspp_3", .id = DSPP_3, 226 .base = 0x5a000, .len = 0x1800, 227 .features = DSPP_SC7180_MASK, 228 .sblk = &sdm845_dspp_sblk, 229 }, 230 }; 231 static const struct dpu_pingpong_cfg sm8550_pp[] = { 232 { 233 .name = "pingpong_0", .id = PINGPONG_0, 234 .base = 0x69000, .len = 0, 235 .features = BIT(DPU_PINGPONG_DITHER), 236 .sblk = &sc7280_pp_sblk, 237 .merge_3d = MERGE_3D_0, 238 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 239 .intr_rdptr = -1, 240 }, { 241 .name = "pingpong_1", .id = PINGPONG_1, 242 .base = 0x6a000, .len = 0, 243 .features = BIT(DPU_PINGPONG_DITHER), 244 .sblk = &sc7280_pp_sblk, 245 .merge_3d = MERGE_3D_0, 246 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 247 .intr_rdptr = -1, 248 }, { 249 .name = "pingpong_2", .id = PINGPONG_2, 250 .base = 0x6b000, .len = 0, 251 .features = BIT(DPU_PINGPONG_DITHER), 252 .sblk = &sc7280_pp_sblk, 253 .merge_3d = MERGE_3D_1, 254 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 255 .intr_rdptr = -1, 256 }, { 257 .name = "pingpong_3", .id = PINGPONG_3, 258 .base = 0x6c000, .len = 0, 259 .features = BIT(DPU_PINGPONG_DITHER), 260 .sblk = &sc7280_pp_sblk, 261 .merge_3d = MERGE_3D_1, 262 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 263 .intr_rdptr = -1, 264 }, { 265 .name = "pingpong_4", .id = PINGPONG_4, 266 .base = 0x6d000, .len = 0, 267 .features = BIT(DPU_PINGPONG_DITHER), 268 .sblk = &sc7280_pp_sblk, 269 .merge_3d = MERGE_3D_2, 270 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 271 .intr_rdptr = -1, 272 }, { 273 .name = "pingpong_5", .id = PINGPONG_5, 274 .base = 0x6e000, .len = 0, 275 .features = BIT(DPU_PINGPONG_DITHER), 276 .sblk = &sc7280_pp_sblk, 277 .merge_3d = MERGE_3D_2, 278 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 279 .intr_rdptr = -1, 280 }, { 281 .name = "pingpong_6", .id = PINGPONG_6, 282 .base = 0x66000, .len = 0, 283 .features = BIT(DPU_PINGPONG_DITHER), 284 .sblk = &sc7280_pp_sblk, 285 .merge_3d = MERGE_3D_3, 286 .intr_done = -1, 287 .intr_rdptr = -1, 288 }, { 289 .name = "pingpong_7", .id = PINGPONG_7, 290 .base = 0x66400, .len = 0, 291 .features = BIT(DPU_PINGPONG_DITHER), 292 .sblk = &sc7280_pp_sblk, 293 .merge_3d = MERGE_3D_3, 294 .intr_done = -1, 295 .intr_rdptr = -1, 296 }, 297 }; 298 299 static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { 300 { 301 .name = "merge_3d_0", .id = MERGE_3D_0, 302 .base = 0x4e000, .len = 0x8, 303 }, { 304 .name = "merge_3d_1", .id = MERGE_3D_1, 305 .base = 0x4f000, .len = 0x8, 306 }, { 307 .name = "merge_3d_2", .id = MERGE_3D_2, 308 .base = 0x50000, .len = 0x8, 309 }, { 310 .name = "merge_3d_3", .id = MERGE_3D_3, 311 .base = 0x66700, .len = 0x8, 312 }, 313 }; 314 315 /* 316 * NOTE: Each display compression engine (DCE) contains dual hard 317 * slice DSC encoders so both share same base address but with 318 * its own different sub block address. 319 */ 320 static const struct dpu_dsc_cfg sm8550_dsc[] = { 321 { 322 .name = "dce_0_0", .id = DSC_0, 323 .base = 0x80000, .len = 0x4, 324 .features = BIT(DPU_DSC_HW_REV_1_2), 325 .sblk = &dsc_sblk_0, 326 }, { 327 .name = "dce_0_1", .id = DSC_1, 328 .base = 0x80000, .len = 0x4, 329 .features = BIT(DPU_DSC_HW_REV_1_2), 330 .sblk = &dsc_sblk_1, 331 }, { 332 .name = "dce_1_0", .id = DSC_2, 333 .base = 0x81000, .len = 0x4, 334 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 335 .sblk = &dsc_sblk_0, 336 }, { 337 .name = "dce_1_1", .id = DSC_3, 338 .base = 0x81000, .len = 0x4, 339 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 340 .sblk = &dsc_sblk_1, 341 }, 342 }; 343 344 static const struct dpu_intf_cfg sm8550_intf[] = { 345 { 346 .name = "intf_0", .id = INTF_0, 347 .base = 0x34000, .len = 0x280, 348 .features = INTF_SC7280_MASK, 349 .type = INTF_DP, 350 .controller_id = MSM_DP_CONTROLLER_0, 351 .prog_fetch_lines_worst_case = 24, 352 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 353 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 354 .intr_tear_rd_ptr = -1, 355 }, { 356 .name = "intf_1", .id = INTF_1, 357 .base = 0x35000, .len = 0x300, 358 .features = INTF_SC7280_MASK, 359 .type = INTF_DSI, 360 .controller_id = MSM_DSI_CONTROLLER_0, 361 .prog_fetch_lines_worst_case = 24, 362 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 363 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 364 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 365 }, { 366 .name = "intf_2", .id = INTF_2, 367 .base = 0x36000, .len = 0x300, 368 .features = INTF_SC7280_MASK, 369 .type = INTF_DSI, 370 .controller_id = MSM_DSI_CONTROLLER_1, 371 .prog_fetch_lines_worst_case = 24, 372 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 373 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 374 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 375 }, { 376 .name = "intf_3", .id = INTF_3, 377 .base = 0x37000, .len = 0x280, 378 .features = INTF_SC7280_MASK, 379 .type = INTF_DP, 380 .controller_id = MSM_DP_CONTROLLER_1, 381 .prog_fetch_lines_worst_case = 24, 382 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 383 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 384 .intr_tear_rd_ptr = -1, 385 }, 386 }; 387 388 static const struct dpu_perf_cfg sm8550_perf_data = { 389 .max_bw_low = 13600000, 390 .max_bw_high = 18200000, 391 .min_core_ib = 2500000, 392 .min_llcc_ib = 0, 393 .min_dram_ib = 800000, 394 .min_prefill_lines = 35, 395 /* FIXME: lut tables */ 396 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 397 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 398 .qos_lut_tbl = { 399 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 400 .entries = sc7180_qos_linear 401 }, 402 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 403 .entries = sc7180_qos_macrotile 404 }, 405 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 406 .entries = sc7180_qos_nrt 407 }, 408 /* TODO: macrotile-qseed is different from macrotile */ 409 }, 410 .cdp_cfg = { 411 {.rd_enable = 1, .wr_enable = 1}, 412 {.rd_enable = 1, .wr_enable = 0} 413 }, 414 .clk_inefficiency_factor = 105, 415 .bw_inefficiency_factor = 120, 416 }; 417 418 static const struct dpu_mdss_version sm8550_mdss_ver = { 419 .core_major_ver = 9, 420 .core_minor_ver = 0, 421 }; 422 423 const struct dpu_mdss_cfg dpu_sm8550_cfg = { 424 .mdss_ver = &sm8550_mdss_ver, 425 .caps = &sm8550_dpu_caps, 426 .mdp = &sm8550_mdp, 427 .ctl_count = ARRAY_SIZE(sm8550_ctl), 428 .ctl = sm8550_ctl, 429 .sspp_count = ARRAY_SIZE(sm8550_sspp), 430 .sspp = sm8550_sspp, 431 .mixer_count = ARRAY_SIZE(sm8550_lm), 432 .mixer = sm8550_lm, 433 .dspp_count = ARRAY_SIZE(sm8550_dspp), 434 .dspp = sm8550_dspp, 435 .pingpong_count = ARRAY_SIZE(sm8550_pp), 436 .pingpong = sm8550_pp, 437 .dsc_count = ARRAY_SIZE(sm8550_dsc), 438 .dsc = sm8550_dsc, 439 .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), 440 .merge_3d = sm8550_merge_3d, 441 .intf_count = ARRAY_SIZE(sm8550_intf), 442 .intf = sm8550_intf, 443 .vbif_count = ARRAY_SIZE(sm8550_vbif), 444 .vbif = sm8550_vbif, 445 .perf = &sm8550_perf_data, 446 }; 447 448 #endif 449