1 /* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _athub_1_0_SH_MASK_HEADER 22 #define _athub_1_0_SH_MASK_HEADER 23 24 25 // addressBlock: athub_atsdec 26 //ATC_ATS_CNTL 27 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0 28 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1 29 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2 30 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8 31 #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER__SHIFT 0x14 32 #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER__SHIFT 0x15 33 #define ATC_ATS_CNTL__TRANS_EXE_RETURN__SHIFT 0x16 34 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 35 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 36 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 37 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003F00L 38 #define ATC_ATS_CNTL__INVALIDATION_LOG_KEEP_ORDER_MASK 0x00100000L 39 #define ATC_ATS_CNTL__TRANS_LOG_KEEP_ORDER_MASK 0x00200000L 40 #define ATC_ATS_CNTL__TRANS_EXE_RETURN_MASK 0x00C00000L 41 //ATC_ATS_STATUS 42 #define ATC_ATS_STATUS__BUSY__SHIFT 0x0 43 #define ATC_ATS_STATUS__CRASHED__SHIFT 0x1 44 #define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2 45 #define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x3 46 #define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING__SHIFT 0x6 47 #define ATC_ATS_STATUS__BUSY_MASK 0x00000001L 48 #define ATC_ATS_STATUS__CRASHED_MASK 0x00000002L 49 #define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x00000004L 50 #define ATC_ATS_STATUS__FLUSH_INVALIDATION_OUTSTANDING_MASK 0x00000038L 51 #define ATC_ATS_STATUS__NONFLUSH_INVALIDATION_OUTSTANDING_MASK 0x000001C0L 52 //ATC_ATS_FAULT_CNTL 53 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0 54 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa 55 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14 56 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x000001FFL 57 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x0007FC00L 58 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1FF00000L 59 //ATC_ATS_FAULT_STATUS_INFO 60 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0 61 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa 62 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf 63 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10 64 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11 65 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12 66 #define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13 67 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18 68 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x000001FFL 69 #define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x00007C00L 70 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x00008000L 71 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x00010000L 72 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x00020000L 73 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x00040000L 74 #define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0x00F80000L 75 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0x0F000000L 76 //ATC_ATS_FAULT_STATUS_ADDR 77 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0 78 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xFFFFFFFFL 79 //ATC_ATS_DEFAULT_PAGE_LOW 80 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0 81 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xFFFFFFFFL 82 //ATC_TRANS_FAULT_RSPCNTRL 83 #define ATC_TRANS_FAULT_RSPCNTRL__VMID0__SHIFT 0x0 84 #define ATC_TRANS_FAULT_RSPCNTRL__VMID1__SHIFT 0x1 85 #define ATC_TRANS_FAULT_RSPCNTRL__VMID2__SHIFT 0x2 86 #define ATC_TRANS_FAULT_RSPCNTRL__VMID3__SHIFT 0x3 87 #define ATC_TRANS_FAULT_RSPCNTRL__VMID4__SHIFT 0x4 88 #define ATC_TRANS_FAULT_RSPCNTRL__VMID5__SHIFT 0x5 89 #define ATC_TRANS_FAULT_RSPCNTRL__VMID6__SHIFT 0x6 90 #define ATC_TRANS_FAULT_RSPCNTRL__VMID7__SHIFT 0x7 91 #define ATC_TRANS_FAULT_RSPCNTRL__VMID8__SHIFT 0x8 92 #define ATC_TRANS_FAULT_RSPCNTRL__VMID9__SHIFT 0x9 93 #define ATC_TRANS_FAULT_RSPCNTRL__VMID10__SHIFT 0xa 94 #define ATC_TRANS_FAULT_RSPCNTRL__VMID11__SHIFT 0xb 95 #define ATC_TRANS_FAULT_RSPCNTRL__VMID12__SHIFT 0xc 96 #define ATC_TRANS_FAULT_RSPCNTRL__VMID13__SHIFT 0xd 97 #define ATC_TRANS_FAULT_RSPCNTRL__VMID14__SHIFT 0xe 98 #define ATC_TRANS_FAULT_RSPCNTRL__VMID15__SHIFT 0xf 99 #define ATC_TRANS_FAULT_RSPCNTRL__VMID16__SHIFT 0x10 100 #define ATC_TRANS_FAULT_RSPCNTRL__VMID17__SHIFT 0x11 101 #define ATC_TRANS_FAULT_RSPCNTRL__VMID18__SHIFT 0x12 102 #define ATC_TRANS_FAULT_RSPCNTRL__VMID19__SHIFT 0x13 103 #define ATC_TRANS_FAULT_RSPCNTRL__VMID20__SHIFT 0x14 104 #define ATC_TRANS_FAULT_RSPCNTRL__VMID21__SHIFT 0x15 105 #define ATC_TRANS_FAULT_RSPCNTRL__VMID22__SHIFT 0x16 106 #define ATC_TRANS_FAULT_RSPCNTRL__VMID23__SHIFT 0x17 107 #define ATC_TRANS_FAULT_RSPCNTRL__VMID24__SHIFT 0x18 108 #define ATC_TRANS_FAULT_RSPCNTRL__VMID25__SHIFT 0x19 109 #define ATC_TRANS_FAULT_RSPCNTRL__VMID26__SHIFT 0x1a 110 #define ATC_TRANS_FAULT_RSPCNTRL__VMID27__SHIFT 0x1b 111 #define ATC_TRANS_FAULT_RSPCNTRL__VMID28__SHIFT 0x1c 112 #define ATC_TRANS_FAULT_RSPCNTRL__VMID29__SHIFT 0x1d 113 #define ATC_TRANS_FAULT_RSPCNTRL__VMID30__SHIFT 0x1e 114 #define ATC_TRANS_FAULT_RSPCNTRL__VMID31__SHIFT 0x1f 115 #define ATC_TRANS_FAULT_RSPCNTRL__VMID0_MASK 0x00000001L 116 #define ATC_TRANS_FAULT_RSPCNTRL__VMID1_MASK 0x00000002L 117 #define ATC_TRANS_FAULT_RSPCNTRL__VMID2_MASK 0x00000004L 118 #define ATC_TRANS_FAULT_RSPCNTRL__VMID3_MASK 0x00000008L 119 #define ATC_TRANS_FAULT_RSPCNTRL__VMID4_MASK 0x00000010L 120 #define ATC_TRANS_FAULT_RSPCNTRL__VMID5_MASK 0x00000020L 121 #define ATC_TRANS_FAULT_RSPCNTRL__VMID6_MASK 0x00000040L 122 #define ATC_TRANS_FAULT_RSPCNTRL__VMID7_MASK 0x00000080L 123 #define ATC_TRANS_FAULT_RSPCNTRL__VMID8_MASK 0x00000100L 124 #define ATC_TRANS_FAULT_RSPCNTRL__VMID9_MASK 0x00000200L 125 #define ATC_TRANS_FAULT_RSPCNTRL__VMID10_MASK 0x00000400L 126 #define ATC_TRANS_FAULT_RSPCNTRL__VMID11_MASK 0x00000800L 127 #define ATC_TRANS_FAULT_RSPCNTRL__VMID12_MASK 0x00001000L 128 #define ATC_TRANS_FAULT_RSPCNTRL__VMID13_MASK 0x00002000L 129 #define ATC_TRANS_FAULT_RSPCNTRL__VMID14_MASK 0x00004000L 130 #define ATC_TRANS_FAULT_RSPCNTRL__VMID15_MASK 0x00008000L 131 #define ATC_TRANS_FAULT_RSPCNTRL__VMID16_MASK 0x00010000L 132 #define ATC_TRANS_FAULT_RSPCNTRL__VMID17_MASK 0x00020000L 133 #define ATC_TRANS_FAULT_RSPCNTRL__VMID18_MASK 0x00040000L 134 #define ATC_TRANS_FAULT_RSPCNTRL__VMID19_MASK 0x00080000L 135 #define ATC_TRANS_FAULT_RSPCNTRL__VMID20_MASK 0x00100000L 136 #define ATC_TRANS_FAULT_RSPCNTRL__VMID21_MASK 0x00200000L 137 #define ATC_TRANS_FAULT_RSPCNTRL__VMID22_MASK 0x00400000L 138 #define ATC_TRANS_FAULT_RSPCNTRL__VMID23_MASK 0x00800000L 139 #define ATC_TRANS_FAULT_RSPCNTRL__VMID24_MASK 0x01000000L 140 #define ATC_TRANS_FAULT_RSPCNTRL__VMID25_MASK 0x02000000L 141 #define ATC_TRANS_FAULT_RSPCNTRL__VMID26_MASK 0x04000000L 142 #define ATC_TRANS_FAULT_RSPCNTRL__VMID27_MASK 0x08000000L 143 #define ATC_TRANS_FAULT_RSPCNTRL__VMID28_MASK 0x10000000L 144 #define ATC_TRANS_FAULT_RSPCNTRL__VMID29_MASK 0x20000000L 145 #define ATC_TRANS_FAULT_RSPCNTRL__VMID30_MASK 0x40000000L 146 #define ATC_TRANS_FAULT_RSPCNTRL__VMID31_MASK 0x80000000L 147 //ATC_ATS_FAULT_STATUS_INFO2 148 #define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0 149 #define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1 150 #define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID__SHIFT 0x9 151 #define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x00000001L 152 #define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x0000001EL 153 #define ATC_ATS_FAULT_STATUS_INFO2__MMHUB_INV_VMID_MASK 0x00003E00L 154 //ATHUB_MISC_CNTL 155 #define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x6 156 #define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x12 157 #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x13 158 #define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x14 159 #define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x15 160 #define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x1b 161 #define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x1c 162 #define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x00000FC0L 163 #define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00040000L 164 #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00080000L 165 #define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00100000L 166 #define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x07E00000L 167 #define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x08000000L 168 #define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x10000000L 169 //ATC_VMID_PASID_MAPPING_UPDATE_STATUS 170 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0 171 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1 172 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2 173 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3 174 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4 175 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5 176 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6 177 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7 178 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8 179 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9 180 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa 181 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb 182 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc 183 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd 184 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe 185 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf 186 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED__SHIFT 0x10 187 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED__SHIFT 0x11 188 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED__SHIFT 0x12 189 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED__SHIFT 0x13 190 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED__SHIFT 0x14 191 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED__SHIFT 0x15 192 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED__SHIFT 0x16 193 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED__SHIFT 0x17 194 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED__SHIFT 0x18 195 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED__SHIFT 0x19 196 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED__SHIFT 0x1a 197 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED__SHIFT 0x1b 198 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED__SHIFT 0x1c 199 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED__SHIFT 0x1d 200 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED__SHIFT 0x1e 201 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED__SHIFT 0x1f 202 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x00000001L 203 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x00000002L 204 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x00000004L 205 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x00000008L 206 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x00000010L 207 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x00000020L 208 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x00000040L 209 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x00000080L 210 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x00000100L 211 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x00000200L 212 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x00000400L 213 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x00000800L 214 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x00001000L 215 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x00002000L 216 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x00004000L 217 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x00008000L 218 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID16_REMAPPING_FINISHED_MASK 0x00010000L 219 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID17_REMAPPING_FINISHED_MASK 0x00020000L 220 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID18_REMAPPING_FINISHED_MASK 0x00040000L 221 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID19_REMAPPING_FINISHED_MASK 0x00080000L 222 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID20_REMAPPING_FINISHED_MASK 0x00100000L 223 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID21_REMAPPING_FINISHED_MASK 0x00200000L 224 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID22_REMAPPING_FINISHED_MASK 0x00400000L 225 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID23_REMAPPING_FINISHED_MASK 0x00800000L 226 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID24_REMAPPING_FINISHED_MASK 0x01000000L 227 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID25_REMAPPING_FINISHED_MASK 0x02000000L 228 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID26_REMAPPING_FINISHED_MASK 0x04000000L 229 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID27_REMAPPING_FINISHED_MASK 0x08000000L 230 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID28_REMAPPING_FINISHED_MASK 0x10000000L 231 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID29_REMAPPING_FINISHED_MASK 0x20000000L 232 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID30_REMAPPING_FINISHED_MASK 0x40000000L 233 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID31_REMAPPING_FINISHED_MASK 0x80000000L 234 //ATC_VMID0_PASID_MAPPING 235 #define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0 236 #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 237 #define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f 238 #define ATC_VMID0_PASID_MAPPING__PASID_MASK 0x0000FFFFL 239 #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 240 #define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000L 241 //ATC_VMID1_PASID_MAPPING 242 #define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0 243 #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 244 #define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f 245 #define ATC_VMID1_PASID_MAPPING__PASID_MASK 0x0000FFFFL 246 #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 247 #define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000L 248 //ATC_VMID2_PASID_MAPPING 249 #define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0 250 #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 251 #define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f 252 #define ATC_VMID2_PASID_MAPPING__PASID_MASK 0x0000FFFFL 253 #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 254 #define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000L 255 //ATC_VMID3_PASID_MAPPING 256 #define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0 257 #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 258 #define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f 259 #define ATC_VMID3_PASID_MAPPING__PASID_MASK 0x0000FFFFL 260 #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 261 #define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000L 262 //ATC_VMID4_PASID_MAPPING 263 #define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0 264 #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 265 #define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f 266 #define ATC_VMID4_PASID_MAPPING__PASID_MASK 0x0000FFFFL 267 #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 268 #define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000L 269 //ATC_VMID5_PASID_MAPPING 270 #define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0 271 #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 272 #define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f 273 #define ATC_VMID5_PASID_MAPPING__PASID_MASK 0x0000FFFFL 274 #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 275 #define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000L 276 //ATC_VMID6_PASID_MAPPING 277 #define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0 278 #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 279 #define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f 280 #define ATC_VMID6_PASID_MAPPING__PASID_MASK 0x0000FFFFL 281 #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 282 #define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000L 283 //ATC_VMID7_PASID_MAPPING 284 #define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0 285 #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 286 #define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f 287 #define ATC_VMID7_PASID_MAPPING__PASID_MASK 0x0000FFFFL 288 #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 289 #define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000L 290 //ATC_VMID8_PASID_MAPPING 291 #define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0 292 #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 293 #define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f 294 #define ATC_VMID8_PASID_MAPPING__PASID_MASK 0x0000FFFFL 295 #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 296 #define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000L 297 //ATC_VMID9_PASID_MAPPING 298 #define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0 299 #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 300 #define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f 301 #define ATC_VMID9_PASID_MAPPING__PASID_MASK 0x0000FFFFL 302 #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 303 #define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000L 304 //ATC_VMID10_PASID_MAPPING 305 #define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0 306 #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 307 #define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f 308 #define ATC_VMID10_PASID_MAPPING__PASID_MASK 0x0000FFFFL 309 #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 310 #define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000L 311 //ATC_VMID11_PASID_MAPPING 312 #define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0 313 #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 314 #define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f 315 #define ATC_VMID11_PASID_MAPPING__PASID_MASK 0x0000FFFFL 316 #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 317 #define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000L 318 //ATC_VMID12_PASID_MAPPING 319 #define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0 320 #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 321 #define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f 322 #define ATC_VMID12_PASID_MAPPING__PASID_MASK 0x0000FFFFL 323 #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 324 #define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000L 325 //ATC_VMID13_PASID_MAPPING 326 #define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0 327 #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 328 #define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f 329 #define ATC_VMID13_PASID_MAPPING__PASID_MASK 0x0000FFFFL 330 #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 331 #define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000L 332 //ATC_VMID14_PASID_MAPPING 333 #define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0 334 #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 335 #define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f 336 #define ATC_VMID14_PASID_MAPPING__PASID_MASK 0x0000FFFFL 337 #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 338 #define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000L 339 //ATC_VMID15_PASID_MAPPING 340 #define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0 341 #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 342 #define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f 343 #define ATC_VMID15_PASID_MAPPING__PASID_MASK 0x0000FFFFL 344 #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 345 #define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000L 346 //ATC_ATS_VMID_STATUS 347 #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0 348 #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1 349 #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2 350 #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3 351 #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4 352 #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5 353 #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6 354 #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7 355 #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8 356 #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9 357 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa 358 #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb 359 #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc 360 #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd 361 #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe 362 #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf 363 #define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING__SHIFT 0x10 364 #define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING__SHIFT 0x11 365 #define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING__SHIFT 0x12 366 #define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING__SHIFT 0x13 367 #define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING__SHIFT 0x14 368 #define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING__SHIFT 0x15 369 #define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING__SHIFT 0x16 370 #define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING__SHIFT 0x17 371 #define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING__SHIFT 0x18 372 #define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING__SHIFT 0x19 373 #define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING__SHIFT 0x1a 374 #define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING__SHIFT 0x1b 375 #define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING__SHIFT 0x1c 376 #define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING__SHIFT 0x1d 377 #define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING__SHIFT 0x1e 378 #define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING__SHIFT 0x1f 379 #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x00000001L 380 #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x00000002L 381 #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x00000004L 382 #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x00000008L 383 #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x00000010L 384 #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x00000020L 385 #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x00000040L 386 #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x00000080L 387 #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x00000100L 388 #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x00000200L 389 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x00000400L 390 #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x00000800L 391 #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x00001000L 392 #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x00002000L 393 #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x00004000L 394 #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x00008000L 395 #define ATC_ATS_VMID_STATUS__VMID16_OUTSTANDING_MASK 0x00010000L 396 #define ATC_ATS_VMID_STATUS__VMID17_OUTSTANDING_MASK 0x00020000L 397 #define ATC_ATS_VMID_STATUS__VMID18_OUTSTANDING_MASK 0x00040000L 398 #define ATC_ATS_VMID_STATUS__VMID19_OUTSTANDING_MASK 0x00080000L 399 #define ATC_ATS_VMID_STATUS__VMID20_OUTSTANDING_MASK 0x00100000L 400 #define ATC_ATS_VMID_STATUS__VMID21_OUTSTANDING_MASK 0x00200000L 401 #define ATC_ATS_VMID_STATUS__VMID22_OUTSTANDING_MASK 0x00400000L 402 #define ATC_ATS_VMID_STATUS__VMID23_OUTSTANDING_MASK 0x00800000L 403 #define ATC_ATS_VMID_STATUS__VMID24_OUTSTANDING_MASK 0x01000000L 404 #define ATC_ATS_VMID_STATUS__VMID25_OUTSTANDING_MASK 0x02000000L 405 #define ATC_ATS_VMID_STATUS__VMID26_OUTSTANDING_MASK 0x04000000L 406 #define ATC_ATS_VMID_STATUS__VMID27_OUTSTANDING_MASK 0x08000000L 407 #define ATC_ATS_VMID_STATUS__VMID28_OUTSTANDING_MASK 0x10000000L 408 #define ATC_ATS_VMID_STATUS__VMID29_OUTSTANDING_MASK 0x20000000L 409 #define ATC_ATS_VMID_STATUS__VMID30_OUTSTANDING_MASK 0x40000000L 410 #define ATC_ATS_VMID_STATUS__VMID31_OUTSTANDING_MASK 0x80000000L 411 //ATC_ATS_GFX_ATCL2_STATUS 412 #define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 413 #define ATC_ATS_GFX_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L 414 //ATC_PERFCOUNTER0_CFG 415 #define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 416 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 417 #define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 418 #define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 419 #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 420 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 421 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 422 #define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 423 #define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 424 #define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 425 //ATC_PERFCOUNTER1_CFG 426 #define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 427 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 428 #define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 429 #define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 430 #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 431 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 432 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 433 #define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 434 #define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 435 #define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 436 //ATC_PERFCOUNTER2_CFG 437 #define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 438 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 439 #define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 440 #define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 441 #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 442 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 443 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 444 #define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 445 #define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 446 #define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 447 //ATC_PERFCOUNTER3_CFG 448 #define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 449 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 450 #define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 451 #define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 452 #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 453 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 454 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 455 #define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 456 #define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 457 #define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 458 //ATC_PERFCOUNTER_RSLT_CNTL 459 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 460 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 461 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 462 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 463 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 464 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 465 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 466 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 467 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 468 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 469 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 470 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 471 //ATC_PERFCOUNTER_LO 472 #define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 473 #define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 474 //ATC_PERFCOUNTER_HI 475 #define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 476 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 477 #define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 478 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 479 //ATHUB_PCIE_ATS_CNTL 480 #define ATHUB_PCIE_ATS_CNTL__STU__SHIFT 0x10 481 #define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 482 #define ATHUB_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 483 #define ATHUB_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 484 //ATHUB_PCIE_PASID_CNTL 485 #define ATHUB_PCIE_PASID_CNTL__PASID_EN__SHIFT 0x10 486 #define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x11 487 #define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x12 488 #define ATHUB_PCIE_PASID_CNTL__PASID_EN_MASK 0x00010000L 489 #define ATHUB_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x00020000L 490 #define ATHUB_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x00040000L 491 //ATHUB_PCIE_PAGE_REQ_CNTL 492 #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 493 #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 494 #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x00000001L 495 #define ATHUB_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x00000002L 496 //ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC 497 #define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 498 #define ATHUB_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL 499 //ATHUB_COMMAND 500 #define ATHUB_COMMAND__BUS_MASTER_EN__SHIFT 0x2 501 #define ATHUB_COMMAND__BUS_MASTER_EN_MASK 0x00000004L 502 //ATHUB_PCIE_ATS_CNTL_VF_0 503 #define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 504 #define ATHUB_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 505 //ATHUB_PCIE_ATS_CNTL_VF_1 506 #define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 507 #define ATHUB_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 508 //ATHUB_PCIE_ATS_CNTL_VF_2 509 #define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 510 #define ATHUB_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 511 //ATHUB_PCIE_ATS_CNTL_VF_3 512 #define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 513 #define ATHUB_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 514 //ATHUB_PCIE_ATS_CNTL_VF_4 515 #define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 516 #define ATHUB_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 517 //ATHUB_PCIE_ATS_CNTL_VF_5 518 #define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 519 #define ATHUB_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 520 //ATHUB_PCIE_ATS_CNTL_VF_6 521 #define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 522 #define ATHUB_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 523 //ATHUB_PCIE_ATS_CNTL_VF_7 524 #define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 525 #define ATHUB_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 526 //ATHUB_PCIE_ATS_CNTL_VF_8 527 #define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 528 #define ATHUB_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 529 //ATHUB_PCIE_ATS_CNTL_VF_9 530 #define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 531 #define ATHUB_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 532 //ATHUB_PCIE_ATS_CNTL_VF_10 533 #define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 534 #define ATHUB_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 535 //ATHUB_PCIE_ATS_CNTL_VF_11 536 #define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 537 #define ATHUB_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 538 //ATHUB_PCIE_ATS_CNTL_VF_12 539 #define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 540 #define ATHUB_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 541 //ATHUB_PCIE_ATS_CNTL_VF_13 542 #define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 543 #define ATHUB_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 544 //ATHUB_PCIE_ATS_CNTL_VF_14 545 #define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 546 #define ATHUB_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 547 //ATHUB_PCIE_ATS_CNTL_VF_15 548 #define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 549 #define ATHUB_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 550 //ATHUB_MEM_POWER_LS 551 #define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 552 #define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 553 #define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 554 #define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 555 //ATS_IH_CREDIT 556 #define ATS_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 557 #define ATS_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 558 #define ATS_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 559 #define ATS_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 560 //ATHUB_IH_CREDIT 561 #define ATHUB_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 562 #define ATHUB_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 563 #define ATHUB_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 564 #define ATHUB_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 565 //ATC_VMID16_PASID_MAPPING 566 #define ATC_VMID16_PASID_MAPPING__PASID__SHIFT 0x0 567 #define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 568 #define ATC_VMID16_PASID_MAPPING__VALID__SHIFT 0x1f 569 #define ATC_VMID16_PASID_MAPPING__PASID_MASK 0x0000FFFFL 570 #define ATC_VMID16_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 571 #define ATC_VMID16_PASID_MAPPING__VALID_MASK 0x80000000L 572 //ATC_VMID17_PASID_MAPPING 573 #define ATC_VMID17_PASID_MAPPING__PASID__SHIFT 0x0 574 #define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 575 #define ATC_VMID17_PASID_MAPPING__VALID__SHIFT 0x1f 576 #define ATC_VMID17_PASID_MAPPING__PASID_MASK 0x0000FFFFL 577 #define ATC_VMID17_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 578 #define ATC_VMID17_PASID_MAPPING__VALID_MASK 0x80000000L 579 //ATC_VMID18_PASID_MAPPING 580 #define ATC_VMID18_PASID_MAPPING__PASID__SHIFT 0x0 581 #define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 582 #define ATC_VMID18_PASID_MAPPING__VALID__SHIFT 0x1f 583 #define ATC_VMID18_PASID_MAPPING__PASID_MASK 0x0000FFFFL 584 #define ATC_VMID18_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 585 #define ATC_VMID18_PASID_MAPPING__VALID_MASK 0x80000000L 586 //ATC_VMID19_PASID_MAPPING 587 #define ATC_VMID19_PASID_MAPPING__PASID__SHIFT 0x0 588 #define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 589 #define ATC_VMID19_PASID_MAPPING__VALID__SHIFT 0x1f 590 #define ATC_VMID19_PASID_MAPPING__PASID_MASK 0x0000FFFFL 591 #define ATC_VMID19_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 592 #define ATC_VMID19_PASID_MAPPING__VALID_MASK 0x80000000L 593 //ATC_VMID20_PASID_MAPPING 594 #define ATC_VMID20_PASID_MAPPING__PASID__SHIFT 0x0 595 #define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 596 #define ATC_VMID20_PASID_MAPPING__VALID__SHIFT 0x1f 597 #define ATC_VMID20_PASID_MAPPING__PASID_MASK 0x0000FFFFL 598 #define ATC_VMID20_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 599 #define ATC_VMID20_PASID_MAPPING__VALID_MASK 0x80000000L 600 //ATC_VMID21_PASID_MAPPING 601 #define ATC_VMID21_PASID_MAPPING__PASID__SHIFT 0x0 602 #define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 603 #define ATC_VMID21_PASID_MAPPING__VALID__SHIFT 0x1f 604 #define ATC_VMID21_PASID_MAPPING__PASID_MASK 0x0000FFFFL 605 #define ATC_VMID21_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 606 #define ATC_VMID21_PASID_MAPPING__VALID_MASK 0x80000000L 607 //ATC_VMID22_PASID_MAPPING 608 #define ATC_VMID22_PASID_MAPPING__PASID__SHIFT 0x0 609 #define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 610 #define ATC_VMID22_PASID_MAPPING__VALID__SHIFT 0x1f 611 #define ATC_VMID22_PASID_MAPPING__PASID_MASK 0x0000FFFFL 612 #define ATC_VMID22_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 613 #define ATC_VMID22_PASID_MAPPING__VALID_MASK 0x80000000L 614 //ATC_VMID23_PASID_MAPPING 615 #define ATC_VMID23_PASID_MAPPING__PASID__SHIFT 0x0 616 #define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 617 #define ATC_VMID23_PASID_MAPPING__VALID__SHIFT 0x1f 618 #define ATC_VMID23_PASID_MAPPING__PASID_MASK 0x0000FFFFL 619 #define ATC_VMID23_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 620 #define ATC_VMID23_PASID_MAPPING__VALID_MASK 0x80000000L 621 //ATC_VMID24_PASID_MAPPING 622 #define ATC_VMID24_PASID_MAPPING__PASID__SHIFT 0x0 623 #define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 624 #define ATC_VMID24_PASID_MAPPING__VALID__SHIFT 0x1f 625 #define ATC_VMID24_PASID_MAPPING__PASID_MASK 0x0000FFFFL 626 #define ATC_VMID24_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 627 #define ATC_VMID24_PASID_MAPPING__VALID_MASK 0x80000000L 628 //ATC_VMID25_PASID_MAPPING 629 #define ATC_VMID25_PASID_MAPPING__PASID__SHIFT 0x0 630 #define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 631 #define ATC_VMID25_PASID_MAPPING__VALID__SHIFT 0x1f 632 #define ATC_VMID25_PASID_MAPPING__PASID_MASK 0x0000FFFFL 633 #define ATC_VMID25_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 634 #define ATC_VMID25_PASID_MAPPING__VALID_MASK 0x80000000L 635 //ATC_VMID26_PASID_MAPPING 636 #define ATC_VMID26_PASID_MAPPING__PASID__SHIFT 0x0 637 #define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 638 #define ATC_VMID26_PASID_MAPPING__VALID__SHIFT 0x1f 639 #define ATC_VMID26_PASID_MAPPING__PASID_MASK 0x0000FFFFL 640 #define ATC_VMID26_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 641 #define ATC_VMID26_PASID_MAPPING__VALID_MASK 0x80000000L 642 //ATC_VMID27_PASID_MAPPING 643 #define ATC_VMID27_PASID_MAPPING__PASID__SHIFT 0x0 644 #define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 645 #define ATC_VMID27_PASID_MAPPING__VALID__SHIFT 0x1f 646 #define ATC_VMID27_PASID_MAPPING__PASID_MASK 0x0000FFFFL 647 #define ATC_VMID27_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 648 #define ATC_VMID27_PASID_MAPPING__VALID_MASK 0x80000000L 649 //ATC_VMID28_PASID_MAPPING 650 #define ATC_VMID28_PASID_MAPPING__PASID__SHIFT 0x0 651 #define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 652 #define ATC_VMID28_PASID_MAPPING__VALID__SHIFT 0x1f 653 #define ATC_VMID28_PASID_MAPPING__PASID_MASK 0x0000FFFFL 654 #define ATC_VMID28_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 655 #define ATC_VMID28_PASID_MAPPING__VALID_MASK 0x80000000L 656 //ATC_VMID29_PASID_MAPPING 657 #define ATC_VMID29_PASID_MAPPING__PASID__SHIFT 0x0 658 #define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 659 #define ATC_VMID29_PASID_MAPPING__VALID__SHIFT 0x1f 660 #define ATC_VMID29_PASID_MAPPING__PASID_MASK 0x0000FFFFL 661 #define ATC_VMID29_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 662 #define ATC_VMID29_PASID_MAPPING__VALID_MASK 0x80000000L 663 //ATC_VMID30_PASID_MAPPING 664 #define ATC_VMID30_PASID_MAPPING__PASID__SHIFT 0x0 665 #define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 666 #define ATC_VMID30_PASID_MAPPING__VALID__SHIFT 0x1f 667 #define ATC_VMID30_PASID_MAPPING__PASID_MASK 0x0000FFFFL 668 #define ATC_VMID30_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 669 #define ATC_VMID30_PASID_MAPPING__VALID_MASK 0x80000000L 670 //ATC_VMID31_PASID_MAPPING 671 #define ATC_VMID31_PASID_MAPPING__PASID__SHIFT 0x0 672 #define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e 673 #define ATC_VMID31_PASID_MAPPING__VALID__SHIFT 0x1f 674 #define ATC_VMID31_PASID_MAPPING__PASID_MASK 0x0000FFFFL 675 #define ATC_VMID31_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000L 676 #define ATC_VMID31_PASID_MAPPING__VALID_MASK 0x80000000L 677 //ATC_ATS_MMHUB_ATCL2_STATUS 678 #define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN__SHIFT 0x0 679 #define ATC_ATS_MMHUB_ATCL2_STATUS__POWERED_DOWN_MASK 0x00000001L 680 //ATHUB_SHARED_VIRT_RESET_REQ 681 #define ATHUB_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 682 #define ATHUB_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 683 #define ATHUB_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 684 #define ATHUB_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 685 //ATHUB_SHARED_ACTIVE_FCN_ID 686 #define ATHUB_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 687 #define ATHUB_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 688 #define ATHUB_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 689 #define ATHUB_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 690 //ATC_ATS_SDPPORT_CNTL 691 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE__SHIFT 0x0 692 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE__SHIFT 0x1 693 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD__SHIFT 0x3 694 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE__SHIFT 0x7 695 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK__SHIFT 0x8 696 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD__SHIFT 0x9 697 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE__SHIFT 0xd 698 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE__SHIFT 0xe 699 #define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE__SHIFT 0xf 700 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN__SHIFT 0x10 701 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV__SHIFT 0x11 702 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN__SHIFT 0x12 703 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x13 704 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN__SHIFT 0x14 705 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV__SHIFT 0x15 706 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN__SHIFT 0x16 707 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV__SHIFT 0x17 708 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN__SHIFT 0x18 709 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV__SHIFT 0x19 710 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_SELF_ACTIVATE_MASK 0x00000001L 711 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_CFG_MODE_MASK 0x00000006L 712 #define ATC_ATS_SDPPORT_CNTL__ATS_INV_HALT_THRESHOLD_MASK 0x00000078L 713 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_SELF_ACTIVATE_MASK 0x00000080L 714 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_QUICK_COMACK_MASK 0x00000100L 715 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_HALT_THRESHOLD_MASK 0x00001E00L 716 #define ATC_ATS_SDPPORT_CNTL__UTCL2_TRANS_PASSIVE_MODE_MASK 0x00002000L 717 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_RDY_MODE_MASK 0x00004000L 718 #define ATC_ATS_SDPPORT_CNTL__UTCL2_MMHUB_RDY_MODE_MASK 0x00008000L 719 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKEN_MASK 0x00010000L 720 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPCKENRCV_MASK 0x00020000L 721 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKEN_MASK 0x00040000L 722 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_RDRSPDATACKENRCV_MASK 0x00080000L 723 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKEN_MASK 0x00100000L 724 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_WRRSPCKENRCV_MASK 0x00200000L 725 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKEN_MASK 0x00400000L 726 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_REQCKENRCV_MASK 0x00800000L 727 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKEN_MASK 0x01000000L 728 #define ATC_ATS_SDPPORT_CNTL__UTCL2_GFX_SDPVDCI_ORIGDATACKENRCV_MASK 0x02000000L 729 //ATC_ATS_VMID_SNAPSHOT_GFX_STAT 730 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0__SHIFT 0x0 731 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1__SHIFT 0x1 732 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2__SHIFT 0x2 733 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3__SHIFT 0x3 734 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4__SHIFT 0x4 735 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5__SHIFT 0x5 736 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6__SHIFT 0x6 737 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7__SHIFT 0x7 738 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8__SHIFT 0x8 739 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9__SHIFT 0x9 740 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10__SHIFT 0xa 741 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11__SHIFT 0xb 742 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12__SHIFT 0xc 743 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13__SHIFT 0xd 744 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14__SHIFT 0xe 745 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15__SHIFT 0xf 746 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID0_MASK 0x00000001L 747 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID1_MASK 0x00000002L 748 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID2_MASK 0x00000004L 749 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID3_MASK 0x00000008L 750 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID4_MASK 0x00000010L 751 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID5_MASK 0x00000020L 752 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID6_MASK 0x00000040L 753 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID7_MASK 0x00000080L 754 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID8_MASK 0x00000100L 755 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID9_MASK 0x00000200L 756 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID10_MASK 0x00000400L 757 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID11_MASK 0x00000800L 758 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID12_MASK 0x00001000L 759 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID13_MASK 0x00002000L 760 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID14_MASK 0x00004000L 761 #define ATC_ATS_VMID_SNAPSHOT_GFX_STAT__VMID15_MASK 0x00008000L 762 //ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT 763 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0__SHIFT 0x0 764 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1__SHIFT 0x1 765 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2__SHIFT 0x2 766 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3__SHIFT 0x3 767 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4__SHIFT 0x4 768 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5__SHIFT 0x5 769 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6__SHIFT 0x6 770 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7__SHIFT 0x7 771 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8__SHIFT 0x8 772 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9__SHIFT 0x9 773 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10__SHIFT 0xa 774 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11__SHIFT 0xb 775 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12__SHIFT 0xc 776 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13__SHIFT 0xd 777 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14__SHIFT 0xe 778 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15__SHIFT 0xf 779 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID0_MASK 0x00000001L 780 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID1_MASK 0x00000002L 781 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID2_MASK 0x00000004L 782 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID3_MASK 0x00000008L 783 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID4_MASK 0x00000010L 784 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID5_MASK 0x00000020L 785 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID6_MASK 0x00000040L 786 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID7_MASK 0x00000080L 787 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID8_MASK 0x00000100L 788 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID9_MASK 0x00000200L 789 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID10_MASK 0x00000400L 790 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID11_MASK 0x00000800L 791 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID12_MASK 0x00001000L 792 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID13_MASK 0x00002000L 793 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID14_MASK 0x00004000L 794 #define ATC_ATS_VMID_SNAPSHOT_MMHUB_STAT__VMID15_MASK 0x00008000L 795 796 797 // addressBlock: athub_xpbdec 798 //XPB_RTR_SRC_APRTR0 799 #define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 800 #define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 801 //XPB_RTR_SRC_APRTR1 802 #define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 803 #define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 804 //XPB_RTR_SRC_APRTR2 805 #define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 806 #define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 807 //XPB_RTR_SRC_APRTR3 808 #define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 809 #define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 810 //XPB_RTR_SRC_APRTR4 811 #define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 812 #define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL 813 //XPB_RTR_SRC_APRTR5 814 #define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 815 #define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL 816 //XPB_RTR_SRC_APRTR6 817 #define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 818 #define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL 819 //XPB_RTR_SRC_APRTR7 820 #define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 821 #define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL 822 //XPB_RTR_SRC_APRTR8 823 #define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 824 #define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL 825 //XPB_RTR_SRC_APRTR9 826 #define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 827 #define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL 828 //XPB_XDMA_RTR_SRC_APRTR0 829 #define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 830 #define XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 831 //XPB_XDMA_RTR_SRC_APRTR1 832 #define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 833 #define XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 834 //XPB_XDMA_RTR_SRC_APRTR2 835 #define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 836 #define XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 837 //XPB_XDMA_RTR_SRC_APRTR3 838 #define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 839 #define XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 840 //XPB_RTR_DEST_MAP0 841 #define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 842 #define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 843 #define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 844 #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 845 #define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 846 #define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L 847 #define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 848 #define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 849 #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 850 #define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 851 //XPB_RTR_DEST_MAP1 852 #define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 853 #define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 854 #define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 855 #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 856 #define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 857 #define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L 858 #define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 859 #define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 860 #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 861 #define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 862 //XPB_RTR_DEST_MAP2 863 #define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 864 #define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 865 #define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 866 #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 867 #define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 868 #define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L 869 #define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 870 #define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 871 #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 872 #define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 873 //XPB_RTR_DEST_MAP3 874 #define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 875 #define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 876 #define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 877 #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 878 #define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 879 #define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L 880 #define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 881 #define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 882 #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 883 #define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 884 //XPB_RTR_DEST_MAP4 885 #define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 886 #define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 887 #define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 888 #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 889 #define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a 890 #define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L 891 #define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL 892 #define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L 893 #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L 894 #define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L 895 //XPB_RTR_DEST_MAP5 896 #define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 897 #define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 898 #define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 899 #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 900 #define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a 901 #define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L 902 #define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL 903 #define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L 904 #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L 905 #define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L 906 //XPB_RTR_DEST_MAP6 907 #define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 908 #define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 909 #define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 910 #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 911 #define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a 912 #define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L 913 #define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL 914 #define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L 915 #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L 916 #define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L 917 //XPB_RTR_DEST_MAP7 918 #define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 919 #define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 920 #define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 921 #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 922 #define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a 923 #define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L 924 #define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL 925 #define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L 926 #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L 927 #define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L 928 //XPB_RTR_DEST_MAP8 929 #define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 930 #define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 931 #define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 932 #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 933 #define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a 934 #define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L 935 #define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL 936 #define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L 937 #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L 938 #define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L 939 //XPB_RTR_DEST_MAP9 940 #define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 941 #define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 942 #define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 943 #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 944 #define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a 945 #define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L 946 #define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL 947 #define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L 948 #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L 949 #define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L 950 //XPB_XDMA_RTR_DEST_MAP0 951 #define XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0 952 #define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 953 #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 954 #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 955 #define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 956 #define XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x00000001L 957 #define XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 958 #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 959 #define XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 960 #define XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 961 //XPB_XDMA_RTR_DEST_MAP1 962 #define XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0 963 #define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 964 #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 965 #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 966 #define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 967 #define XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x00000001L 968 #define XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 969 #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 970 #define XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 971 #define XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 972 //XPB_XDMA_RTR_DEST_MAP2 973 #define XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0 974 #define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 975 #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 976 #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 977 #define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 978 #define XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x00000001L 979 #define XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 980 #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 981 #define XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 982 #define XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 983 //XPB_XDMA_RTR_DEST_MAP3 984 #define XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0 985 #define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 986 #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 987 #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 988 #define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 989 #define XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x00000001L 990 #define XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 991 #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 992 #define XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 993 #define XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 994 //XPB_CLG_CFG0 995 #define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 996 #define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 997 #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 998 #define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL 999 #define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L 1000 #define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L 1001 //XPB_CLG_CFG1 1002 #define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 1003 #define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 1004 #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 1005 #define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL 1006 #define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L 1007 #define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L 1008 //XPB_CLG_CFG2 1009 #define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 1010 #define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 1011 #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 1012 #define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL 1013 #define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L 1014 #define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L 1015 //XPB_CLG_CFG3 1016 #define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 1017 #define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 1018 #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 1019 #define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL 1020 #define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L 1021 #define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L 1022 //XPB_CLG_CFG4 1023 #define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 1024 #define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 1025 #define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 1026 #define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL 1027 #define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L 1028 #define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L 1029 //XPB_CLG_CFG5 1030 #define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 1031 #define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 1032 #define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 1033 #define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL 1034 #define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L 1035 #define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L 1036 //XPB_CLG_CFG6 1037 #define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 1038 #define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 1039 #define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 1040 #define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL 1041 #define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L 1042 #define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L 1043 //XPB_CLG_CFG7 1044 #define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 1045 #define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 1046 #define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 1047 #define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL 1048 #define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L 1049 #define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L 1050 //XPB_CLG_EXTRA 1051 #define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 1052 #define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 1053 #define XPB_CLG_EXTRA__VLD0__SHIFT 0xb 1054 #define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc 1055 #define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf 1056 #define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 1057 #define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a 1058 #define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b 1059 #define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL 1060 #define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L 1061 #define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L 1062 #define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L 1063 #define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L 1064 #define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L 1065 #define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L 1066 #define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L 1067 //XPB_CLG_EXTRA_MSK 1068 #define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 1069 #define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 1070 #define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb 1071 #define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 1072 #define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL 1073 #define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L 1074 #define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L 1075 #define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L 1076 //XPB_LB_ADDR 1077 #define XPB_LB_ADDR__CMP0__SHIFT 0x0 1078 #define XPB_LB_ADDR__MASK0__SHIFT 0xa 1079 #define XPB_LB_ADDR__CMP1__SHIFT 0x14 1080 #define XPB_LB_ADDR__MASK1__SHIFT 0x1a 1081 #define XPB_LB_ADDR__CMP0_MASK 0x000003FFL 1082 #define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L 1083 #define XPB_LB_ADDR__CMP1_MASK 0x03F00000L 1084 #define XPB_LB_ADDR__MASK1_MASK 0xFC000000L 1085 //XPB_WCB_STS 1086 #define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 1087 #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 1088 #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 1089 #define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL 1090 #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L 1091 #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L 1092 //XPB_HST_CFG 1093 #define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 1094 #define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L 1095 //XPB_P2P_BAR_CFG 1096 #define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 1097 #define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 1098 #define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 1099 #define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 1100 #define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 1101 #define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 1102 #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa 1103 #define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb 1104 #define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc 1105 #define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL 1106 #define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L 1107 #define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L 1108 #define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L 1109 #define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L 1110 #define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L 1111 #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L 1112 #define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L 1113 #define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L 1114 //XPB_P2P_BAR0 1115 #define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 1116 #define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 1117 #define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 1118 #define XPB_P2P_BAR0__VALID__SHIFT 0xc 1119 #define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd 1120 #define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe 1121 #define XPB_P2P_BAR0__RESERVED__SHIFT 0xf 1122 #define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 1123 #define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL 1124 #define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L 1125 #define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L 1126 #define XPB_P2P_BAR0__VALID_MASK 0x00001000L 1127 #define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L 1128 #define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L 1129 #define XPB_P2P_BAR0__RESERVED_MASK 0x00008000L 1130 #define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L 1131 //XPB_P2P_BAR1 1132 #define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 1133 #define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 1134 #define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 1135 #define XPB_P2P_BAR1__VALID__SHIFT 0xc 1136 #define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd 1137 #define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe 1138 #define XPB_P2P_BAR1__RESERVED__SHIFT 0xf 1139 #define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 1140 #define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL 1141 #define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L 1142 #define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L 1143 #define XPB_P2P_BAR1__VALID_MASK 0x00001000L 1144 #define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L 1145 #define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L 1146 #define XPB_P2P_BAR1__RESERVED_MASK 0x00008000L 1147 #define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L 1148 //XPB_P2P_BAR2 1149 #define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 1150 #define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 1151 #define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 1152 #define XPB_P2P_BAR2__VALID__SHIFT 0xc 1153 #define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd 1154 #define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe 1155 #define XPB_P2P_BAR2__RESERVED__SHIFT 0xf 1156 #define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 1157 #define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL 1158 #define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L 1159 #define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L 1160 #define XPB_P2P_BAR2__VALID_MASK 0x00001000L 1161 #define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L 1162 #define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L 1163 #define XPB_P2P_BAR2__RESERVED_MASK 0x00008000L 1164 #define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L 1165 //XPB_P2P_BAR3 1166 #define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 1167 #define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 1168 #define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 1169 #define XPB_P2P_BAR3__VALID__SHIFT 0xc 1170 #define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd 1171 #define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe 1172 #define XPB_P2P_BAR3__RESERVED__SHIFT 0xf 1173 #define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 1174 #define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL 1175 #define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L 1176 #define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L 1177 #define XPB_P2P_BAR3__VALID_MASK 0x00001000L 1178 #define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L 1179 #define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L 1180 #define XPB_P2P_BAR3__RESERVED_MASK 0x00008000L 1181 #define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L 1182 //XPB_P2P_BAR4 1183 #define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 1184 #define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 1185 #define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 1186 #define XPB_P2P_BAR4__VALID__SHIFT 0xc 1187 #define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd 1188 #define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe 1189 #define XPB_P2P_BAR4__RESERVED__SHIFT 0xf 1190 #define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 1191 #define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL 1192 #define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L 1193 #define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L 1194 #define XPB_P2P_BAR4__VALID_MASK 0x00001000L 1195 #define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L 1196 #define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L 1197 #define XPB_P2P_BAR4__RESERVED_MASK 0x00008000L 1198 #define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L 1199 //XPB_P2P_BAR5 1200 #define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 1201 #define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 1202 #define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 1203 #define XPB_P2P_BAR5__VALID__SHIFT 0xc 1204 #define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd 1205 #define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe 1206 #define XPB_P2P_BAR5__RESERVED__SHIFT 0xf 1207 #define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 1208 #define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL 1209 #define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L 1210 #define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L 1211 #define XPB_P2P_BAR5__VALID_MASK 0x00001000L 1212 #define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L 1213 #define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L 1214 #define XPB_P2P_BAR5__RESERVED_MASK 0x00008000L 1215 #define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L 1216 //XPB_P2P_BAR6 1217 #define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 1218 #define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 1219 #define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 1220 #define XPB_P2P_BAR6__VALID__SHIFT 0xc 1221 #define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd 1222 #define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe 1223 #define XPB_P2P_BAR6__RESERVED__SHIFT 0xf 1224 #define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 1225 #define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL 1226 #define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L 1227 #define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L 1228 #define XPB_P2P_BAR6__VALID_MASK 0x00001000L 1229 #define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L 1230 #define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L 1231 #define XPB_P2P_BAR6__RESERVED_MASK 0x00008000L 1232 #define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L 1233 //XPB_P2P_BAR7 1234 #define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 1235 #define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 1236 #define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 1237 #define XPB_P2P_BAR7__VALID__SHIFT 0xc 1238 #define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd 1239 #define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe 1240 #define XPB_P2P_BAR7__RESERVED__SHIFT 0xf 1241 #define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 1242 #define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL 1243 #define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L 1244 #define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L 1245 #define XPB_P2P_BAR7__VALID_MASK 0x00001000L 1246 #define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L 1247 #define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L 1248 #define XPB_P2P_BAR7__RESERVED_MASK 0x00008000L 1249 #define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L 1250 //XPB_P2P_BAR_SETUP 1251 #define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 1252 #define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 1253 #define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc 1254 #define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd 1255 #define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe 1256 #define XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf 1257 #define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 1258 #define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL 1259 #define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L 1260 #define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L 1261 #define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L 1262 #define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L 1263 #define XPB_P2P_BAR_SETUP__RESERVED_MASK 0x00008000L 1264 #define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L 1265 //XPB_P2P_BAR_DELTA_ABOVE 1266 #define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 1267 #define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 1268 #define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL 1269 #define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L 1270 //XPB_P2P_BAR_DELTA_BELOW 1271 #define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 1272 #define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 1273 #define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL 1274 #define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L 1275 //XPB_PEER_SYS_BAR0 1276 #define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 1277 #define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 1278 #define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L 1279 #define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 1280 //XPB_PEER_SYS_BAR1 1281 #define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 1282 #define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 1283 #define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L 1284 #define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 1285 //XPB_PEER_SYS_BAR2 1286 #define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 1287 #define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 1288 #define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L 1289 #define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 1290 //XPB_PEER_SYS_BAR3 1291 #define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 1292 #define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 1293 #define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L 1294 #define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 1295 //XPB_PEER_SYS_BAR4 1296 #define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 1297 #define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 1298 #define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L 1299 #define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL 1300 //XPB_PEER_SYS_BAR5 1301 #define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 1302 #define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 1303 #define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L 1304 #define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL 1305 //XPB_PEER_SYS_BAR6 1306 #define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 1307 #define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 1308 #define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L 1309 #define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL 1310 //XPB_PEER_SYS_BAR7 1311 #define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 1312 #define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 1313 #define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L 1314 #define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL 1315 //XPB_PEER_SYS_BAR8 1316 #define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 1317 #define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 1318 #define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L 1319 #define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL 1320 //XPB_PEER_SYS_BAR9 1321 #define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 1322 #define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 1323 #define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L 1324 #define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL 1325 //XPB_XDMA_PEER_SYS_BAR0 1326 #define XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0 1327 #define XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x1 1328 #define XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x00000001L 1329 #define XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 1330 //XPB_XDMA_PEER_SYS_BAR1 1331 #define XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0 1332 #define XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x1 1333 #define XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x00000001L 1334 #define XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 1335 //XPB_XDMA_PEER_SYS_BAR2 1336 #define XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0 1337 #define XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x1 1338 #define XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x00000001L 1339 #define XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 1340 //XPB_XDMA_PEER_SYS_BAR3 1341 #define XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0 1342 #define XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x1 1343 #define XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x00000001L 1344 #define XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 1345 //XPB_CLK_GAT 1346 #define XPB_CLK_GAT__ONDLY__SHIFT 0x0 1347 #define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 1348 #define XPB_CLK_GAT__RDYDLY__SHIFT 0xc 1349 #define XPB_CLK_GAT__ENABLE__SHIFT 0x12 1350 #define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 1351 #define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL 1352 #define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L 1353 #define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L 1354 #define XPB_CLK_GAT__ENABLE_MASK 0x00040000L 1355 #define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L 1356 //XPB_INTF_CFG 1357 #define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 1358 #define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 1359 #define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 1360 #define XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17 1361 #define XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18 1362 #define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19 1363 #define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a 1364 #define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b 1365 #define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 1366 #define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e 1367 #define XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f 1368 #define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL 1369 #define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L 1370 #define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L 1371 #define XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x00800000L 1372 #define XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x01000000L 1373 #define XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x02000000L 1374 #define XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x04000000L 1375 #define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L 1376 #define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L 1377 #define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L 1378 #define XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000L 1379 //XPB_INTF_STS 1380 #define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 1381 #define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 1382 #define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf 1383 #define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 1384 #define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 1385 #define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 1386 #define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 1387 #define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL 1388 #define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L 1389 #define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L 1390 #define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L 1391 #define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L 1392 #define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L 1393 #define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L 1394 //XPB_PIPE_STS 1395 #define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 1396 #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 1397 #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 1398 #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf 1399 #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 1400 #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 1401 #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 1402 #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 1403 #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 1404 #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 1405 #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 1406 #define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 1407 #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 1408 #define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L 1409 #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL 1410 #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L 1411 #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L 1412 #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L 1413 #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L 1414 #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L 1415 #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L 1416 #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L 1417 #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L 1418 #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L 1419 #define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L 1420 #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L 1421 //XPB_SUB_CTRL 1422 #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 1423 #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 1424 #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 1425 #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 1426 #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 1427 #define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 1428 #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 1429 #define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 1430 #define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 1431 #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 1432 #define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa 1433 #define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb 1434 #define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc 1435 #define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd 1436 #define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe 1437 #define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf 1438 #define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 1439 #define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 1440 #define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 1441 #define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 1442 #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L 1443 #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L 1444 #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L 1445 #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L 1446 #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L 1447 #define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L 1448 #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L 1449 #define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L 1450 #define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L 1451 #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L 1452 #define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L 1453 #define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L 1454 #define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L 1455 #define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L 1456 #define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L 1457 #define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L 1458 #define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L 1459 #define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L 1460 #define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L 1461 #define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L 1462 //XPB_MAP_INVERT_FLUSH_NUM_LSB 1463 #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 1464 #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL 1465 //XPB_PERF_KNOBS 1466 #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 1467 #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 1468 #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc 1469 #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL 1470 #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L 1471 #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L 1472 //XPB_STICKY 1473 #define XPB_STICKY__BITS__SHIFT 0x0 1474 #define XPB_STICKY__BITS_MASK 0xFFFFFFFFL 1475 //XPB_STICKY_W1C 1476 #define XPB_STICKY_W1C__BITS__SHIFT 0x0 1477 #define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL 1478 //XPB_MISC_CFG 1479 #define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 1480 #define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 1481 #define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 1482 #define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 1483 #define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f 1484 #define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL 1485 #define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L 1486 #define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L 1487 #define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L 1488 #define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L 1489 //XPB_INTF_CFG2 1490 #define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 1491 #define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL 1492 //XPB_CLG_EXTRA_RD 1493 #define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 1494 #define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 1495 #define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb 1496 #define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc 1497 #define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf 1498 #define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 1499 #define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a 1500 #define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b 1501 #define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL 1502 #define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L 1503 #define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L 1504 #define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L 1505 #define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L 1506 #define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L 1507 #define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L 1508 #define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L 1509 //XPB_CLG_EXTRA_MSK_RD 1510 #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 1511 #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 1512 #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb 1513 #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 1514 #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL 1515 #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L 1516 #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L 1517 #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L 1518 //XPB_CLG_GFX_MATCH 1519 #define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 1520 #define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 1521 #define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc 1522 #define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 1523 #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 1524 #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 1525 #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a 1526 #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b 1527 #define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL 1528 #define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 1529 #define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L 1530 #define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L 1531 #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L 1532 #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L 1533 #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L 1534 #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L 1535 //XPB_CLG_GFX_MATCH_MSK 1536 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1537 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 1538 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc 1539 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 1540 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 1541 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 1542 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L 1543 #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L 1544 //XPB_CLG_MM_MATCH 1545 #define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 1546 #define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 1547 #define XPB_CLG_MM_MATCH__FARBIRC2_ID__SHIFT 0xc 1548 #define XPB_CLG_MM_MATCH__FARBIRC3_ID__SHIFT 0x12 1549 #define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0x18 1550 #define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0x19 1551 #define XPB_CLG_MM_MATCH__FARBIRC2_VLD__SHIFT 0x1a 1552 #define XPB_CLG_MM_MATCH__FARBIRC3_VLD__SHIFT 0x1b 1553 #define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL 1554 #define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 1555 #define XPB_CLG_MM_MATCH__FARBIRC2_ID_MASK 0x0003F000L 1556 #define XPB_CLG_MM_MATCH__FARBIRC3_ID_MASK 0x00FC0000L 1557 #define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x01000000L 1558 #define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x02000000L 1559 #define XPB_CLG_MM_MATCH__FARBIRC2_VLD_MASK 0x04000000L 1560 #define XPB_CLG_MM_MATCH__FARBIRC3_VLD_MASK 0x08000000L 1561 //XPB_CLG_MM_MATCH_MSK 1562 #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 1563 #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 1564 #define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc 1565 #define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 1566 #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 1567 #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 1568 #define XPB_CLG_MM_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L 1569 #define XPB_CLG_MM_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L 1570 //XPB_CLG_GFX_UNITID_MAPPING0 1571 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1572 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1573 #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1574 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1575 #define XPB_CLG_GFX_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1576 #define XPB_CLG_GFX_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1577 //XPB_CLG_GFX_UNITID_MAPPING1 1578 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1579 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1580 #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1581 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1582 #define XPB_CLG_GFX_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1583 #define XPB_CLG_GFX_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1584 //XPB_CLG_GFX_UNITID_MAPPING2 1585 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1586 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1587 #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1588 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1589 #define XPB_CLG_GFX_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1590 #define XPB_CLG_GFX_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1591 //XPB_CLG_GFX_UNITID_MAPPING3 1592 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1593 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1594 #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1595 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1596 #define XPB_CLG_GFX_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1597 #define XPB_CLG_GFX_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1598 //XPB_CLG_GFX_UNITID_MAPPING4 1599 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW__SHIFT 0x0 1600 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD__SHIFT 0x5 1601 #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM__SHIFT 0x6 1602 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_LOW_MASK 0x0000001FL 1603 #define XPB_CLG_GFX_UNITID_MAPPING4__UNITID_VLD_MASK 0x00000020L 1604 #define XPB_CLG_GFX_UNITID_MAPPING4__DEST_CLG_NUM_MASK 0x000001C0L 1605 //XPB_CLG_GFX_UNITID_MAPPING5 1606 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW__SHIFT 0x0 1607 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD__SHIFT 0x5 1608 #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM__SHIFT 0x6 1609 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_LOW_MASK 0x0000001FL 1610 #define XPB_CLG_GFX_UNITID_MAPPING5__UNITID_VLD_MASK 0x00000020L 1611 #define XPB_CLG_GFX_UNITID_MAPPING5__DEST_CLG_NUM_MASK 0x000001C0L 1612 //XPB_CLG_GFX_UNITID_MAPPING6 1613 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW__SHIFT 0x0 1614 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD__SHIFT 0x5 1615 #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM__SHIFT 0x6 1616 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_LOW_MASK 0x0000001FL 1617 #define XPB_CLG_GFX_UNITID_MAPPING6__UNITID_VLD_MASK 0x00000020L 1618 #define XPB_CLG_GFX_UNITID_MAPPING6__DEST_CLG_NUM_MASK 0x000001C0L 1619 //XPB_CLG_GFX_UNITID_MAPPING7 1620 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW__SHIFT 0x0 1621 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD__SHIFT 0x5 1622 #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM__SHIFT 0x6 1623 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_LOW_MASK 0x0000001FL 1624 #define XPB_CLG_GFX_UNITID_MAPPING7__UNITID_VLD_MASK 0x00000020L 1625 #define XPB_CLG_GFX_UNITID_MAPPING7__DEST_CLG_NUM_MASK 0x000001C0L 1626 //XPB_CLG_MM_UNITID_MAPPING0 1627 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW__SHIFT 0x0 1628 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD__SHIFT 0x5 1629 #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM__SHIFT 0x6 1630 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_LOW_MASK 0x0000001FL 1631 #define XPB_CLG_MM_UNITID_MAPPING0__UNITID_VLD_MASK 0x00000020L 1632 #define XPB_CLG_MM_UNITID_MAPPING0__DEST_CLG_NUM_MASK 0x000001C0L 1633 //XPB_CLG_MM_UNITID_MAPPING1 1634 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW__SHIFT 0x0 1635 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD__SHIFT 0x5 1636 #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM__SHIFT 0x6 1637 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_LOW_MASK 0x0000001FL 1638 #define XPB_CLG_MM_UNITID_MAPPING1__UNITID_VLD_MASK 0x00000020L 1639 #define XPB_CLG_MM_UNITID_MAPPING1__DEST_CLG_NUM_MASK 0x000001C0L 1640 //XPB_CLG_MM_UNITID_MAPPING2 1641 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW__SHIFT 0x0 1642 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD__SHIFT 0x5 1643 #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM__SHIFT 0x6 1644 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_LOW_MASK 0x0000001FL 1645 #define XPB_CLG_MM_UNITID_MAPPING2__UNITID_VLD_MASK 0x00000020L 1646 #define XPB_CLG_MM_UNITID_MAPPING2__DEST_CLG_NUM_MASK 0x000001C0L 1647 //XPB_CLG_MM_UNITID_MAPPING3 1648 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW__SHIFT 0x0 1649 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD__SHIFT 0x5 1650 #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM__SHIFT 0x6 1651 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_LOW_MASK 0x0000001FL 1652 #define XPB_CLG_MM_UNITID_MAPPING3__UNITID_VLD_MASK 0x00000020L 1653 #define XPB_CLG_MM_UNITID_MAPPING3__DEST_CLG_NUM_MASK 0x000001C0L 1654 1655 1656 // addressBlock: athub_rpbdec 1657 //RPB_PASSPW_CONF 1658 #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 1659 #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 1660 #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT 0x2 1661 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0x3 1662 #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0x4 1663 #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x5 1664 #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0x6 1665 #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x7 1666 #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT 0x8 1667 #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x9 1668 #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0xa 1669 #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT 0xb 1670 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xc 1671 #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd 1672 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0xe 1673 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0xf 1674 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x10 1675 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x11 1676 #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L 1677 #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L 1678 #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK 0x00000004L 1679 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000008L 1680 #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00000010L 1681 #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00000020L 1682 #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00000040L 1683 #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00000080L 1684 #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK 0x00000100L 1685 #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00000200L 1686 #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00000400L 1687 #define RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK 0x00000800L 1688 #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00001000L 1689 #define RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L 1690 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00004000L 1691 #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00008000L 1692 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00010000L 1693 #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00020000L 1694 //RPB_BLOCKLEVEL_CONF 1695 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 1696 #define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT 0x2 1697 #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x4 1698 #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x6 1699 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0x8 1700 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xa 1701 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0xc 1702 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xe 1703 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xf 1704 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 1705 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x11 1706 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L 1707 #define RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK 0x0000000CL 1708 #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000030L 1709 #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x000000C0L 1710 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00000300L 1711 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x00000C00L 1712 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00003000L 1713 #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00004000L 1714 #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00008000L 1715 #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L 1716 #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00020000L 1717 //RPB_TAG_CONF 1718 #define RPB_TAG_CONF__RPB_ATS_TR__SHIFT 0x0 1719 #define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0x8 1720 #define RPB_TAG_CONF__RPB_ATS_PR__SHIFT 0x10 1721 #define RPB_TAG_CONF__RPB_ATS_TR_MASK 0x000000FFL 1722 #define RPB_TAG_CONF__RPB_IO_WR_MASK 0x0000FF00L 1723 #define RPB_TAG_CONF__RPB_ATS_PR_MASK 0x00FF0000L 1724 //RPB_EFF_CNTL 1725 #define RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0 1726 #define RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8 1727 #define RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0x000000FFL 1728 #define RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0x0000FF00L 1729 //RPB_ARB_CNTL 1730 #define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 1731 #define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 1732 #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 1733 #define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 1734 #define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 1735 #define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL 1736 #define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L 1737 #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L 1738 #define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L 1739 #define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L 1740 //RPB_ARB_CNTL2 1741 #define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 1742 #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 1743 #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 1744 #define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL 1745 #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L 1746 #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L 1747 //RPB_BIF_CNTL 1748 #define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 1749 #define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 1750 #define RPB_BIF_CNTL__ARB_MODE__SHIFT 0x10 1751 #define RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT 0x11 1752 #define RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT 0x12 1753 #define RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT 0x13 1754 #define RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT 0x1b 1755 #define RPB_BIF_CNTL__TR_PRI_EN__SHIFT 0x1c 1756 #define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT 0x1d 1757 #define RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT 0x1e 1758 #define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL 1759 #define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L 1760 #define RPB_BIF_CNTL__ARB_MODE_MASK 0x00010000L 1761 #define RPB_BIF_CNTL__DRAIN_VC_NUM_MASK 0x00020000L 1762 #define RPB_BIF_CNTL__SWITCH_ENABLE_MASK 0x00040000L 1763 #define RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK 0x07F80000L 1764 #define RPB_BIF_CNTL__PAGE_PRI_EN_MASK 0x08000000L 1765 #define RPB_BIF_CNTL__TR_PRI_EN_MASK 0x10000000L 1766 #define RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK 0x20000000L 1767 #define RPB_BIF_CNTL__PARITY_CHECK_EN_MASK 0x40000000L 1768 //RPB_WR_SWITCH_CNTL 1769 #define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 1770 #define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 1771 #define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe 1772 #define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 1773 #define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c 1774 #define RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL 1775 #define RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L 1776 #define RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L 1777 #define RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L 1778 #define RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L 1779 //RPB_RD_SWITCH_CNTL 1780 #define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0 1781 #define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x7 1782 #define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0xe 1783 #define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x15 1784 #define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT 0x1c 1785 #define RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0x0000007FL 1786 #define RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0x00003F80L 1787 #define RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0x001FC000L 1788 #define RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0x0FE00000L 1789 #define RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK 0x10000000L 1790 //RPB_CID_QUEUE_WR 1791 #define RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT 0x0 1792 #define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT 0x5 1793 #define RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0xb 1794 #define RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0xc 1795 #define RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xf 1796 #define RPB_CID_QUEUE_WR__UPDATE__SHIFT 0x12 1797 #define RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK 0x0000001FL 1798 #define RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK 0x000007E0L 1799 #define RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x00000800L 1800 #define RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x00007000L 1801 #define RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x00038000L 1802 #define RPB_CID_QUEUE_WR__UPDATE_MASK 0x00040000L 1803 //RPB_CID_QUEUE_RD 1804 #define RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT 0x0 1805 #define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT 0x5 1806 #define RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0xb 1807 #define RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xe 1808 #define RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK 0x0000001FL 1809 #define RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK 0x000007E0L 1810 #define RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x00003800L 1811 #define RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0x0001C000L 1812 //RPB_CID_QUEUE_EX 1813 #define RPB_CID_QUEUE_EX__START__SHIFT 0x0 1814 #define RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1 1815 #define RPB_CID_QUEUE_EX__START_MASK 0x00000001L 1816 #define RPB_CID_QUEUE_EX__OFFSET_MASK 0x000001FEL 1817 //RPB_CID_QUEUE_EX_DATA 1818 #define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0 1819 #define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10 1820 #define RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0x0000FFFFL 1821 #define RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xFFFF0000L 1822 //RPB_SWITCH_CNTL2 1823 #define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT 0x0 1824 #define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT 0x7 1825 #define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT 0xe 1826 #define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT 0x15 1827 #define RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK 0x0000007FL 1828 #define RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK 0x00003F80L 1829 #define RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK 0x001FC000L 1830 #define RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK 0x0FE00000L 1831 //RPB_DEINTRLV_COMBINE_CNTL 1832 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 1833 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 1834 #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 1835 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL 1836 #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L 1837 #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L 1838 //RPB_VC_SWITCH_RDWR 1839 #define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 1840 #define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 1841 #define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa 1842 #define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L 1843 #define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL 1844 #define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L 1845 //RPB_PERFCOUNTER_LO 1846 #define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1847 #define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1848 //RPB_PERFCOUNTER_HI 1849 #define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1850 #define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1851 #define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1852 #define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1853 //RPB_PERFCOUNTER0_CFG 1854 #define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1855 #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1856 #define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1857 #define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1858 #define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1859 #define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1860 #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1861 #define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1862 #define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1863 #define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1864 //RPB_PERFCOUNTER1_CFG 1865 #define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1866 #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1867 #define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1868 #define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1869 #define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1870 #define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1871 #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1872 #define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1873 #define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1874 #define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1875 //RPB_PERFCOUNTER2_CFG 1876 #define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1877 #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1878 #define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1879 #define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1880 #define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1881 #define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1882 #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1883 #define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1884 #define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1885 #define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1886 //RPB_PERFCOUNTER3_CFG 1887 #define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 1888 #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 1889 #define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 1890 #define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 1891 #define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 1892 #define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 1893 #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 1894 #define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 1895 #define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 1896 #define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 1897 //RPB_PERFCOUNTER_RSLT_CNTL 1898 #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1899 #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1900 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1901 #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1902 #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1903 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1904 #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1905 #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1906 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1907 #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1908 #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1909 #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1910 //RPB_RD_QUEUE_CNTL 1911 #define RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 1912 #define RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 1913 #define RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 1914 #define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 1915 #define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 1916 #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 1917 #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa 1918 #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 1919 #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 1920 #define RPB_RD_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L 1921 #define RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L 1922 #define RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L 1923 #define RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L 1924 #define RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L 1925 #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L 1926 #define RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L 1927 #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L 1928 #define RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L 1929 //RPB_RD_QUEUE_CNTL2 1930 #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 1931 #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 1932 #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb 1933 #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 1934 #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL 1935 #define RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L 1936 #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L 1937 #define RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L 1938 //RPB_WR_QUEUE_CNTL 1939 #define RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT 0x0 1940 #define RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT 0x1 1941 #define RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT 0x2 1942 #define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT 0x3 1943 #define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT 0x4 1944 #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT 0x5 1945 #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT 0xa 1946 #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT 0x10 1947 #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT 0x15 1948 #define RPB_WR_QUEUE_CNTL__ARB_MODE_MASK 0x00000001L 1949 #define RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK 0x00000002L 1950 #define RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK 0x00000004L 1951 #define RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK 0x00000008L 1952 #define RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK 0x00000010L 1953 #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK 0x000003E0L 1954 #define RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK 0x0000FC00L 1955 #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK 0x001F0000L 1956 #define RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK 0x07E00000L 1957 //RPB_WR_QUEUE_CNTL2 1958 #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT 0x0 1959 #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT 0x5 1960 #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT 0xb 1961 #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT 0x10 1962 #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK 0x0000001FL 1963 #define RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK 0x000007E0L 1964 #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK 0x0000F800L 1965 #define RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK 0x003F0000L 1966 //RPB_EA_QUEUE_WR 1967 #define RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT 0x0 1968 #define RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT 0x5 1969 #define RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT 0x8 1970 #define RPB_EA_QUEUE_WR__UPDATE__SHIFT 0xb 1971 #define RPB_EA_QUEUE_WR__EA_NUMBER_MASK 0x0000001FL 1972 #define RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK 0x000000E0L 1973 #define RPB_EA_QUEUE_WR__READ_QUEUE_MASK 0x00000700L 1974 #define RPB_EA_QUEUE_WR__UPDATE_MASK 0x00000800L 1975 //RPB_ATS_CNTL 1976 #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 1977 #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 1978 #define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 1979 #define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 1980 #define RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT 0xf 1981 #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 1982 #define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 1983 #define RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT 0x19 1984 #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L 1985 #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L 1986 #define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL 1987 #define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L 1988 #define RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK 0x00078000L 1989 #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L 1990 #define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L 1991 #define RPB_ATS_CNTL__INVAL_COM_CMD_MASK 0x7E000000L 1992 //RPB_ATS_CNTL2 1993 #define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x0 1994 #define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0x6 1995 #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0xc 1996 #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0xf 1997 #define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x12 1998 #define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x0000003FL 1999 #define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x00000FC0L 2000 #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x00007000L 2001 #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00038000L 2002 #define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x000C0000L 2003 //RPB_SDPPORT_CNTL 2004 #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 2005 #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 2006 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 2007 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 2008 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 2009 #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 2010 #define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT 0xa 2011 #define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT 0xb 2012 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT 0xd 2013 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT 0xe 2014 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT 0xf 2015 #define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT 0x10 2016 #define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT 0x14 2017 #define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT 0x15 2018 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 2019 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 2020 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 2021 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 2022 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a 2023 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b 2024 #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L 2025 #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L 2026 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L 2027 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L 2028 #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L 2029 #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L 2030 #define RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK 0x00000400L 2031 #define RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK 0x00001800L 2032 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK 0x00002000L 2033 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK 0x00004000L 2034 #define RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK 0x00008000L 2035 #define RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK 0x000F0000L 2036 #define RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK 0x00100000L 2037 #define RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK 0x00200000L 2038 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L 2039 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L 2040 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L 2041 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L 2042 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L 2043 #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L 2044 2045 #endif 2046