1 /*
2 * Low-Level PCI Access for i386 machines.
3 *
4 * (c) 1999 Martin Mares <mj@ucw.cz>
5 */
6
7 #undef DEBUG
8
9 #ifdef DEBUG
10 #define DBG(x...) printk(x)
11 #else
12 #define DBG(x...)
13 #endif
14
15 #define PCI_PROBE_BIOS 0x0001
16 #define PCI_PROBE_CONF1 0x0002
17 #define PCI_PROBE_CONF2 0x0004
18 #define PCI_PROBE_MMCONF 0x0008
19 #define PCI_PROBE_MASK 0x000f
20 #define PCI_PROBE_NOEARLY 0x0010
21
22 #define PCI_NO_CHECKS 0x0400
23 #define PCI_USE_PIRQ_MASK 0x0800
24 #define PCI_ASSIGN_ROMS 0x1000
25 #define PCI_BIOS_IRQ_SCAN 0x2000
26 #define PCI_ASSIGN_ALL_BUSSES 0x4000
27 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000
28 #define PCI_USE__CRS 0x10000
29 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
30 #define PCI_HAS_IO_ECS 0x40000
31 #define PCI_NOASSIGN_ROMS 0x80000
32 #define PCI_ROOT_NO_CRS 0x100000
33 #define PCI_NOASSIGN_BARS 0x200000
34
35 extern unsigned int pci_probe;
36 extern unsigned long pirq_table_addr;
37
38 enum pci_bf_sort_state {
39 pci_bf_sort_default,
40 pci_force_nobf,
41 pci_force_bf,
42 pci_dmi_bf,
43 };
44
45 /* pci-i386.c */
46
47 void pcibios_resource_survey(void);
48 void pcibios_set_cache_line_size(void);
49
50 /* pci-pc.c */
51
52 extern int pcibios_last_bus;
53 extern struct pci_bus *pci_root_bus;
54 extern struct pci_ops pci_root_ops;
55
56 void pcibios_scan_specific_bus(int busn);
57
58 /* pci-irq.c */
59
60 struct irq_info {
61 u8 bus, devfn; /* Bus, device and function */
62 struct {
63 u8 link; /* IRQ line ID, chipset dependent,
64 0 = not routed */
65 u16 bitmap; /* Available IRQs */
66 } __attribute__((packed)) irq[4];
67 u8 slot; /* Slot number, 0=onboard */
68 u8 rfu;
69 } __attribute__((packed));
70
71 struct irq_routing_table {
72 u32 signature; /* PIRQ_SIGNATURE should be here */
73 u16 version; /* PIRQ_VERSION */
74 u16 size; /* Table size in bytes */
75 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
76 u16 exclusive_irqs; /* IRQs devoted exclusively to
77 PCI usage */
78 u16 rtr_vendor, rtr_device; /* Vendor and device ID of
79 interrupt router */
80 u32 miniport_data; /* Crap */
81 u8 rfu[11];
82 u8 checksum; /* Modulo 256 checksum must give 0 */
83 struct irq_info slots[0];
84 } __attribute__((packed));
85
86 extern unsigned int pcibios_irq_mask;
87
88 extern raw_spinlock_t pci_config_lock;
89
90 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
91 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
92
93 struct pci_raw_ops {
94 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
95 int reg, int len, u32 *val);
96 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
97 int reg, int len, u32 val);
98 };
99
100 extern const struct pci_raw_ops *raw_pci_ops;
101 extern const struct pci_raw_ops *raw_pci_ext_ops;
102
103 extern const struct pci_raw_ops pci_direct_conf1;
104 extern bool port_cf9_safe;
105
106 /* arch_initcall level */
107 extern int pci_direct_probe(void);
108 extern void pci_direct_init(int type);
109 extern void pci_pcbios_init(void);
110 extern void __init dmi_check_pciprobe(void);
111 extern void __init dmi_check_skip_isa_align(void);
112
113 /* some common used subsys_initcalls */
114 extern int __init pci_acpi_init(void);
115 extern void __init pcibios_irq_init(void);
116 extern int __init pcibios_init(void);
117 extern int pci_legacy_init(void);
118 extern void pcibios_fixup_irqs(void);
119
120 /* pci-mmconfig.c */
121
122 /* "PCI MMCONFIG %04x [bus %02x-%02x]" */
123 #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
124
125 struct pci_mmcfg_region {
126 struct list_head list;
127 struct resource res;
128 u64 address;
129 char __iomem *virt;
130 u16 segment;
131 u8 start_bus;
132 u8 end_bus;
133 char name[PCI_MMCFG_RESOURCE_NAME_LEN];
134 };
135
136 extern int __init pci_mmcfg_arch_init(void);
137 extern void __init pci_mmcfg_arch_free(void);
138 extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
139
140 extern struct list_head pci_mmcfg_list;
141
142 #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
143
144 /*
145 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
146 * on their northbrige except through the * %eax register. As such, you MUST
147 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
148 * accessor functions.
149 * In fact just use pci_config_*, nothing else please.
150 */
mmio_config_readb(void __iomem * pos)151 static inline unsigned char mmio_config_readb(void __iomem *pos)
152 {
153 u8 val;
154 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
155 return val;
156 }
157
mmio_config_readw(void __iomem * pos)158 static inline unsigned short mmio_config_readw(void __iomem *pos)
159 {
160 u16 val;
161 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
162 return val;
163 }
164
mmio_config_readl(void __iomem * pos)165 static inline unsigned int mmio_config_readl(void __iomem *pos)
166 {
167 u32 val;
168 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
169 return val;
170 }
171
mmio_config_writeb(void __iomem * pos,u8 val)172 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
173 {
174 asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
175 }
176
mmio_config_writew(void __iomem * pos,u16 val)177 static inline void mmio_config_writew(void __iomem *pos, u16 val)
178 {
179 asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
180 }
181
mmio_config_writel(void __iomem * pos,u32 val)182 static inline void mmio_config_writel(void __iomem *pos, u32 val)
183 {
184 asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
185 }
186
187 #ifdef CONFIG_PCI
188 # ifdef CONFIG_ACPI
189 # define x86_default_pci_init pci_acpi_init
190 # else
191 # define x86_default_pci_init pci_legacy_init
192 # endif
193 # define x86_default_pci_init_irq pcibios_irq_init
194 # define x86_default_pci_fixup_irqs pcibios_fixup_irqs
195 #else
196 # define x86_default_pci_init NULL
197 # define x86_default_pci_init_irq NULL
198 # define x86_default_pci_fixup_irqs NULL
199 #endif
200