1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _smuio_13_0_2_OFFSET_HEADER 25 #define _smuio_13_0_2_OFFSET_HEADER 26 27 28 29 // addressBlock: smuio_smuio_SmuSmuioDec 30 // base address: 0x5a000 31 #define regSMUSVI0_TEL_PLANE0 0x0004 32 #define regSMUSVI0_TEL_PLANE0_BASE_IDX 0 33 #define regSMUSVI0_PLANE0_CURRENTVID 0x0014 34 #define regSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0 35 #define regSMUIO_MCM_CONFIG 0x0024 36 #define regSMUIO_MCM_CONFIG_BASE_IDX 0 37 #define regCKSVII2C_IC_CON 0x0040 38 #define regCKSVII2C_IC_CON_BASE_IDX 0 39 #define regCKSVII2C_IC_TAR 0x0041 40 #define regCKSVII2C_IC_TAR_BASE_IDX 0 41 #define regCKSVII2C_IC_SAR 0x0042 42 #define regCKSVII2C_IC_SAR_BASE_IDX 0 43 #define regCKSVII2C_IC_HS_MADDR 0x0043 44 #define regCKSVII2C_IC_HS_MADDR_BASE_IDX 0 45 #define regCKSVII2C_IC_DATA_CMD 0x0044 46 #define regCKSVII2C_IC_DATA_CMD_BASE_IDX 0 47 #define regCKSVII2C_IC_SS_SCL_HCNT 0x0045 48 #define regCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX 0 49 #define regCKSVII2C_IC_SS_SCL_LCNT 0x0046 50 #define regCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX 0 51 #define regCKSVII2C_IC_FS_SCL_HCNT 0x0047 52 #define regCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX 0 53 #define regCKSVII2C_IC_FS_SCL_LCNT 0x0048 54 #define regCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX 0 55 #define regCKSVII2C_IC_HS_SCL_HCNT 0x0049 56 #define regCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX 0 57 #define regCKSVII2C_IC_HS_SCL_LCNT 0x004a 58 #define regCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX 0 59 #define regCKSVII2C_IC_INTR_STAT 0x004b 60 #define regCKSVII2C_IC_INTR_STAT_BASE_IDX 0 61 #define regCKSVII2C_IC_INTR_MASK 0x004c 62 #define regCKSVII2C_IC_INTR_MASK_BASE_IDX 0 63 #define regCKSVII2C_IC_RAW_INTR_STAT 0x004d 64 #define regCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX 0 65 #define regCKSVII2C_IC_RX_TL 0x004e 66 #define regCKSVII2C_IC_RX_TL_BASE_IDX 0 67 #define regCKSVII2C_IC_TX_TL 0x004f 68 #define regCKSVII2C_IC_TX_TL_BASE_IDX 0 69 #define regCKSVII2C_IC_CLR_INTR 0x0050 70 #define regCKSVII2C_IC_CLR_INTR_BASE_IDX 0 71 #define regCKSVII2C_IC_CLR_RX_UNDER 0x0051 72 #define regCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX 0 73 #define regCKSVII2C_IC_CLR_RX_OVER 0x0052 74 #define regCKSVII2C_IC_CLR_RX_OVER_BASE_IDX 0 75 #define regCKSVII2C_IC_CLR_TX_OVER 0x0053 76 #define regCKSVII2C_IC_CLR_TX_OVER_BASE_IDX 0 77 #define regCKSVII2C_IC_CLR_RD_REQ 0x0054 78 #define regCKSVII2C_IC_CLR_RD_REQ_BASE_IDX 0 79 #define regCKSVII2C_IC_CLR_TX_ABRT 0x0055 80 #define regCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX 0 81 #define regCKSVII2C_IC_CLR_RX_DONE 0x0056 82 #define regCKSVII2C_IC_CLR_RX_DONE_BASE_IDX 0 83 #define regCKSVII2C_IC_CLR_ACTIVITY 0x0057 84 #define regCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX 0 85 #define regCKSVII2C_IC_CLR_STOP_DET 0x0058 86 #define regCKSVII2C_IC_CLR_STOP_DET_BASE_IDX 0 87 #define regCKSVII2C_IC_CLR_START_DET 0x0059 88 #define regCKSVII2C_IC_CLR_START_DET_BASE_IDX 0 89 #define regCKSVII2C_IC_CLR_GEN_CALL 0x005a 90 #define regCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX 0 91 #define regCKSVII2C_IC_ENABLE 0x005b 92 #define regCKSVII2C_IC_ENABLE_BASE_IDX 0 93 #define regCKSVII2C_IC_STATUS 0x005c 94 #define regCKSVII2C_IC_STATUS_BASE_IDX 0 95 #define regCKSVII2C_IC_TXFLR 0x005d 96 #define regCKSVII2C_IC_TXFLR_BASE_IDX 0 97 #define regCKSVII2C_IC_RXFLR 0x005e 98 #define regCKSVII2C_IC_RXFLR_BASE_IDX 0 99 #define regCKSVII2C_IC_SDA_HOLD 0x005f 100 #define regCKSVII2C_IC_SDA_HOLD_BASE_IDX 0 101 #define regCKSVII2C_IC_TX_ABRT_SOURCE 0x0060 102 #define regCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX 0 103 #define regCKSVII2C_IC_SLV_DATA_NACK_ONLY 0x0061 104 #define regCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 105 #define regCKSVII2C_IC_DMA_CR 0x0062 106 #define regCKSVII2C_IC_DMA_CR_BASE_IDX 0 107 #define regCKSVII2C_IC_DMA_TDLR 0x0063 108 #define regCKSVII2C_IC_DMA_TDLR_BASE_IDX 0 109 #define regCKSVII2C_IC_DMA_RDLR 0x0064 110 #define regCKSVII2C_IC_DMA_RDLR_BASE_IDX 0 111 #define regCKSVII2C_IC_SDA_SETUP 0x0065 112 #define regCKSVII2C_IC_SDA_SETUP_BASE_IDX 0 113 #define regCKSVII2C_IC_ACK_GENERAL_CALL 0x0066 114 #define regCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX 0 115 #define regCKSVII2C_IC_ENABLE_STATUS 0x0067 116 #define regCKSVII2C_IC_ENABLE_STATUS_BASE_IDX 0 117 #define regCKSVII2C_IC_FS_SPKLEN 0x0068 118 #define regCKSVII2C_IC_FS_SPKLEN_BASE_IDX 0 119 #define regCKSVII2C_IC_HS_SPKLEN 0x0069 120 #define regCKSVII2C_IC_HS_SPKLEN_BASE_IDX 0 121 #define regCKSVII2C_IC_CLR_RESTART_DET 0x006a 122 #define regCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX 0 123 #define regCKSVII2C_IC_COMP_PARAM_1 0x006b 124 #define regCKSVII2C_IC_COMP_PARAM_1_BASE_IDX 0 125 #define regCKSVII2C_IC_COMP_VERSION 0x006c 126 #define regCKSVII2C_IC_COMP_VERSION_BASE_IDX 0 127 #define regCKSVII2C_IC_COMP_TYPE 0x006d 128 #define regCKSVII2C_IC_COMP_TYPE_BASE_IDX 0 129 #define regCKSVII2C1_IC_CON 0x0080 130 #define regCKSVII2C1_IC_CON_BASE_IDX 0 131 #define regCKSVII2C1_IC_TAR 0x0081 132 #define regCKSVII2C1_IC_TAR_BASE_IDX 0 133 #define regCKSVII2C1_IC_SAR 0x0082 134 #define regCKSVII2C1_IC_SAR_BASE_IDX 0 135 #define regCKSVII2C1_IC_HS_MADDR 0x0083 136 #define regCKSVII2C1_IC_HS_MADDR_BASE_IDX 0 137 #define regCKSVII2C1_IC_DATA_CMD 0x0084 138 #define regCKSVII2C1_IC_DATA_CMD_BASE_IDX 0 139 #define regCKSVII2C1_IC_SS_SCL_HCNT 0x0085 140 #define regCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX 0 141 #define regCKSVII2C1_IC_SS_SCL_LCNT 0x0086 142 #define regCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX 0 143 #define regCKSVII2C1_IC_FS_SCL_HCNT 0x0087 144 #define regCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX 0 145 #define regCKSVII2C1_IC_FS_SCL_LCNT 0x0088 146 #define regCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX 0 147 #define regCKSVII2C1_IC_HS_SCL_HCNT 0x0089 148 #define regCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX 0 149 #define regCKSVII2C1_IC_HS_SCL_LCNT 0x008a 150 #define regCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX 0 151 #define regCKSVII2C1_IC_INTR_STAT 0x008b 152 #define regCKSVII2C1_IC_INTR_STAT_BASE_IDX 0 153 #define regCKSVII2C1_IC_INTR_MASK 0x008c 154 #define regCKSVII2C1_IC_INTR_MASK_BASE_IDX 0 155 #define regCKSVII2C1_IC_RAW_INTR_STAT 0x008d 156 #define regCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX 0 157 #define regCKSVII2C1_IC_RX_TL 0x008e 158 #define regCKSVII2C1_IC_RX_TL_BASE_IDX 0 159 #define regCKSVII2C1_IC_TX_TL 0x008f 160 #define regCKSVII2C1_IC_TX_TL_BASE_IDX 0 161 #define regCKSVII2C1_IC_CLR_INTR 0x0090 162 #define regCKSVII2C1_IC_CLR_INTR_BASE_IDX 0 163 #define regCKSVII2C1_IC_CLR_RX_UNDER 0x0091 164 #define regCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX 0 165 #define regCKSVII2C1_IC_CLR_RX_OVER 0x0092 166 #define regCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX 0 167 #define regCKSVII2C1_IC_CLR_TX_OVER 0x0093 168 #define regCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX 0 169 #define regCKSVII2C1_IC_CLR_RD_REQ 0x0094 170 #define regCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX 0 171 #define regCKSVII2C1_IC_CLR_TX_ABRT 0x0095 172 #define regCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX 0 173 #define regCKSVII2C1_IC_CLR_RX_DONE 0x0096 174 #define regCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX 0 175 #define regCKSVII2C1_IC_CLR_ACTIVITY 0x0097 176 #define regCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX 0 177 #define regCKSVII2C1_IC_CLR_STOP_DET 0x0098 178 #define regCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX 0 179 #define regCKSVII2C1_IC_CLR_START_DET 0x0099 180 #define regCKSVII2C1_IC_CLR_START_DET_BASE_IDX 0 181 #define regCKSVII2C1_IC_CLR_GEN_CALL 0x009a 182 #define regCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX 0 183 #define regCKSVII2C1_IC_ENABLE 0x009b 184 #define regCKSVII2C1_IC_ENABLE_BASE_IDX 0 185 #define regCKSVII2C1_IC_STATUS 0x009c 186 #define regCKSVII2C1_IC_STATUS_BASE_IDX 0 187 #define regCKSVII2C1_IC_TXFLR 0x009d 188 #define regCKSVII2C1_IC_TXFLR_BASE_IDX 0 189 #define regCKSVII2C1_IC_RXFLR 0x009e 190 #define regCKSVII2C1_IC_RXFLR_BASE_IDX 0 191 #define regCKSVII2C1_IC_SDA_HOLD 0x009f 192 #define regCKSVII2C1_IC_SDA_HOLD_BASE_IDX 0 193 #define regCKSVII2C1_IC_TX_ABRT_SOURCE 0x00a0 194 #define regCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX 0 195 #define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY 0x00a1 196 #define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 197 #define regCKSVII2C1_IC_DMA_CR 0x00a2 198 #define regCKSVII2C1_IC_DMA_CR_BASE_IDX 0 199 #define regCKSVII2C1_IC_DMA_TDLR 0x00a3 200 #define regCKSVII2C1_IC_DMA_TDLR_BASE_IDX 0 201 #define regCKSVII2C1_IC_DMA_RDLR 0x00a4 202 #define regCKSVII2C1_IC_DMA_RDLR_BASE_IDX 0 203 #define regCKSVII2C1_IC_SDA_SETUP 0x00a5 204 #define regCKSVII2C1_IC_SDA_SETUP_BASE_IDX 0 205 #define regCKSVII2C1_IC_ACK_GENERAL_CALL 0x00a6 206 #define regCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX 0 207 #define regCKSVII2C1_IC_ENABLE_STATUS 0x00a7 208 #define regCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX 0 209 #define regCKSVII2C1_IC_FS_SPKLEN 0x00a8 210 #define regCKSVII2C1_IC_FS_SPKLEN_BASE_IDX 0 211 #define regCKSVII2C1_IC_HS_SPKLEN 0x00a9 212 #define regCKSVII2C1_IC_HS_SPKLEN_BASE_IDX 0 213 #define regCKSVII2C1_IC_CLR_RESTART_DET 0x00aa 214 #define regCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX 0 215 #define regCKSVII2C1_IC_COMP_PARAM_1 0x00ab 216 #define regCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX 0 217 #define regCKSVII2C1_IC_COMP_VERSION 0x00ac 218 #define regCKSVII2C1_IC_COMP_VERSION_BASE_IDX 0 219 #define regCKSVII2C1_IC_COMP_TYPE 0x00ad 220 #define regCKSVII2C1_IC_COMP_TYPE_BASE_IDX 0 221 #define regSMUIO_MP_RESET_INTR 0x00c1 222 #define regSMUIO_MP_RESET_INTR_BASE_IDX 0 223 #define regSMUIO_SOC_HALT 0x00c2 224 #define regSMUIO_SOC_HALT_BASE_IDX 0 225 #define regSMUIO_PWRMGT 0x00cd 226 #define regSMUIO_PWRMGT_BASE_IDX 0 227 #define regSMUIO_GFX_MISC_CNTL 0x00d1 228 #define regSMUIO_GFX_MISC_CNTL_BASE_IDX 0 229 #define regROM_CNTL 0x00e1 230 #define regROM_CNTL_BASE_IDX 0 231 #define regPAGE_MIRROR_CNTL 0x00e2 232 #define regPAGE_MIRROR_CNTL_BASE_IDX 0 233 #define regROM_STATUS 0x00e3 234 #define regROM_STATUS_BASE_IDX 0 235 #define regCGTT_ROM_CLK_CTRL0 0x00e4 236 #define regCGTT_ROM_CLK_CTRL0_BASE_IDX 0 237 #define regROM_INDEX 0x00e5 238 #define regROM_INDEX_BASE_IDX 0 239 #define regROM_DATA 0x00e6 240 #define regROM_DATA_BASE_IDX 0 241 #define regROM_START 0x00e7 242 #define regROM_START_BASE_IDX 0 243 #define regROM_SW_CNTL 0x00e9 244 #define regROM_SW_CNTL_BASE_IDX 0 245 #define regROM_SW_STATUS 0x00ea 246 #define regROM_SW_STATUS_BASE_IDX 0 247 #define regROM_SW_COMMAND 0x00eb 248 #define regROM_SW_COMMAND_BASE_IDX 0 249 #define regROM_SW_DATA_1 0x00ed 250 #define regROM_SW_DATA_1_BASE_IDX 0 251 #define regROM_SW_DATA_2 0x00ee 252 #define regROM_SW_DATA_2_BASE_IDX 0 253 #define regROM_SW_DATA_3 0x00ef 254 #define regROM_SW_DATA_3_BASE_IDX 0 255 #define regROM_SW_DATA_4 0x00f0 256 #define regROM_SW_DATA_4_BASE_IDX 0 257 #define regROM_SW_DATA_5 0x00f1 258 #define regROM_SW_DATA_5_BASE_IDX 0 259 #define regROM_SW_DATA_6 0x00f2 260 #define regROM_SW_DATA_6_BASE_IDX 0 261 #define regROM_SW_DATA_7 0x00f3 262 #define regROM_SW_DATA_7_BASE_IDX 0 263 #define regROM_SW_DATA_8 0x00f4 264 #define regROM_SW_DATA_8_BASE_IDX 0 265 #define regROM_SW_DATA_9 0x00f5 266 #define regROM_SW_DATA_9_BASE_IDX 0 267 #define regROM_SW_DATA_10 0x00f6 268 #define regROM_SW_DATA_10_BASE_IDX 0 269 #define regROM_SW_DATA_11 0x00f7 270 #define regROM_SW_DATA_11_BASE_IDX 0 271 #define regROM_SW_DATA_12 0x00f8 272 #define regROM_SW_DATA_12_BASE_IDX 0 273 #define regROM_SW_DATA_13 0x00f9 274 #define regROM_SW_DATA_13_BASE_IDX 0 275 #define regROM_SW_DATA_14 0x00fa 276 #define regROM_SW_DATA_14_BASE_IDX 0 277 #define regROM_SW_DATA_15 0x00fb 278 #define regROM_SW_DATA_15_BASE_IDX 0 279 #define regROM_SW_DATA_16 0x00fc 280 #define regROM_SW_DATA_16_BASE_IDX 0 281 #define regROM_SW_DATA_17 0x00fd 282 #define regROM_SW_DATA_17_BASE_IDX 0 283 #define regROM_SW_DATA_18 0x00fe 284 #define regROM_SW_DATA_18_BASE_IDX 0 285 #define regROM_SW_DATA_19 0x00ff 286 #define regROM_SW_DATA_19_BASE_IDX 0 287 #define regROM_SW_DATA_20 0x0100 288 #define regROM_SW_DATA_20_BASE_IDX 0 289 #define regROM_SW_DATA_21 0x0101 290 #define regROM_SW_DATA_21_BASE_IDX 0 291 #define regROM_SW_DATA_22 0x0102 292 #define regROM_SW_DATA_22_BASE_IDX 0 293 #define regROM_SW_DATA_23 0x0103 294 #define regROM_SW_DATA_23_BASE_IDX 0 295 #define regROM_SW_DATA_24 0x0104 296 #define regROM_SW_DATA_24_BASE_IDX 0 297 #define regROM_SW_DATA_25 0x0105 298 #define regROM_SW_DATA_25_BASE_IDX 0 299 #define regROM_SW_DATA_26 0x0106 300 #define regROM_SW_DATA_26_BASE_IDX 0 301 #define regROM_SW_DATA_27 0x0107 302 #define regROM_SW_DATA_27_BASE_IDX 0 303 #define regROM_SW_DATA_28 0x0108 304 #define regROM_SW_DATA_28_BASE_IDX 0 305 #define regROM_SW_DATA_29 0x0109 306 #define regROM_SW_DATA_29_BASE_IDX 0 307 #define regROM_SW_DATA_30 0x010a 308 #define regROM_SW_DATA_30_BASE_IDX 0 309 #define regROM_SW_DATA_31 0x010b 310 #define regROM_SW_DATA_31_BASE_IDX 0 311 #define regROM_SW_DATA_32 0x010c 312 #define regROM_SW_DATA_32_BASE_IDX 0 313 #define regROM_SW_DATA_33 0x010d 314 #define regROM_SW_DATA_33_BASE_IDX 0 315 #define regROM_SW_DATA_34 0x010e 316 #define regROM_SW_DATA_34_BASE_IDX 0 317 #define regROM_SW_DATA_35 0x010f 318 #define regROM_SW_DATA_35_BASE_IDX 0 319 #define regROM_SW_DATA_36 0x0110 320 #define regROM_SW_DATA_36_BASE_IDX 0 321 #define regROM_SW_DATA_37 0x0111 322 #define regROM_SW_DATA_37_BASE_IDX 0 323 #define regROM_SW_DATA_38 0x0112 324 #define regROM_SW_DATA_38_BASE_IDX 0 325 #define regROM_SW_DATA_39 0x0113 326 #define regROM_SW_DATA_39_BASE_IDX 0 327 #define regROM_SW_DATA_40 0x0114 328 #define regROM_SW_DATA_40_BASE_IDX 0 329 #define regROM_SW_DATA_41 0x0115 330 #define regROM_SW_DATA_41_BASE_IDX 0 331 #define regROM_SW_DATA_42 0x0116 332 #define regROM_SW_DATA_42_BASE_IDX 0 333 #define regROM_SW_DATA_43 0x0117 334 #define regROM_SW_DATA_43_BASE_IDX 0 335 #define regROM_SW_DATA_44 0x0118 336 #define regROM_SW_DATA_44_BASE_IDX 0 337 #define regROM_SW_DATA_45 0x0119 338 #define regROM_SW_DATA_45_BASE_IDX 0 339 #define regROM_SW_DATA_46 0x011a 340 #define regROM_SW_DATA_46_BASE_IDX 0 341 #define regROM_SW_DATA_47 0x011b 342 #define regROM_SW_DATA_47_BASE_IDX 0 343 #define regROM_SW_DATA_48 0x011c 344 #define regROM_SW_DATA_48_BASE_IDX 0 345 #define regROM_SW_DATA_49 0x011d 346 #define regROM_SW_DATA_49_BASE_IDX 0 347 #define regROM_SW_DATA_50 0x011e 348 #define regROM_SW_DATA_50_BASE_IDX 0 349 #define regROM_SW_DATA_51 0x011f 350 #define regROM_SW_DATA_51_BASE_IDX 0 351 #define regROM_SW_DATA_52 0x0120 352 #define regROM_SW_DATA_52_BASE_IDX 0 353 #define regROM_SW_DATA_53 0x0121 354 #define regROM_SW_DATA_53_BASE_IDX 0 355 #define regROM_SW_DATA_54 0x0122 356 #define regROM_SW_DATA_54_BASE_IDX 0 357 #define regROM_SW_DATA_55 0x0123 358 #define regROM_SW_DATA_55_BASE_IDX 0 359 #define regROM_SW_DATA_56 0x0124 360 #define regROM_SW_DATA_56_BASE_IDX 0 361 #define regROM_SW_DATA_57 0x0125 362 #define regROM_SW_DATA_57_BASE_IDX 0 363 #define regROM_SW_DATA_58 0x0126 364 #define regROM_SW_DATA_58_BASE_IDX 0 365 #define regROM_SW_DATA_59 0x0127 366 #define regROM_SW_DATA_59_BASE_IDX 0 367 #define regROM_SW_DATA_60 0x0128 368 #define regROM_SW_DATA_60_BASE_IDX 0 369 #define regROM_SW_DATA_61 0x0129 370 #define regROM_SW_DATA_61_BASE_IDX 0 371 #define regROM_SW_DATA_62 0x012a 372 #define regROM_SW_DATA_62_BASE_IDX 0 373 #define regROM_SW_DATA_63 0x012b 374 #define regROM_SW_DATA_63_BASE_IDX 0 375 #define regROM_SW_DATA_64 0x012c 376 #define regROM_SW_DATA_64_BASE_IDX 0 377 #define regSMU_GPIOPAD_SW_INT_STAT 0x0140 378 #define regSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 0 379 #define regSMU_GPIOPAD_MASK 0x0141 380 #define regSMU_GPIOPAD_MASK_BASE_IDX 0 381 #define regSMU_GPIOPAD_A 0x0142 382 #define regSMU_GPIOPAD_A_BASE_IDX 0 383 #define regSMU_GPIOPAD_TXIMPSEL 0x0143 384 #define regSMU_GPIOPAD_TXIMPSEL_BASE_IDX 0 385 #define regSMU_GPIOPAD_EN 0x0144 386 #define regSMU_GPIOPAD_EN_BASE_IDX 0 387 #define regSMU_GPIOPAD_Y 0x0145 388 #define regSMU_GPIOPAD_Y_BASE_IDX 0 389 #define regSMU_GPIOPAD_RXEN 0x0146 390 #define regSMU_GPIOPAD_RXEN_BASE_IDX 0 391 #define regSMU_GPIOPAD_RCVR_SEL0 0x0147 392 #define regSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 0 393 #define regSMU_GPIOPAD_RCVR_SEL1 0x0148 394 #define regSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 0 395 #define regSMU_GPIOPAD_PU_EN 0x0149 396 #define regSMU_GPIOPAD_PU_EN_BASE_IDX 0 397 #define regSMU_GPIOPAD_PD_EN 0x014a 398 #define regSMU_GPIOPAD_PD_EN_BASE_IDX 0 399 #define regSMU_GPIOPAD_PINSTRAPS 0x014b 400 #define regSMU_GPIOPAD_PINSTRAPS_BASE_IDX 0 401 #define regDFT_PINSTRAPS 0x014c 402 #define regDFT_PINSTRAPS_BASE_IDX 0 403 #define regSMU_GPIOPAD_INT_STAT_EN 0x014d 404 #define regSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 0 405 #define regSMU_GPIOPAD_INT_STAT 0x014e 406 #define regSMU_GPIOPAD_INT_STAT_BASE_IDX 0 407 #define regSMU_GPIOPAD_INT_STAT_AK 0x014f 408 #define regSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 0 409 #define regSMU_GPIOPAD_INT_EN 0x0150 410 #define regSMU_GPIOPAD_INT_EN_BASE_IDX 0 411 #define regSMU_GPIOPAD_INT_TYPE 0x0151 412 #define regSMU_GPIOPAD_INT_TYPE_BASE_IDX 0 413 #define regSMU_GPIOPAD_INT_POLARITY 0x0152 414 #define regSMU_GPIOPAD_INT_POLARITY_BASE_IDX 0 415 #define regROM_CC_BIF_PINSTRAP 0x0153 416 #define regROM_CC_BIF_PINSTRAP_BASE_IDX 0 417 #define regIO_SMUIO_PINSTRAP 0x0154 418 #define regIO_SMUIO_PINSTRAP_BASE_IDX 0 419 #define regSMUIO_PCC_CONTROL 0x0155 420 #define regSMUIO_PCC_CONTROL_BASE_IDX 0 421 #define regSMUIO_PCC_GPIO_SELECT 0x0156 422 #define regSMUIO_PCC_GPIO_SELECT_BASE_IDX 0 423 #define regSMUIO_GPIO_INT0_SELECT 0x0157 424 #define regSMUIO_GPIO_INT0_SELECT_BASE_IDX 0 425 #define regSMUIO_GPIO_INT1_SELECT 0x0158 426 #define regSMUIO_GPIO_INT1_SELECT_BASE_IDX 0 427 #define regSMUIO_GPIO_INT2_SELECT 0x0159 428 #define regSMUIO_GPIO_INT2_SELECT_BASE_IDX 0 429 #define regSMUIO_GPIO_INT3_SELECT 0x015a 430 #define regSMUIO_GPIO_INT3_SELECT_BASE_IDX 0 431 #define regSMU_GPIOPAD_MP_INT0_STAT 0x015b 432 #define regSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 0 433 #define regSMU_GPIOPAD_MP_INT1_STAT 0x015c 434 #define regSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 0 435 #define regSMU_GPIOPAD_MP_INT2_STAT 0x015d 436 #define regSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 0 437 #define regSMU_GPIOPAD_MP_INT3_STAT 0x015e 438 #define regSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 0 439 #define regSMIO_INDEX 0x015f 440 #define regSMIO_INDEX_BASE_IDX 0 441 #define regS0_VID_SMIO_CNTL 0x0160 442 #define regS0_VID_SMIO_CNTL_BASE_IDX 0 443 #define regS1_VID_SMIO_CNTL 0x0161 444 #define regS1_VID_SMIO_CNTL_BASE_IDX 0 445 #define regOPEN_DRAIN_SELECT 0x0162 446 #define regOPEN_DRAIN_SELECT_BASE_IDX 0 447 #define regSMIO_ENABLE 0x0163 448 #define regSMIO_ENABLE_BASE_IDX 0 449 #define regSMU_GPIOPAD_S0 0x0164 450 #define regSMU_GPIOPAD_S0_BASE_IDX 0 451 #define regSMU_GPIOPAD_S1 0x0165 452 #define regSMU_GPIOPAD_S1_BASE_IDX 0 453 #define regSMU_GPIOPAD_SCL_EN 0x0166 454 #define regSMU_GPIOPAD_SCL_EN_BASE_IDX 0 455 #define regSMU_GPIOPAD_SDA_EN 0x0167 456 #define regSMU_GPIOPAD_SDA_EN_BASE_IDX 0 457 #define regSMU_GPIOPAD_SCHMEN 0x0168 458 #define regSMU_GPIOPAD_SCHMEN_BASE_IDX 0 459 460 461 // addressBlock: smuio_smuio_pwr_SmuSmuioDec 462 // base address: 0x5a800 463 #define regIP_DISCOVERY_VERSION 0x0000 464 #define regIP_DISCOVERY_VERSION_BASE_IDX 1 465 #define regSOC_GAP_PWROK 0x00fc 466 #define regSOC_GAP_PWROK_BASE_IDX 1 467 #define regGFX_GAP_PWROK 0x00fd 468 #define regGFX_GAP_PWROK_BASE_IDX 1 469 #define regPWROK_REFCLK_GAP_CYCLES 0x00fe 470 #define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1 471 #define regGOLDEN_TSC_INCREMENT_UPPER 0x0104 472 #define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1 473 #define regGOLDEN_TSC_INCREMENT_LOWER 0x0105 474 #define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1 475 #define regGOLDEN_TSC_COUNT_UPPER 0x0106 476 #define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1 477 #define regGOLDEN_TSC_COUNT_LOWER 0x0107 478 #define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1 479 #define regSOC_GOLDEN_TSC_SHADOW_UPPER 0x0108 480 #define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 481 #define regSOC_GOLDEN_TSC_SHADOW_LOWER 0x0109 482 #define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 483 #define regGFX_GOLDEN_TSC_SHADOW_UPPER 0x010a 484 #define regGFX_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 485 #define regGFX_GOLDEN_TSC_SHADOW_LOWER 0x010b 486 #define regGFX_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 487 #define regSCRATCH_REGISTER0 0x0114 488 #define regSCRATCH_REGISTER0_BASE_IDX 1 489 #define regSCRATCH_REGISTER1 0x0115 490 #define regSCRATCH_REGISTER1_BASE_IDX 1 491 #define regSCRATCH_REGISTER2 0x0116 492 #define regSCRATCH_REGISTER2_BASE_IDX 1 493 #define regSCRATCH_REGISTER3 0x0117 494 #define regSCRATCH_REGISTER3_BASE_IDX 1 495 #define regSCRATCH_REGISTER4 0x0118 496 #define regSCRATCH_REGISTER4_BASE_IDX 1 497 #define regSCRATCH_REGISTER5 0x0119 498 #define regSCRATCH_REGISTER5_BASE_IDX 1 499 #define regSCRATCH_REGISTER6 0x011a 500 #define regSCRATCH_REGISTER6_BASE_IDX 1 501 #define regSCRATCH_REGISTER7 0x011b 502 #define regSCRATCH_REGISTER7_BASE_IDX 1 503 #define regPWR_DISP_TIMER_CONTROL 0x0134 504 #define regPWR_DISP_TIMER_CONTROL_BASE_IDX 1 505 #define regPWR_DISP_TIMER_DEBUG 0x0135 506 #define regPWR_DISP_TIMER_DEBUG_BASE_IDX 1 507 #define regPWR_DISP_TIMER2_CONTROL 0x0136 508 #define regPWR_DISP_TIMER2_CONTROL_BASE_IDX 1 509 #define regPWR_DISP_TIMER2_DEBUG 0x0137 510 #define regPWR_DISP_TIMER2_DEBUG_BASE_IDX 1 511 #define regPWR_DISP_TIMER_GLOBAL_CONTROL 0x0138 512 #define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1 513 #define regPWR_IH_CONTROL 0x0139 514 #define regPWR_IH_CONTROL_BASE_IDX 1 515 516 #endif 517