1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86_64/entry.S 4 * 5 * Copyright (C) 1991, 1992 Linus Torvalds 6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs 7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 8 * 9 * entry.S contains the system-call and fault low-level handling routines. 10 * 11 * Some of this is documented in Documentation/x86/entry_64.rst 12 * 13 * A note on terminology: 14 * - iret frame: Architecture defined interrupt frame from SS to RIP 15 * at the top of the kernel process stack. 16 * 17 * Some macro usage: 18 * - SYM_FUNC_START/END:Define functions in the symbol table. 19 * - idtentry: Define exception entry points. 20 */ 21#include <linux/linkage.h> 22#include <asm/segment.h> 23#include <asm/cache.h> 24#include <asm/errno.h> 25#include <asm/asm-offsets.h> 26#include <asm/msr.h> 27#include <asm/unistd.h> 28#include <asm/thread_info.h> 29#include <asm/hw_irq.h> 30#include <asm/page_types.h> 31#include <asm/irqflags.h> 32#include <asm/paravirt.h> 33#include <asm/percpu.h> 34#include <asm/asm.h> 35#include <asm/smap.h> 36#include <asm/pgtable_types.h> 37#include <asm/export.h> 38#include <asm/frame.h> 39#include <asm/trapnr.h> 40#include <asm/nospec-branch.h> 41#include <asm/fsgsbase.h> 42#include <linux/err.h> 43 44#include "calling.h" 45 46.code64 47.section .entry.text, "ax" 48 49/* 50 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. 51 * 52 * This is the only entry point used for 64-bit system calls. The 53 * hardware interface is reasonably well designed and the register to 54 * argument mapping Linux uses fits well with the registers that are 55 * available when SYSCALL is used. 56 * 57 * SYSCALL instructions can be found inlined in libc implementations as 58 * well as some other programs and libraries. There are also a handful 59 * of SYSCALL instructions in the vDSO used, for example, as a 60 * clock_gettimeofday fallback. 61 * 62 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, 63 * then loads new ss, cs, and rip from previously programmed MSRs. 64 * rflags gets masked by a value from another MSR (so CLD and CLAC 65 * are not needed). SYSCALL does not save anything on the stack 66 * and does not change rsp. 67 * 68 * Registers on entry: 69 * rax system call number 70 * rcx return address 71 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) 72 * rdi arg0 73 * rsi arg1 74 * rdx arg2 75 * r10 arg3 (needs to be moved to rcx to conform to C ABI) 76 * r8 arg4 77 * r9 arg5 78 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) 79 * 80 * Only called from user space. 81 * 82 * When user can change pt_regs->foo always force IRET. That is because 83 * it deals with uncanonical addresses better. SYSRET has trouble 84 * with them due to bugs in both AMD and Intel CPUs. 85 */ 86 87SYM_CODE_START(entry_SYSCALL_64) 88 UNWIND_HINT_ENTRY 89 ENDBR 90 91 swapgs 92 /* tss.sp2 is scratch space. */ 93 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2) 94 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp 95 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 96 97SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL) 98 ANNOTATE_NOENDBR 99 100 /* Construct struct pt_regs on stack */ 101 pushq $__USER_DS /* pt_regs->ss */ 102 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */ 103 pushq %r11 /* pt_regs->flags */ 104 pushq $__USER_CS /* pt_regs->cs */ 105 pushq %rcx /* pt_regs->ip */ 106SYM_INNER_LABEL(entry_SYSCALL_64_after_hwframe, SYM_L_GLOBAL) 107 pushq %rax /* pt_regs->orig_ax */ 108 109 PUSH_AND_CLEAR_REGS rax=$-ENOSYS 110 111 /* IRQs are off. */ 112 movq %rsp, %rdi 113 /* Sign extend the lower 32bit as syscall numbers are treated as int */ 114 movslq %eax, %rsi 115 116 /* clobbers %rax, make sure it is after saving the syscall nr */ 117 IBRS_ENTER 118 UNTRAIN_RET 119 120 call do_syscall_64 /* returns with IRQs disabled */ 121 122 /* 123 * Try to use SYSRET instead of IRET if we're returning to 124 * a completely clean 64-bit userspace context. If we're not, 125 * go to the slow exit path. 126 * In the Xen PV case we must use iret anyway. 127 */ 128 129 ALTERNATIVE "", "jmp swapgs_restore_regs_and_return_to_usermode", \ 130 X86_FEATURE_XENPV 131 132 movq RCX(%rsp), %rcx 133 movq RIP(%rsp), %r11 134 135 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ 136 jne swapgs_restore_regs_and_return_to_usermode 137 138 /* 139 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP 140 * in kernel space. This essentially lets the user take over 141 * the kernel, since userspace controls RSP. 142 * 143 * If width of "canonical tail" ever becomes variable, this will need 144 * to be updated to remain correct on both old and new CPUs. 145 * 146 * Change top bits to match most significant bit (47th or 56th bit 147 * depending on paging mode) in the address. 148 */ 149#ifdef CONFIG_X86_5LEVEL 150 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ 151 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 152#else 153 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 154 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx 155#endif 156 157 /* If this changed %rcx, it was not canonical */ 158 cmpq %rcx, %r11 159 jne swapgs_restore_regs_and_return_to_usermode 160 161 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ 162 jne swapgs_restore_regs_and_return_to_usermode 163 164 movq R11(%rsp), %r11 165 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ 166 jne swapgs_restore_regs_and_return_to_usermode 167 168 /* 169 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot 170 * restore RF properly. If the slowpath sets it for whatever reason, we 171 * need to restore it correctly. 172 * 173 * SYSRET can restore TF, but unlike IRET, restoring TF results in a 174 * trap from userspace immediately after SYSRET. This would cause an 175 * infinite loop whenever #DB happens with register state that satisfies 176 * the opportunistic SYSRET conditions. For example, single-stepping 177 * this user code: 178 * 179 * movq $stuck_here, %rcx 180 * pushfq 181 * popq %r11 182 * stuck_here: 183 * 184 * would never get past 'stuck_here'. 185 */ 186 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 187 jnz swapgs_restore_regs_and_return_to_usermode 188 189 /* nothing to check for RSP */ 190 191 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ 192 jne swapgs_restore_regs_and_return_to_usermode 193 194 /* 195 * We win! This label is here just for ease of understanding 196 * perf profiles. Nothing jumps here. 197 */ 198syscall_return_via_sysret: 199 IBRS_EXIT 200 POP_REGS pop_rdi=0 201 202 /* 203 * Now all regs are restored except RSP and RDI. 204 * Save old stack pointer and switch to trampoline stack. 205 */ 206 movq %rsp, %rdi 207 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 208 UNWIND_HINT_EMPTY 209 210 pushq RSP-RDI(%rdi) /* RSP */ 211 pushq (%rdi) /* RDI */ 212 213 /* 214 * We are on the trampoline stack. All regs except RDI are live. 215 * We can do future final exit work right here. 216 */ 217 STACKLEAK_ERASE_NOCLOBBER 218 219 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 220 221 popq %rdi 222 popq %rsp 223SYM_INNER_LABEL(entry_SYSRETQ_unsafe_stack, SYM_L_GLOBAL) 224 ANNOTATE_NOENDBR 225 swapgs 226 sysretq 227SYM_INNER_LABEL(entry_SYSRETQ_end, SYM_L_GLOBAL) 228 ANNOTATE_NOENDBR 229 int3 230SYM_CODE_END(entry_SYSCALL_64) 231 232/* 233 * %rdi: prev task 234 * %rsi: next task 235 */ 236.pushsection .text, "ax" 237SYM_FUNC_START(__switch_to_asm) 238 /* 239 * Save callee-saved registers 240 * This must match the order in inactive_task_frame 241 */ 242 pushq %rbp 243 pushq %rbx 244 pushq %r12 245 pushq %r13 246 pushq %r14 247 pushq %r15 248 249 /* switch stack */ 250 movq %rsp, TASK_threadsp(%rdi) 251 movq TASK_threadsp(%rsi), %rsp 252 253#ifdef CONFIG_STACKPROTECTOR 254 movq TASK_stack_canary(%rsi), %rbx 255 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + stack_canary_offset 256#endif 257 258 /* 259 * When switching from a shallower to a deeper call stack 260 * the RSB may either underflow or use entries populated 261 * with userspace addresses. On CPUs where those concerns 262 * exist, overwrite the RSB with entries which capture 263 * speculative execution to prevent attack. 264 */ 265 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW 266 267 /* restore callee-saved registers */ 268 popq %r15 269 popq %r14 270 popq %r13 271 popq %r12 272 popq %rbx 273 popq %rbp 274 275 jmp __switch_to 276SYM_FUNC_END(__switch_to_asm) 277.popsection 278 279/* 280 * A newly forked process directly context switches into this address. 281 * 282 * rax: prev task we switched from 283 * rbx: kernel thread func (NULL for user thread) 284 * r12: kernel thread arg 285 */ 286.pushsection .text, "ax" 287SYM_CODE_START(ret_from_fork) 288 UNWIND_HINT_EMPTY 289 ANNOTATE_NOENDBR // copy_thread 290 movq %rax, %rdi 291 call schedule_tail /* rdi: 'prev' task parameter */ 292 293 testq %rbx, %rbx /* from kernel_thread? */ 294 jnz 1f /* kernel threads are uncommon */ 295 2962: 297 UNWIND_HINT_REGS 298 movq %rsp, %rdi 299 call syscall_exit_to_user_mode /* returns with IRQs disabled */ 300 jmp swapgs_restore_regs_and_return_to_usermode 301 3021: 303 /* kernel thread */ 304 UNWIND_HINT_EMPTY 305 movq %r12, %rdi 306 CALL_NOSPEC rbx 307 /* 308 * A kernel thread is allowed to return here after successfully 309 * calling kernel_execve(). Exit to userspace to complete the execve() 310 * syscall. 311 */ 312 movq $0, RAX(%rsp) 313 jmp 2b 314SYM_CODE_END(ret_from_fork) 315.popsection 316 317.macro DEBUG_ENTRY_ASSERT_IRQS_OFF 318#ifdef CONFIG_DEBUG_ENTRY 319 pushq %rax 320 SAVE_FLAGS 321 testl $X86_EFLAGS_IF, %eax 322 jz .Lokay_\@ 323 ud2 324.Lokay_\@: 325 popq %rax 326#endif 327.endm 328 329SYM_CODE_START_LOCAL(xen_error_entry) 330 UNWIND_HINT_FUNC 331 PUSH_AND_CLEAR_REGS save_ret=1 332 ENCODE_FRAME_POINTER 8 333 UNTRAIN_RET 334 RET 335SYM_CODE_END(xen_error_entry) 336 337/** 338 * idtentry_body - Macro to emit code calling the C function 339 * @cfunc: C function to be called 340 * @has_error_code: Hardware pushed error code on stack 341 */ 342.macro idtentry_body cfunc has_error_code:req 343 344 /* 345 * Call error_entry() and switch to the task stack if from userspace. 346 * 347 * When in XENPV, it is already in the task stack, and it can't fault 348 * for native_iret() nor native_load_gs_index() since XENPV uses its 349 * own pvops for IRET and load_gs_index(). And it doesn't need to 350 * switch the CR3. So it can skip invoking error_entry(). 351 */ 352 ALTERNATIVE "call error_entry; movq %rax, %rsp", \ 353 "call xen_error_entry", X86_FEATURE_XENPV 354 355 ENCODE_FRAME_POINTER 356 UNWIND_HINT_REGS 357 358 movq %rsp, %rdi /* pt_regs pointer into 1st argument*/ 359 360 .if \has_error_code == 1 361 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 362 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 363 .endif 364 365 call \cfunc 366 367 /* For some configurations \cfunc ends up being a noreturn. */ 368 REACHABLE 369 370 jmp error_return 371.endm 372 373/** 374 * idtentry - Macro to generate entry stubs for simple IDT entries 375 * @vector: Vector number 376 * @asmsym: ASM symbol for the entry point 377 * @cfunc: C function to be called 378 * @has_error_code: Hardware pushed error code on stack 379 * 380 * The macro emits code to set up the kernel context for straight forward 381 * and simple IDT entries. No IST stack, no paranoid entry checks. 382 */ 383.macro idtentry vector asmsym cfunc has_error_code:req 384SYM_CODE_START(\asmsym) 385 UNWIND_HINT_IRET_REGS offset=\has_error_code*8 386 ENDBR 387 ASM_CLAC 388 cld 389 390 .if \has_error_code == 0 391 pushq $-1 /* ORIG_RAX: no syscall to restart */ 392 .endif 393 394 .if \vector == X86_TRAP_BP 395 /* 396 * If coming from kernel space, create a 6-word gap to allow the 397 * int3 handler to emulate a call instruction. 398 */ 399 testb $3, CS-ORIG_RAX(%rsp) 400 jnz .Lfrom_usermode_no_gap_\@ 401 .rept 6 402 pushq 5*8(%rsp) 403 .endr 404 UNWIND_HINT_IRET_REGS offset=8 405.Lfrom_usermode_no_gap_\@: 406 .endif 407 408 idtentry_body \cfunc \has_error_code 409 410_ASM_NOKPROBE(\asmsym) 411SYM_CODE_END(\asmsym) 412.endm 413 414/* 415 * Interrupt entry/exit. 416 * 417 + The interrupt stubs push (vector) onto the stack, which is the error_code 418 * position of idtentry exceptions, and jump to one of the two idtentry points 419 * (common/spurious). 420 * 421 * common_interrupt is a hotpath, align it to a cache line 422 */ 423.macro idtentry_irq vector cfunc 424 .p2align CONFIG_X86_L1_CACHE_SHIFT 425 idtentry \vector asm_\cfunc \cfunc has_error_code=1 426.endm 427 428/* 429 * System vectors which invoke their handlers directly and are not 430 * going through the regular common device interrupt handling code. 431 */ 432.macro idtentry_sysvec vector cfunc 433 idtentry \vector asm_\cfunc \cfunc has_error_code=0 434.endm 435 436/** 437 * idtentry_mce_db - Macro to generate entry stubs for #MC and #DB 438 * @vector: Vector number 439 * @asmsym: ASM symbol for the entry point 440 * @cfunc: C function to be called 441 * 442 * The macro emits code to set up the kernel context for #MC and #DB 443 * 444 * If the entry comes from user space it uses the normal entry path 445 * including the return to user space work and preemption checks on 446 * exit. 447 * 448 * If hits in kernel mode then it needs to go through the paranoid 449 * entry as the exception can hit any random state. No preemption 450 * check on exit to keep the paranoid path simple. 451 */ 452.macro idtentry_mce_db vector asmsym cfunc 453SYM_CODE_START(\asmsym) 454 UNWIND_HINT_IRET_REGS 455 ENDBR 456 ASM_CLAC 457 cld 458 459 pushq $-1 /* ORIG_RAX: no syscall to restart */ 460 461 /* 462 * If the entry is from userspace, switch stacks and treat it as 463 * a normal entry. 464 */ 465 testb $3, CS-ORIG_RAX(%rsp) 466 jnz .Lfrom_usermode_switch_stack_\@ 467 468 /* paranoid_entry returns GS information for paranoid_exit in EBX. */ 469 call paranoid_entry 470 471 UNWIND_HINT_REGS 472 473 movq %rsp, %rdi /* pt_regs pointer */ 474 475 call \cfunc 476 477 jmp paranoid_exit 478 479 /* Switch to the regular task stack and use the noist entry point */ 480.Lfrom_usermode_switch_stack_\@: 481 idtentry_body noist_\cfunc, has_error_code=0 482 483_ASM_NOKPROBE(\asmsym) 484SYM_CODE_END(\asmsym) 485.endm 486 487#ifdef CONFIG_AMD_MEM_ENCRYPT 488/** 489 * idtentry_vc - Macro to generate entry stub for #VC 490 * @vector: Vector number 491 * @asmsym: ASM symbol for the entry point 492 * @cfunc: C function to be called 493 * 494 * The macro emits code to set up the kernel context for #VC. The #VC handler 495 * runs on an IST stack and needs to be able to cause nested #VC exceptions. 496 * 497 * To make this work the #VC entry code tries its best to pretend it doesn't use 498 * an IST stack by switching to the task stack if coming from user-space (which 499 * includes early SYSCALL entry path) or back to the stack in the IRET frame if 500 * entered from kernel-mode. 501 * 502 * If entered from kernel-mode the return stack is validated first, and if it is 503 * not safe to use (e.g. because it points to the entry stack) the #VC handler 504 * will switch to a fall-back stack (VC2) and call a special handler function. 505 * 506 * The macro is only used for one vector, but it is planned to be extended in 507 * the future for the #HV exception. 508 */ 509.macro idtentry_vc vector asmsym cfunc 510SYM_CODE_START(\asmsym) 511 UNWIND_HINT_IRET_REGS 512 ENDBR 513 ASM_CLAC 514 cld 515 516 /* 517 * If the entry is from userspace, switch stacks and treat it as 518 * a normal entry. 519 */ 520 testb $3, CS-ORIG_RAX(%rsp) 521 jnz .Lfrom_usermode_switch_stack_\@ 522 523 /* 524 * paranoid_entry returns SWAPGS flag for paranoid_exit in EBX. 525 * EBX == 0 -> SWAPGS, EBX == 1 -> no SWAPGS 526 */ 527 call paranoid_entry 528 529 UNWIND_HINT_REGS 530 531 /* 532 * Switch off the IST stack to make it free for nested exceptions. The 533 * vc_switch_off_ist() function will switch back to the interrupted 534 * stack if it is safe to do so. If not it switches to the VC fall-back 535 * stack. 536 */ 537 movq %rsp, %rdi /* pt_regs pointer */ 538 call vc_switch_off_ist 539 movq %rax, %rsp /* Switch to new stack */ 540 541 ENCODE_FRAME_POINTER 542 UNWIND_HINT_REGS 543 544 /* Update pt_regs */ 545 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 546 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 547 548 movq %rsp, %rdi /* pt_regs pointer */ 549 550 call kernel_\cfunc 551 552 /* 553 * No need to switch back to the IST stack. The current stack is either 554 * identical to the stack in the IRET frame or the VC fall-back stack, 555 * so it is definitely mapped even with PTI enabled. 556 */ 557 jmp paranoid_exit 558 559 /* Switch to the regular task stack */ 560.Lfrom_usermode_switch_stack_\@: 561 idtentry_body user_\cfunc, has_error_code=1 562 563_ASM_NOKPROBE(\asmsym) 564SYM_CODE_END(\asmsym) 565.endm 566#endif 567 568/* 569 * Double fault entry. Straight paranoid. No checks from which context 570 * this comes because for the espfix induced #DF this would do the wrong 571 * thing. 572 */ 573.macro idtentry_df vector asmsym cfunc 574SYM_CODE_START(\asmsym) 575 UNWIND_HINT_IRET_REGS offset=8 576 ENDBR 577 ASM_CLAC 578 cld 579 580 /* paranoid_entry returns GS information for paranoid_exit in EBX. */ 581 call paranoid_entry 582 UNWIND_HINT_REGS 583 584 movq %rsp, %rdi /* pt_regs pointer into first argument */ 585 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/ 586 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ 587 call \cfunc 588 589 /* For some configurations \cfunc ends up being a noreturn. */ 590 REACHABLE 591 592 jmp paranoid_exit 593 594_ASM_NOKPROBE(\asmsym) 595SYM_CODE_END(\asmsym) 596.endm 597 598/* 599 * Include the defines which emit the idt entries which are shared 600 * shared between 32 and 64 bit and emit the __irqentry_text_* markers 601 * so the stacktrace boundary checks work. 602 */ 603 .align 16 604 .globl __irqentry_text_start 605__irqentry_text_start: 606 607#include <asm/idtentry.h> 608 609 .align 16 610 .globl __irqentry_text_end 611__irqentry_text_end: 612 ANNOTATE_NOENDBR 613 614SYM_CODE_START_LOCAL(common_interrupt_return) 615SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL) 616 IBRS_EXIT 617#ifdef CONFIG_DEBUG_ENTRY 618 /* Assert that pt_regs indicates user mode. */ 619 testb $3, CS(%rsp) 620 jnz 1f 621 ud2 6221: 623#endif 624#ifdef CONFIG_XEN_PV 625 ALTERNATIVE "", "jmp xenpv_restore_regs_and_return_to_usermode", X86_FEATURE_XENPV 626#endif 627 628 POP_REGS pop_rdi=0 629 630 /* 631 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. 632 * Save old stack pointer and switch to trampoline stack. 633 */ 634 movq %rsp, %rdi 635 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp 636 UNWIND_HINT_EMPTY 637 638 /* Copy the IRET frame to the trampoline stack. */ 639 pushq 6*8(%rdi) /* SS */ 640 pushq 5*8(%rdi) /* RSP */ 641 pushq 4*8(%rdi) /* EFLAGS */ 642 pushq 3*8(%rdi) /* CS */ 643 pushq 2*8(%rdi) /* RIP */ 644 645 /* Push user RDI on the trampoline stack. */ 646 pushq (%rdi) 647 648 /* 649 * We are on the trampoline stack. All regs except RDI are live. 650 * We can do future final exit work right here. 651 */ 652 STACKLEAK_ERASE_NOCLOBBER 653 654 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 655 656 /* Restore RDI. */ 657 popq %rdi 658 swapgs 659 jmp .Lnative_iret 660 661 662SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL) 663#ifdef CONFIG_DEBUG_ENTRY 664 /* Assert that pt_regs indicates kernel mode. */ 665 testb $3, CS(%rsp) 666 jz 1f 667 ud2 6681: 669#endif 670 POP_REGS 671 addq $8, %rsp /* skip regs->orig_ax */ 672 /* 673 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization 674 * when returning from IPI handler. 675 */ 676#ifdef CONFIG_XEN_PV 677SYM_INNER_LABEL(early_xen_iret_patch, SYM_L_GLOBAL) 678 ANNOTATE_NOENDBR 679 .byte 0xe9 680 .long .Lnative_iret - (. + 4) 681#endif 682 683.Lnative_iret: 684 UNWIND_HINT_IRET_REGS 685 /* 686 * Are we returning to a stack segment from the LDT? Note: in 687 * 64-bit mode SS:RSP on the exception stack is always valid. 688 */ 689#ifdef CONFIG_X86_ESPFIX64 690 testb $4, (SS-RIP)(%rsp) 691 jnz native_irq_return_ldt 692#endif 693 694SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL) 695 ANNOTATE_NOENDBR // exc_double_fault 696 /* 697 * This may fault. Non-paranoid faults on return to userspace are 698 * handled by fixup_bad_iret. These include #SS, #GP, and #NP. 699 * Double-faults due to espfix64 are handled in exc_double_fault. 700 * Other faults here are fatal. 701 */ 702 iretq 703 704#ifdef CONFIG_X86_ESPFIX64 705native_irq_return_ldt: 706 /* 707 * We are running with user GSBASE. All GPRs contain their user 708 * values. We have a percpu ESPFIX stack that is eight slots 709 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom 710 * of the ESPFIX stack. 711 * 712 * We clobber RAX and RDI in this code. We stash RDI on the 713 * normal stack and RAX on the ESPFIX stack. 714 * 715 * The ESPFIX stack layout we set up looks like this: 716 * 717 * --- top of ESPFIX stack --- 718 * SS 719 * RSP 720 * RFLAGS 721 * CS 722 * RIP <-- RSP points here when we're done 723 * RAX <-- espfix_waddr points here 724 * --- bottom of ESPFIX stack --- 725 */ 726 727 pushq %rdi /* Stash user RDI */ 728 swapgs /* to kernel GS */ 729 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ 730 731 movq PER_CPU_VAR(espfix_waddr), %rdi 732 movq %rax, (0*8)(%rdi) /* user RAX */ 733 movq (1*8)(%rsp), %rax /* user RIP */ 734 movq %rax, (1*8)(%rdi) 735 movq (2*8)(%rsp), %rax /* user CS */ 736 movq %rax, (2*8)(%rdi) 737 movq (3*8)(%rsp), %rax /* user RFLAGS */ 738 movq %rax, (3*8)(%rdi) 739 movq (5*8)(%rsp), %rax /* user SS */ 740 movq %rax, (5*8)(%rdi) 741 movq (4*8)(%rsp), %rax /* user RSP */ 742 movq %rax, (4*8)(%rdi) 743 /* Now RAX == RSP. */ 744 745 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ 746 747 /* 748 * espfix_stack[31:16] == 0. The page tables are set up such that 749 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of 750 * espfix_waddr for any X. That is, there are 65536 RO aliases of 751 * the same page. Set up RSP so that RSP[31:16] contains the 752 * respective 16 bits of the /userspace/ RSP and RSP nonetheless 753 * still points to an RO alias of the ESPFIX stack. 754 */ 755 orq PER_CPU_VAR(espfix_stack), %rax 756 757 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi 758 swapgs /* to user GS */ 759 popq %rdi /* Restore user RDI */ 760 761 movq %rax, %rsp 762 UNWIND_HINT_IRET_REGS offset=8 763 764 /* 765 * At this point, we cannot write to the stack any more, but we can 766 * still read. 767 */ 768 popq %rax /* Restore user RAX */ 769 770 /* 771 * RSP now points to an ordinary IRET frame, except that the page 772 * is read-only and RSP[31:16] are preloaded with the userspace 773 * values. We can now IRET back to userspace. 774 */ 775 jmp native_irq_return_iret 776#endif 777SYM_CODE_END(common_interrupt_return) 778_ASM_NOKPROBE(common_interrupt_return) 779 780/* 781 * Reload gs selector with exception handling 782 * edi: new selector 783 * 784 * Is in entry.text as it shouldn't be instrumented. 785 */ 786SYM_FUNC_START(asm_load_gs_index) 787 FRAME_BEGIN 788 swapgs 789.Lgs_change: 790 ANNOTATE_NOENDBR // error_entry 791 movl %edi, %gs 7922: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE 793 swapgs 794 FRAME_END 795 RET 796 797 /* running with kernelgs */ 798.Lbad_gs: 799 swapgs /* switch back to user gs */ 800.macro ZAP_GS 801 /* This can't be a string because the preprocessor needs to see it. */ 802 movl $__USER_DS, %eax 803 movl %eax, %gs 804.endm 805 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG 806 xorl %eax, %eax 807 movl %eax, %gs 808 jmp 2b 809 810 _ASM_EXTABLE(.Lgs_change, .Lbad_gs) 811 812SYM_FUNC_END(asm_load_gs_index) 813EXPORT_SYMBOL(asm_load_gs_index) 814 815#ifdef CONFIG_XEN_PV 816/* 817 * A note on the "critical region" in our callback handler. 818 * We want to avoid stacking callback handlers due to events occurring 819 * during handling of the last event. To do this, we keep events disabled 820 * until we've done all processing. HOWEVER, we must enable events before 821 * popping the stack frame (can't be done atomically) and so it would still 822 * be possible to get enough handler activations to overflow the stack. 823 * Although unlikely, bugs of that kind are hard to track down, so we'd 824 * like to avoid the possibility. 825 * So, on entry to the handler we detect whether we interrupted an 826 * existing activation in its critical region -- if so, we pop the current 827 * activation and restart the handler using the previous one. 828 * 829 * C calling convention: exc_xen_hypervisor_callback(struct *pt_regs) 830 */ 831SYM_CODE_START_LOCAL(exc_xen_hypervisor_callback) 832 833/* 834 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will 835 * see the correct pointer to the pt_regs 836 */ 837 UNWIND_HINT_FUNC 838 movq %rdi, %rsp /* we don't return, adjust the stack frame */ 839 UNWIND_HINT_REGS 840 841 call xen_pv_evtchn_do_upcall 842 843 jmp error_return 844SYM_CODE_END(exc_xen_hypervisor_callback) 845 846/* 847 * Hypervisor uses this for application faults while it executes. 848 * We get here for two reasons: 849 * 1. Fault while reloading DS, ES, FS or GS 850 * 2. Fault while executing IRET 851 * Category 1 we do not need to fix up as Xen has already reloaded all segment 852 * registers that could be reloaded and zeroed the others. 853 * Category 2 we fix up by killing the current process. We cannot use the 854 * normal Linux return path in this case because if we use the IRET hypercall 855 * to pop the stack frame we end up in an infinite loop of failsafe callbacks. 856 * We distinguish between categories by comparing each saved segment register 857 * with its current contents: any discrepancy means we in category 1. 858 */ 859SYM_CODE_START(xen_failsafe_callback) 860 UNWIND_HINT_EMPTY 861 ENDBR 862 movl %ds, %ecx 863 cmpw %cx, 0x10(%rsp) 864 jne 1f 865 movl %es, %ecx 866 cmpw %cx, 0x18(%rsp) 867 jne 1f 868 movl %fs, %ecx 869 cmpw %cx, 0x20(%rsp) 870 jne 1f 871 movl %gs, %ecx 872 cmpw %cx, 0x28(%rsp) 873 jne 1f 874 /* All segments match their saved values => Category 2 (Bad IRET). */ 875 movq (%rsp), %rcx 876 movq 8(%rsp), %r11 877 addq $0x30, %rsp 878 pushq $0 /* RIP */ 879 UNWIND_HINT_IRET_REGS offset=8 880 jmp asm_exc_general_protection 8811: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ 882 movq (%rsp), %rcx 883 movq 8(%rsp), %r11 884 addq $0x30, %rsp 885 UNWIND_HINT_IRET_REGS 886 pushq $-1 /* orig_ax = -1 => not a system call */ 887 PUSH_AND_CLEAR_REGS 888 ENCODE_FRAME_POINTER 889 jmp error_return 890SYM_CODE_END(xen_failsafe_callback) 891#endif /* CONFIG_XEN_PV */ 892 893/* 894 * Save all registers in pt_regs. Return GSBASE related information 895 * in EBX depending on the availability of the FSGSBASE instructions: 896 * 897 * FSGSBASE R/EBX 898 * N 0 -> SWAPGS on exit 899 * 1 -> no SWAPGS on exit 900 * 901 * Y GSBASE value at entry, must be restored in paranoid_exit 902 * 903 * R14 - old CR3 904 * R15 - old SPEC_CTRL 905 */ 906SYM_CODE_START_LOCAL(paranoid_entry) 907 UNWIND_HINT_FUNC 908 PUSH_AND_CLEAR_REGS save_ret=1 909 ENCODE_FRAME_POINTER 8 910 911 /* 912 * Always stash CR3 in %r14. This value will be restored, 913 * verbatim, at exit. Needed if paranoid_entry interrupted 914 * another entry that already switched to the user CR3 value 915 * but has not yet returned to userspace. 916 * 917 * This is also why CS (stashed in the "iret frame" by the 918 * hardware at entry) can not be used: this may be a return 919 * to kernel code, but with a user CR3 value. 920 * 921 * Switching CR3 does not depend on kernel GSBASE so it can 922 * be done before switching to the kernel GSBASE. This is 923 * required for FSGSBASE because the kernel GSBASE has to 924 * be retrieved from a kernel internal table. 925 */ 926 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 927 928 /* 929 * Handling GSBASE depends on the availability of FSGSBASE. 930 * 931 * Without FSGSBASE the kernel enforces that negative GSBASE 932 * values indicate kernel GSBASE. With FSGSBASE no assumptions 933 * can be made about the GSBASE value when entering from user 934 * space. 935 */ 936 ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE 937 938 /* 939 * Read the current GSBASE and store it in %rbx unconditionally, 940 * retrieve and set the current CPUs kernel GSBASE. The stored value 941 * has to be restored in paranoid_exit unconditionally. 942 * 943 * The unconditional write to GS base below ensures that no subsequent 944 * loads based on a mispredicted GS base can happen, therefore no LFENCE 945 * is needed here. 946 */ 947 SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx 948 jmp .Lparanoid_gsbase_done 949 950.Lparanoid_entry_checkgs: 951 /* EBX = 1 -> kernel GSBASE active, no restore required */ 952 movl $1, %ebx 953 954 /* 955 * The kernel-enforced convention is a negative GSBASE indicates 956 * a kernel value. No SWAPGS needed on entry and exit. 957 */ 958 movl $MSR_GS_BASE, %ecx 959 rdmsr 960 testl %edx, %edx 961 js .Lparanoid_kernel_gsbase 962 963 /* EBX = 0 -> SWAPGS required on exit */ 964 xorl %ebx, %ebx 965 swapgs 966.Lparanoid_kernel_gsbase: 967 FENCE_SWAPGS_KERNEL_ENTRY 968.Lparanoid_gsbase_done: 969 970 /* 971 * Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like 972 * CR3 above, keep the old value in a callee saved register. 973 */ 974 IBRS_ENTER save_reg=%r15 975 UNTRAIN_RET 976 977 RET 978SYM_CODE_END(paranoid_entry) 979 980/* 981 * "Paranoid" exit path from exception stack. This is invoked 982 * only on return from non-NMI IST interrupts that came 983 * from kernel space. 984 * 985 * We may be returning to very strange contexts (e.g. very early 986 * in syscall entry), so checking for preemption here would 987 * be complicated. Fortunately, there's no good reason to try 988 * to handle preemption here. 989 * 990 * R/EBX contains the GSBASE related information depending on the 991 * availability of the FSGSBASE instructions: 992 * 993 * FSGSBASE R/EBX 994 * N 0 -> SWAPGS on exit 995 * 1 -> no SWAPGS on exit 996 * 997 * Y User space GSBASE, must be restored unconditionally 998 * 999 * R14 - old CR3 1000 * R15 - old SPEC_CTRL 1001 */ 1002SYM_CODE_START_LOCAL(paranoid_exit) 1003 UNWIND_HINT_REGS 1004 1005 /* 1006 * Must restore IBRS state before both CR3 and %GS since we need access 1007 * to the per-CPU x86_spec_ctrl_shadow variable. 1008 */ 1009 IBRS_EXIT save_reg=%r15 1010 1011 /* 1012 * The order of operations is important. RESTORE_CR3 requires 1013 * kernel GSBASE. 1014 * 1015 * NB to anyone to try to optimize this code: this code does 1016 * not execute at all for exceptions from user mode. Those 1017 * exceptions go through error_exit instead. 1018 */ 1019 RESTORE_CR3 scratch_reg=%rax save_reg=%r14 1020 1021 /* Handle the three GSBASE cases */ 1022 ALTERNATIVE "jmp .Lparanoid_exit_checkgs", "", X86_FEATURE_FSGSBASE 1023 1024 /* With FSGSBASE enabled, unconditionally restore GSBASE */ 1025 wrgsbase %rbx 1026 jmp restore_regs_and_return_to_kernel 1027 1028.Lparanoid_exit_checkgs: 1029 /* On non-FSGSBASE systems, conditionally do SWAPGS */ 1030 testl %ebx, %ebx 1031 jnz restore_regs_and_return_to_kernel 1032 1033 /* We are returning to a context with user GSBASE */ 1034 swapgs 1035 jmp restore_regs_and_return_to_kernel 1036SYM_CODE_END(paranoid_exit) 1037 1038/* 1039 * Switch GS and CR3 if needed. 1040 */ 1041SYM_CODE_START_LOCAL(error_entry) 1042 UNWIND_HINT_FUNC 1043 1044 PUSH_AND_CLEAR_REGS save_ret=1 1045 ENCODE_FRAME_POINTER 8 1046 1047 testb $3, CS+8(%rsp) 1048 jz .Lerror_kernelspace 1049 1050 /* 1051 * We entered from user mode or we're pretending to have entered 1052 * from user mode due to an IRET fault. 1053 */ 1054 swapgs 1055 FENCE_SWAPGS_USER_ENTRY 1056 /* We have user CR3. Change to kernel CR3. */ 1057 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1058 IBRS_ENTER 1059 UNTRAIN_RET 1060 1061 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */ 1062.Lerror_entry_from_usermode_after_swapgs: 1063 1064 /* Put us onto the real thread stack. */ 1065 call sync_regs 1066 RET 1067 1068 /* 1069 * There are two places in the kernel that can potentially fault with 1070 * usergs. Handle them here. B stepping K8s sometimes report a 1071 * truncated RIP for IRET exceptions returning to compat mode. Check 1072 * for these here too. 1073 */ 1074.Lerror_kernelspace: 1075 leaq native_irq_return_iret(%rip), %rcx 1076 cmpq %rcx, RIP+8(%rsp) 1077 je .Lerror_bad_iret 1078 movl %ecx, %eax /* zero extend */ 1079 cmpq %rax, RIP+8(%rsp) 1080 je .Lbstep_iret 1081 cmpq $.Lgs_change, RIP+8(%rsp) 1082 jne .Lerror_entry_done_lfence 1083 1084 /* 1085 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up 1086 * gsbase and proceed. We'll fix up the exception and land in 1087 * .Lgs_change's error handler with kernel gsbase. 1088 */ 1089 swapgs 1090 1091 /* 1092 * Issue an LFENCE to prevent GS speculation, regardless of whether it is a 1093 * kernel or user gsbase. 1094 */ 1095.Lerror_entry_done_lfence: 1096 FENCE_SWAPGS_KERNEL_ENTRY 1097 leaq 8(%rsp), %rax /* return pt_regs pointer */ 1098 ANNOTATE_UNRET_END 1099 RET 1100 1101.Lbstep_iret: 1102 /* Fix truncated RIP */ 1103 movq %rcx, RIP+8(%rsp) 1104 /* fall through */ 1105 1106.Lerror_bad_iret: 1107 /* 1108 * We came from an IRET to user mode, so we have user 1109 * gsbase and CR3. Switch to kernel gsbase and CR3: 1110 */ 1111 swapgs 1112 FENCE_SWAPGS_USER_ENTRY 1113 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax 1114 IBRS_ENTER 1115 UNTRAIN_RET 1116 1117 /* 1118 * Pretend that the exception came from user mode: set up pt_regs 1119 * as if we faulted immediately after IRET. 1120 */ 1121 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */ 1122 call fixup_bad_iret 1123 mov %rax, %rdi 1124 jmp .Lerror_entry_from_usermode_after_swapgs 1125SYM_CODE_END(error_entry) 1126 1127SYM_CODE_START_LOCAL(error_return) 1128 UNWIND_HINT_REGS 1129 DEBUG_ENTRY_ASSERT_IRQS_OFF 1130 testb $3, CS(%rsp) 1131 jz restore_regs_and_return_to_kernel 1132 jmp swapgs_restore_regs_and_return_to_usermode 1133SYM_CODE_END(error_return) 1134 1135/* 1136 * Runs on exception stack. Xen PV does not go through this path at all, 1137 * so we can use real assembly here. 1138 * 1139 * Registers: 1140 * %r14: Used to save/restore the CR3 of the interrupted context 1141 * when PAGE_TABLE_ISOLATION is in use. Do not clobber. 1142 */ 1143SYM_CODE_START(asm_exc_nmi) 1144 UNWIND_HINT_IRET_REGS 1145 ENDBR 1146 1147 /* 1148 * We allow breakpoints in NMIs. If a breakpoint occurs, then 1149 * the iretq it performs will take us out of NMI context. 1150 * This means that we can have nested NMIs where the next 1151 * NMI is using the top of the stack of the previous NMI. We 1152 * can't let it execute because the nested NMI will corrupt the 1153 * stack of the previous NMI. NMI handlers are not re-entrant 1154 * anyway. 1155 * 1156 * To handle this case we do the following: 1157 * Check the a special location on the stack that contains 1158 * a variable that is set when NMIs are executing. 1159 * The interrupted task's stack is also checked to see if it 1160 * is an NMI stack. 1161 * If the variable is not set and the stack is not the NMI 1162 * stack then: 1163 * o Set the special variable on the stack 1164 * o Copy the interrupt frame into an "outermost" location on the 1165 * stack 1166 * o Copy the interrupt frame into an "iret" location on the stack 1167 * o Continue processing the NMI 1168 * If the variable is set or the previous stack is the NMI stack: 1169 * o Modify the "iret" location to jump to the repeat_nmi 1170 * o return back to the first NMI 1171 * 1172 * Now on exit of the first NMI, we first clear the stack variable 1173 * The NMI stack will tell any nested NMIs at that point that it is 1174 * nested. Then we pop the stack normally with iret, and if there was 1175 * a nested NMI that updated the copy interrupt stack frame, a 1176 * jump will be made to the repeat_nmi code that will handle the second 1177 * NMI. 1178 * 1179 * However, espfix prevents us from directly returning to userspace 1180 * with a single IRET instruction. Similarly, IRET to user mode 1181 * can fault. We therefore handle NMIs from user space like 1182 * other IST entries. 1183 */ 1184 1185 ASM_CLAC 1186 cld 1187 1188 /* Use %rdx as our temp variable throughout */ 1189 pushq %rdx 1190 1191 testb $3, CS-RIP+8(%rsp) 1192 jz .Lnmi_from_kernel 1193 1194 /* 1195 * NMI from user mode. We need to run on the thread stack, but we 1196 * can't go through the normal entry paths: NMIs are masked, and 1197 * we don't want to enable interrupts, because then we'll end 1198 * up in an awkward situation in which IRQs are on but NMIs 1199 * are off. 1200 * 1201 * We also must not push anything to the stack before switching 1202 * stacks lest we corrupt the "NMI executing" variable. 1203 */ 1204 1205 swapgs 1206 FENCE_SWAPGS_USER_ENTRY 1207 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx 1208 movq %rsp, %rdx 1209 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp 1210 UNWIND_HINT_IRET_REGS base=%rdx offset=8 1211 pushq 5*8(%rdx) /* pt_regs->ss */ 1212 pushq 4*8(%rdx) /* pt_regs->rsp */ 1213 pushq 3*8(%rdx) /* pt_regs->flags */ 1214 pushq 2*8(%rdx) /* pt_regs->cs */ 1215 pushq 1*8(%rdx) /* pt_regs->rip */ 1216 UNWIND_HINT_IRET_REGS 1217 pushq $-1 /* pt_regs->orig_ax */ 1218 PUSH_AND_CLEAR_REGS rdx=(%rdx) 1219 ENCODE_FRAME_POINTER 1220 1221 IBRS_ENTER 1222 UNTRAIN_RET 1223 1224 /* 1225 * At this point we no longer need to worry about stack damage 1226 * due to nesting -- we're on the normal thread stack and we're 1227 * done with the NMI stack. 1228 */ 1229 1230 movq %rsp, %rdi 1231 movq $-1, %rsi 1232 call exc_nmi 1233 1234 /* 1235 * Return back to user mode. We must *not* do the normal exit 1236 * work, because we don't want to enable interrupts. 1237 */ 1238 jmp swapgs_restore_regs_and_return_to_usermode 1239 1240.Lnmi_from_kernel: 1241 /* 1242 * Here's what our stack frame will look like: 1243 * +---------------------------------------------------------+ 1244 * | original SS | 1245 * | original Return RSP | 1246 * | original RFLAGS | 1247 * | original CS | 1248 * | original RIP | 1249 * +---------------------------------------------------------+ 1250 * | temp storage for rdx | 1251 * +---------------------------------------------------------+ 1252 * | "NMI executing" variable | 1253 * +---------------------------------------------------------+ 1254 * | iret SS } Copied from "outermost" frame | 1255 * | iret Return RSP } on each loop iteration; overwritten | 1256 * | iret RFLAGS } by a nested NMI to force another | 1257 * | iret CS } iteration if needed. | 1258 * | iret RIP } | 1259 * +---------------------------------------------------------+ 1260 * | outermost SS } initialized in first_nmi; | 1261 * | outermost Return RSP } will not be changed before | 1262 * | outermost RFLAGS } NMI processing is done. | 1263 * | outermost CS } Copied to "iret" frame on each | 1264 * | outermost RIP } iteration. | 1265 * +---------------------------------------------------------+ 1266 * | pt_regs | 1267 * +---------------------------------------------------------+ 1268 * 1269 * The "original" frame is used by hardware. Before re-enabling 1270 * NMIs, we need to be done with it, and we need to leave enough 1271 * space for the asm code here. 1272 * 1273 * We return by executing IRET while RSP points to the "iret" frame. 1274 * That will either return for real or it will loop back into NMI 1275 * processing. 1276 * 1277 * The "outermost" frame is copied to the "iret" frame on each 1278 * iteration of the loop, so each iteration starts with the "iret" 1279 * frame pointing to the final return target. 1280 */ 1281 1282 /* 1283 * Determine whether we're a nested NMI. 1284 * 1285 * If we interrupted kernel code between repeat_nmi and 1286 * end_repeat_nmi, then we are a nested NMI. We must not 1287 * modify the "iret" frame because it's being written by 1288 * the outer NMI. That's okay; the outer NMI handler is 1289 * about to about to call exc_nmi() anyway, so we can just 1290 * resume the outer NMI. 1291 */ 1292 1293 movq $repeat_nmi, %rdx 1294 cmpq 8(%rsp), %rdx 1295 ja 1f 1296 movq $end_repeat_nmi, %rdx 1297 cmpq 8(%rsp), %rdx 1298 ja nested_nmi_out 12991: 1300 1301 /* 1302 * Now check "NMI executing". If it's set, then we're nested. 1303 * This will not detect if we interrupted an outer NMI just 1304 * before IRET. 1305 */ 1306 cmpl $1, -8(%rsp) 1307 je nested_nmi 1308 1309 /* 1310 * Now test if the previous stack was an NMI stack. This covers 1311 * the case where we interrupt an outer NMI after it clears 1312 * "NMI executing" but before IRET. We need to be careful, though: 1313 * there is one case in which RSP could point to the NMI stack 1314 * despite there being no NMI active: naughty userspace controls 1315 * RSP at the very beginning of the SYSCALL targets. We can 1316 * pull a fast one on naughty userspace, though: we program 1317 * SYSCALL to mask DF, so userspace cannot cause DF to be set 1318 * if it controls the kernel's RSP. We set DF before we clear 1319 * "NMI executing". 1320 */ 1321 lea 6*8(%rsp), %rdx 1322 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ 1323 cmpq %rdx, 4*8(%rsp) 1324 /* If the stack pointer is above the NMI stack, this is a normal NMI */ 1325 ja first_nmi 1326 1327 subq $EXCEPTION_STKSZ, %rdx 1328 cmpq %rdx, 4*8(%rsp) 1329 /* If it is below the NMI stack, it is a normal NMI */ 1330 jb first_nmi 1331 1332 /* Ah, it is within the NMI stack. */ 1333 1334 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) 1335 jz first_nmi /* RSP was user controlled. */ 1336 1337 /* This is a nested NMI. */ 1338 1339nested_nmi: 1340 /* 1341 * Modify the "iret" frame to point to repeat_nmi, forcing another 1342 * iteration of NMI handling. 1343 */ 1344 subq $8, %rsp 1345 leaq -10*8(%rsp), %rdx 1346 pushq $__KERNEL_DS 1347 pushq %rdx 1348 pushfq 1349 pushq $__KERNEL_CS 1350 pushq $repeat_nmi 1351 1352 /* Put stack back */ 1353 addq $(6*8), %rsp 1354 1355nested_nmi_out: 1356 popq %rdx 1357 1358 /* We are returning to kernel mode, so this cannot result in a fault. */ 1359 iretq 1360 1361first_nmi: 1362 /* Restore rdx. */ 1363 movq (%rsp), %rdx 1364 1365 /* Make room for "NMI executing". */ 1366 pushq $0 1367 1368 /* Leave room for the "iret" frame */ 1369 subq $(5*8), %rsp 1370 1371 /* Copy the "original" frame to the "outermost" frame */ 1372 .rept 5 1373 pushq 11*8(%rsp) 1374 .endr 1375 UNWIND_HINT_IRET_REGS 1376 1377 /* Everything up to here is safe from nested NMIs */ 1378 1379#ifdef CONFIG_DEBUG_ENTRY 1380 /* 1381 * For ease of testing, unmask NMIs right away. Disabled by 1382 * default because IRET is very expensive. 1383 */ 1384 pushq $0 /* SS */ 1385 pushq %rsp /* RSP (minus 8 because of the previous push) */ 1386 addq $8, (%rsp) /* Fix up RSP */ 1387 pushfq /* RFLAGS */ 1388 pushq $__KERNEL_CS /* CS */ 1389 pushq $1f /* RIP */ 1390 iretq /* continues at repeat_nmi below */ 1391 UNWIND_HINT_IRET_REGS 13921: 1393#endif 1394 1395repeat_nmi: 1396 ANNOTATE_NOENDBR // this code 1397 /* 1398 * If there was a nested NMI, the first NMI's iret will return 1399 * here. But NMIs are still enabled and we can take another 1400 * nested NMI. The nested NMI checks the interrupted RIP to see 1401 * if it is between repeat_nmi and end_repeat_nmi, and if so 1402 * it will just return, as we are about to repeat an NMI anyway. 1403 * This makes it safe to copy to the stack frame that a nested 1404 * NMI will update. 1405 * 1406 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if 1407 * we're repeating an NMI, gsbase has the same value that it had on 1408 * the first iteration. paranoid_entry will load the kernel 1409 * gsbase if needed before we call exc_nmi(). "NMI executing" 1410 * is zero. 1411 */ 1412 movq $1, 10*8(%rsp) /* Set "NMI executing". */ 1413 1414 /* 1415 * Copy the "outermost" frame to the "iret" frame. NMIs that nest 1416 * here must not modify the "iret" frame while we're writing to 1417 * it or it will end up containing garbage. 1418 */ 1419 addq $(10*8), %rsp 1420 .rept 5 1421 pushq -6*8(%rsp) 1422 .endr 1423 subq $(5*8), %rsp 1424end_repeat_nmi: 1425 ANNOTATE_NOENDBR // this code 1426 1427 /* 1428 * Everything below this point can be preempted by a nested NMI. 1429 * If this happens, then the inner NMI will change the "iret" 1430 * frame to point back to repeat_nmi. 1431 */ 1432 pushq $-1 /* ORIG_RAX: no syscall to restart */ 1433 1434 /* 1435 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit 1436 * as we should not be calling schedule in NMI context. 1437 * Even with normal interrupts enabled. An NMI should not be 1438 * setting NEED_RESCHED or anything that normal interrupts and 1439 * exceptions might do. 1440 */ 1441 call paranoid_entry 1442 UNWIND_HINT_REGS 1443 1444 movq %rsp, %rdi 1445 movq $-1, %rsi 1446 call exc_nmi 1447 1448 /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */ 1449 IBRS_EXIT save_reg=%r15 1450 1451 /* Always restore stashed CR3 value (see paranoid_entry) */ 1452 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 1453 1454 /* 1455 * The above invocation of paranoid_entry stored the GSBASE 1456 * related information in R/EBX depending on the availability 1457 * of FSGSBASE. 1458 * 1459 * If FSGSBASE is enabled, restore the saved GSBASE value 1460 * unconditionally, otherwise take the conditional SWAPGS path. 1461 */ 1462 ALTERNATIVE "jmp nmi_no_fsgsbase", "", X86_FEATURE_FSGSBASE 1463 1464 wrgsbase %rbx 1465 jmp nmi_restore 1466 1467nmi_no_fsgsbase: 1468 /* EBX == 0 -> invoke SWAPGS */ 1469 testl %ebx, %ebx 1470 jnz nmi_restore 1471 1472nmi_swapgs: 1473 swapgs 1474 1475nmi_restore: 1476 POP_REGS 1477 1478 /* 1479 * Skip orig_ax and the "outermost" frame to point RSP at the "iret" 1480 * at the "iret" frame. 1481 */ 1482 addq $6*8, %rsp 1483 1484 /* 1485 * Clear "NMI executing". Set DF first so that we can easily 1486 * distinguish the remaining code between here and IRET from 1487 * the SYSCALL entry and exit paths. 1488 * 1489 * We arguably should just inspect RIP instead, but I (Andy) wrote 1490 * this code when I had the misapprehension that Xen PV supported 1491 * NMIs, and Xen PV would break that approach. 1492 */ 1493 std 1494 movq $0, 5*8(%rsp) /* clear "NMI executing" */ 1495 1496 /* 1497 * iretq reads the "iret" frame and exits the NMI stack in a 1498 * single instruction. We are returning to kernel mode, so this 1499 * cannot result in a fault. Similarly, we don't need to worry 1500 * about espfix64 on the way back to kernel mode. 1501 */ 1502 iretq 1503SYM_CODE_END(asm_exc_nmi) 1504 1505#ifndef CONFIG_IA32_EMULATION 1506/* 1507 * This handles SYSCALL from 32-bit code. There is no way to program 1508 * MSRs to fully disable 32-bit SYSCALL. 1509 */ 1510SYM_CODE_START(ignore_sysret) 1511 UNWIND_HINT_EMPTY 1512 ENDBR 1513 mov $-ENOSYS, %eax 1514 sysretl 1515SYM_CODE_END(ignore_sysret) 1516#endif 1517 1518.pushsection .text, "ax" 1519SYM_CODE_START(rewind_stack_and_make_dead) 1520 UNWIND_HINT_FUNC 1521 /* Prevent any naive code from trying to unwind to our caller. */ 1522 xorl %ebp, %ebp 1523 1524 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax 1525 leaq -PTREGS_SIZE(%rax), %rsp 1526 UNWIND_HINT_REGS 1527 1528 call make_task_dead 1529SYM_CODE_END(rewind_stack_and_make_dead) 1530.popsection 1531