1 // SPDX-License-Identifier: GPL-2.0
2 #include "misc.h"
3 #include <asm/e820/types.h>
4 #include <asm/processor.h>
5 #include "pgtable.h"
6 #include "../string.h"
7 #include "efi.h"
8
9 #define BIOS_START_MIN 0x20000U /* 128K, less than this is insane */
10 #define BIOS_START_MAX 0x9f000U /* 640K, absolute maximum */
11
12 #ifdef CONFIG_X86_5LEVEL
13 /* __pgtable_l5_enabled needs to be in .data to avoid being cleared along with .bss */
14 unsigned int __section(".data") __pgtable_l5_enabled;
15 unsigned int __section(".data") pgdir_shift = 39;
16 unsigned int __section(".data") ptrs_per_p4d = 1;
17 #endif
18
19 struct paging_config {
20 unsigned long trampoline_start;
21 unsigned long l5_required;
22 };
23
24 /* Buffer to preserve trampoline memory */
25 static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
26
27 /*
28 * Trampoline address will be printed by extract_kernel() for debugging
29 * purposes.
30 *
31 * Avoid putting the pointer into .bss as it will be cleared between
32 * paging_prepare() and extract_kernel().
33 */
34 unsigned long *trampoline_32bit __section(".data");
35
36 extern struct boot_params *boot_params;
37 int cmdline_find_option_bool(const char *option);
38
find_trampoline_placement(void)39 static unsigned long find_trampoline_placement(void)
40 {
41 unsigned long bios_start = 0, ebda_start = 0;
42 struct boot_e820_entry *entry;
43 char *signature;
44 int i;
45
46 /*
47 * Find a suitable spot for the trampoline.
48 * This code is based on reserve_bios_regions().
49 */
50
51 /*
52 * EFI systems may not provide legacy ROM. The memory may not be mapped
53 * at all.
54 *
55 * Only look for values in the legacy ROM for non-EFI system.
56 */
57 signature = (char *)&boot_params->efi_info.efi_loader_signature;
58 if (strncmp(signature, EFI32_LOADER_SIGNATURE, 4) &&
59 strncmp(signature, EFI64_LOADER_SIGNATURE, 4)) {
60 ebda_start = *(unsigned short *)0x40e << 4;
61 bios_start = *(unsigned short *)0x413 << 10;
62 }
63
64 if (bios_start < BIOS_START_MIN || bios_start > BIOS_START_MAX)
65 bios_start = BIOS_START_MAX;
66
67 if (ebda_start > BIOS_START_MIN && ebda_start < bios_start)
68 bios_start = ebda_start;
69
70 bios_start = round_down(bios_start, PAGE_SIZE);
71
72 /* Find the first usable memory region under bios_start. */
73 for (i = boot_params->e820_entries - 1; i >= 0; i--) {
74 unsigned long new = bios_start;
75
76 entry = &boot_params->e820_table[i];
77
78 /* Skip all entries above bios_start. */
79 if (bios_start <= entry->addr)
80 continue;
81
82 /* Skip non-RAM entries. */
83 if (entry->type != E820_TYPE_RAM)
84 continue;
85
86 /* Adjust bios_start to the end of the entry if needed. */
87 if (bios_start > entry->addr + entry->size)
88 new = entry->addr + entry->size;
89
90 /* Keep bios_start page-aligned. */
91 new = round_down(new, PAGE_SIZE);
92
93 /* Skip the entry if it's too small. */
94 if (new - TRAMPOLINE_32BIT_SIZE < entry->addr)
95 continue;
96
97 /* Protect against underflow. */
98 if (new - TRAMPOLINE_32BIT_SIZE > bios_start)
99 break;
100
101 bios_start = new;
102 break;
103 }
104
105 /* Place the trampoline just below the end of low memory */
106 return bios_start - TRAMPOLINE_32BIT_SIZE;
107 }
108
paging_prepare(void * rmode)109 struct paging_config paging_prepare(void *rmode)
110 {
111 struct paging_config paging_config = {};
112
113 /* Initialize boot_params. Required for cmdline_find_option_bool(). */
114 boot_params = rmode;
115
116 /*
117 * Check if LA57 is desired and supported.
118 *
119 * There are several parts to the check:
120 * - if the kernel supports 5-level paging: CONFIG_X86_5LEVEL=y
121 * - if user asked to disable 5-level paging: no5lvl in cmdline
122 * - if the machine supports 5-level paging:
123 * + CPUID leaf 7 is supported
124 * + the leaf has the feature bit set
125 *
126 * That's substitute for boot_cpu_has() in early boot code.
127 */
128 if (IS_ENABLED(CONFIG_X86_5LEVEL) &&
129 !cmdline_find_option_bool("no5lvl") &&
130 native_cpuid_eax(0) >= 7 &&
131 (native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
132 paging_config.l5_required = 1;
133 }
134
135 paging_config.trampoline_start = find_trampoline_placement();
136
137 trampoline_32bit = (unsigned long *)paging_config.trampoline_start;
138
139 /* Preserve trampoline memory */
140 memcpy(trampoline_save, trampoline_32bit, TRAMPOLINE_32BIT_SIZE);
141
142 /* Clear trampoline memory first */
143 memset(trampoline_32bit, 0, TRAMPOLINE_32BIT_SIZE);
144
145 /* Copy trampoline code in place */
146 memcpy(trampoline_32bit + TRAMPOLINE_32BIT_CODE_OFFSET / sizeof(unsigned long),
147 &trampoline_32bit_src, TRAMPOLINE_32BIT_CODE_SIZE);
148
149 /*
150 * The code below prepares page table in trampoline memory.
151 *
152 * The new page table will be used by trampoline code for switching
153 * from 4- to 5-level paging or vice versa.
154 *
155 * If switching is not required, the page table is unused: trampoline
156 * code wouldn't touch CR3.
157 */
158
159 /*
160 * We are not going to use the page table in trampoline memory if we
161 * are already in the desired paging mode.
162 */
163 if (paging_config.l5_required == !!(native_read_cr4() & X86_CR4_LA57))
164 goto out;
165
166 if (paging_config.l5_required) {
167 /*
168 * For 4- to 5-level paging transition, set up current CR3 as
169 * the first and the only entry in a new top-level page table.
170 */
171 trampoline_32bit[TRAMPOLINE_32BIT_PGTABLE_OFFSET] = __native_read_cr3() | _PAGE_TABLE_NOENC;
172 } else {
173 unsigned long src;
174
175 /*
176 * For 5- to 4-level paging transition, copy page table pointed
177 * by first entry in the current top-level page table as our
178 * new top-level page table.
179 *
180 * We cannot just point to the page table from trampoline as it
181 * may be above 4G.
182 */
183 src = *(unsigned long *)__native_read_cr3() & PAGE_MASK;
184 memcpy(trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long),
185 (void *)src, PAGE_SIZE);
186 }
187
188 out:
189 return paging_config;
190 }
191
cleanup_trampoline(void * pgtable)192 void cleanup_trampoline(void *pgtable)
193 {
194 void *trampoline_pgtable;
195
196 trampoline_pgtable = trampoline_32bit + TRAMPOLINE_32BIT_PGTABLE_OFFSET / sizeof(unsigned long);
197
198 /*
199 * Move the top level page table out of trampoline memory,
200 * if it's there.
201 */
202 if ((void *)__native_read_cr3() == trampoline_pgtable) {
203 memcpy(pgtable, trampoline_pgtable, PAGE_SIZE);
204 native_write_cr3((unsigned long)pgtable);
205 }
206
207 /* Restore trampoline memory */
208 memcpy(trampoline_32bit, trampoline_save, TRAMPOLINE_32BIT_SIZE);
209
210 /* Initialize variables for 5-level paging */
211 #ifdef CONFIG_X86_5LEVEL
212 if (__read_cr4() & X86_CR4_LA57) {
213 __pgtable_l5_enabled = 1;
214 pgdir_shift = 48;
215 ptrs_per_p4d = 512;
216 }
217 #endif
218 }
219