1 /*
2 * arch/ppc/platforms/cpci405.c
3 *
4 * Board setup routines for the esd CPCI-405 cPCI Board.
5 *
6 * Author: Stefan Roese
7 * stefan.roese@esd-electronics.com
8 *
9 * Copyright 2001-2003 esd electronic system design - hannover germany
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * History: 11/09/2001 - armin
17 * added board_init to add in additional instuctions needed during platfrom_init
18 *
19 * : 03/26/03 - stefan
20 * Added cpci405_early_serial_map (cloned from evb405ep) to generate
21 * BASE_BAUD dynamically from the UDIV settings (configured by U-Boot).
22 *
23 */
24
25 #include <linux/config.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <asm/system.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
31 #include <asm/todc.h>
32 #include <linux/serial.h>
33
34 void *cpci405_nvram;
35
36 /*
37 * Some IRQs unique to CPCI-405.
38 */
39 int __init
ppc405_map_irq(struct pci_dev * dev,unsigned char idsel,unsigned char pin)40 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
41 {
42 static char pci_irq_table[][4] =
43 /*
44 * PCI IDSEL/INTPIN->INTLINE
45 * A B C D
46 */
47 {
48 {28, 28, 28, 28}, /* IDSEL 15 - cPCI slot 8 */
49 {29, 29, 29, 29}, /* IDSEL 16 - cPCI slot 7 */
50 {30, 30, 30, 30}, /* IDSEL 17 - cPCI slot 6 */
51 {27, 27, 27, 27}, /* IDSEL 18 - cPCI slot 5 */
52 {28, 28, 28, 28}, /* IDSEL 19 - cPCI slot 4 */
53 {29, 29, 29, 29}, /* IDSEL 20 - cPCI slot 3 */
54 {30, 30, 30, 30}, /* IDSEL 21 - cPCI slot 2 */
55 };
56 const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
57 return PCI_IRQ_TABLE_LOOKUP;
58 };
59
60 /* The serial clock for the chip is an internal clock determined by
61 * different clock speeds/dividers.
62 * Calculate the proper input baud rate and setup the serial driver.
63 */
64 static void __init
cpci405_early_serial_map(void)65 cpci405_early_serial_map(void)
66 {
67 u32 uart_div;
68 int serial_baud_405;
69 bd_t *bip = (bd_t *) __res;
70 struct serial_struct serialreq = {0};
71
72 /* Calculate the serial clock input frequency
73 *
74 * The base baud is the PLL OUTA (provided in the board info
75 * structure) divided by the external UART Divisor, divided
76 * by 16.
77 */
78 uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
79 serial_baud_405 = bip->bi_procfreq / uart_div / 16;
80
81 /* Update the serial port attributes */
82 serialreq.baud_base = serial_baud_405;
83 serialreq.flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST);
84 serialreq.io_type = SERIAL_IO_MEM;
85
86 serialreq.line = 0;
87 serialreq.port = 0;
88 serialreq.irq = ACTING_UART0_INT;
89 serialreq.iomem_base = (void*)ACTING_UART0_IO_BASE;
90
91 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
92 /* Configure debug serial access */
93 gen550_init(0, &serialreq);
94 #endif
95
96 if (early_serial_setup(&serialreq) != 0) {
97 printk("Early serial init of port 0 failed\n");
98 }
99
100 serialreq.line = 1;
101 serialreq.port = 1;
102 serialreq.irq = ACTING_UART1_INT;
103 serialreq.iomem_base = (void*)ACTING_UART1_IO_BASE;
104
105 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
106 /* Configure debug serial access */
107 gen550_init(1, &serialreq);
108 #endif
109
110 if (early_serial_setup(&serialreq) != 0) {
111 printk("Early serial init of port 1 failed\n");
112 }
113 }
114
115 void __init
board_setup_arch(void)116 board_setup_arch(void)
117 {
118 cpci405_early_serial_map();
119 TODC_INIT(TODC_TYPE_MK48T35, cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
120 }
121
122 void __init
board_io_mapping(void)123 board_io_mapping(void)
124 {
125 cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
126 }
127
128 void __init
board_setup_irq(void)129 board_setup_irq(void)
130 {
131 }
132
133 void __init
board_init(void)134 board_init(void)
135 {
136 ppc_md.time_init = todc_time_init;
137 ppc_md.set_rtc_time = todc_set_rtc_time;
138 ppc_md.get_rtc_time = todc_get_rtc_time;
139 ppc_md.nvram_read_val = todc_direct_read_val;
140 ppc_md.nvram_write_val = todc_direct_write_val;
141 }
142