1 /* 2 * arch/ppc/kernel/cputable.c 3 * 4 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/config.h> 13 #include <linux/string.h> 14 #include <linux/sched.h> 15 #include <linux/threads.h> 16 #include <linux/init.h> 17 #include <asm/cputable.h> 18 19 struct cpu_spec* cur_cpu_spec[NR_CPUS]; 20 21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 33 extern void __setup_cpu_8xx(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 34 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec); 35 36 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ 37 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4)) 38 39 /* This table only contains "desktop" CPUs, it need to be filled with embedded 40 * ones as well... 41 */ 42 #define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \ 43 PPC_FEATURE_HAS_MMU) 44 45 /* We only set the altivec features if the kernel was compiled with altivec 46 * support 47 */ 48 #ifdef CONFIG_ALTIVEC 49 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 50 #else 51 #define CPU_FTR_ALTIVEC_COMP 0 52 #endif 53 54 /* We need to mark all pages as being coherent if we're SMP or we 55 * have a 754x and an MPC107 host bridge. 56 */ 57 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) 58 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 59 #else 60 #define CPU_FTR_COMMON 0 61 #endif 62 63 struct cpu_spec cpu_specs[] = { 64 #if CLASSIC_PPC 65 { /* 601 */ 66 0xffff0000, 0x00010000, "601", 67 CPU_FTR_COMMON | 68 CPU_FTR_601 | CPU_FTR_HPTE_TABLE, 69 COMMON_PPC | PPC_FEATURE_601_INSTR | PPC_FEATURE_UNIFIED_CACHE, 70 32, 32, 71 __setup_cpu_601 72 }, 73 { /* 603 */ 74 0xffff0000, 0x00030000, "603", 75 CPU_FTR_COMMON | 76 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 77 CPU_FTR_CAN_NAP, 78 COMMON_PPC, 79 32, 32, 80 __setup_cpu_603 81 }, 82 { /* 603e */ 83 0xffff0000, 0x00060000, "603e", 84 CPU_FTR_COMMON | 85 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 86 CPU_FTR_CAN_NAP, 87 COMMON_PPC, 88 32, 32, 89 __setup_cpu_603 90 }, 91 { /* 603ev */ 92 0xffff0000, 0x00070000, "603ev", 93 CPU_FTR_COMMON | 94 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 95 CPU_FTR_CAN_NAP, 96 COMMON_PPC, 97 32, 32, 98 __setup_cpu_603 99 }, 100 { /* 604 */ 101 0xffff0000, 0x00040000, "604", 102 CPU_FTR_COMMON | 103 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | 104 CPU_FTR_HPTE_TABLE, 105 COMMON_PPC, 106 32, 32, 107 __setup_cpu_604 108 }, 109 { /* 604e */ 110 0xfffff000, 0x00090000, "604e", 111 CPU_FTR_COMMON | 112 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | 113 CPU_FTR_HPTE_TABLE, 114 COMMON_PPC, 115 32, 32, 116 __setup_cpu_604 117 }, 118 { /* 604r */ 119 0xffff0000, 0x00090000, "604r", 120 CPU_FTR_COMMON | 121 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | 122 CPU_FTR_HPTE_TABLE, 123 COMMON_PPC, 124 32, 32, 125 __setup_cpu_604 126 }, 127 { /* 604ev */ 128 0xffff0000, 0x000a0000, "604ev", 129 CPU_FTR_COMMON | 130 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | 131 CPU_FTR_HPTE_TABLE, 132 COMMON_PPC, 133 32, 32, 134 __setup_cpu_604 135 }, 136 { /* 740/750 (0x4202, don't support TAU ?) */ 137 0xffffffff, 0x00084202, "740/750", 138 CPU_FTR_COMMON | 139 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 140 CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP, 141 COMMON_PPC, 142 32, 32, 143 __setup_cpu_750 144 }, 145 { /* 745/755 */ 146 0xfffff000, 0x00083000, "745/755", 147 CPU_FTR_COMMON | 148 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 149 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP, 150 COMMON_PPC, 151 32, 32, 152 __setup_cpu_750 153 }, 154 { /* 750CX */ 155 0xffffff00, 0x00082200, "750CX", 156 CPU_FTR_COMMON | 157 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 158 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP, 159 COMMON_PPC, 160 32, 32, 161 __setup_cpu_750cx 162 }, 163 { /* 750FX rev 1.x */ 164 0xffffff00, 0x70000100, "750FX", 165 CPU_FTR_COMMON | 166 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 167 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP | 168 CPU_FTR_750FX | CPU_FTR_NO_DPM, 169 COMMON_PPC, 170 32, 32, 171 __setup_cpu_750 172 }, 173 { /* 750FX rev 2.0 must disable HID0[DPM] */ 174 0xffffffff, 0x70000200, "750FX", 175 CPU_FTR_COMMON | 176 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 177 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP | 178 CPU_FTR_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NO_DPM, 179 COMMON_PPC, 180 32, 32, 181 __setup_cpu_750 182 }, 183 { /* 750FX (All revs > 2.0) */ 184 0xffff0000, 0x70000000, "750FX", 185 CPU_FTR_COMMON | 186 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 187 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP | 188 CPU_FTR_750FX | CPU_FTR_HAS_HIGH_BATS, 189 COMMON_PPC, 190 32, 32, 191 __setup_cpu_750fx 192 }, 193 { /* 740/750 (L2CR bit need fixup for 740) */ 194 0xffff0000, 0x00080000, "740/750", 195 CPU_FTR_COMMON | 196 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 197 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_CAN_NAP, 198 COMMON_PPC, 199 32, 32, 200 __setup_cpu_750 201 }, 202 { /* 7400 rev 1.1 ? (no TAU) */ 203 0xffffffff, 0x000c1101, "7400 (1.1)", 204 CPU_FTR_COMMON | 205 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 206 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | 207 CPU_FTR_CAN_NAP, 208 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 209 32, 32, 210 __setup_cpu_7400 211 }, 212 { /* 7400 */ 213 0xffff0000, 0x000c0000, "7400", 214 CPU_FTR_COMMON | 215 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 216 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | 217 CPU_FTR_CAN_NAP, 218 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 219 32, 32, 220 __setup_cpu_7400 221 }, 222 { /* 7410 */ 223 0xffff0000, 0x800c0000, "7410", 224 CPU_FTR_COMMON | 225 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 226 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | 227 CPU_FTR_CAN_NAP, 228 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 229 32, 32, 230 __setup_cpu_7410 231 }, 232 { /* 7450 1.x - no doze/nap */ 233 0xffffff00, 0x80000100, "7450", 234 CPU_FTR_COMMON | 235 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 236 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 237 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT, 238 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 239 32, 32, 240 __setup_cpu_745x 241 }, 242 { /* 7450 2.0 - no doze/nap */ 243 0xffffffff, 0x80000200, "7450", 244 CPU_FTR_COMMON | 245 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 246 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 247 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT, 248 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 249 32, 32, 250 __setup_cpu_745x 251 }, 252 { /* 7450 2.1 */ 253 0xffffffff, 0x80000201, "7450", 254 CPU_FTR_COMMON | 255 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | 256 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 257 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | 258 CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT, 259 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 260 32, 32, 261 __setup_cpu_745x 262 }, 263 { /* 7450 2.3 and newer */ 264 0xffff0000, 0x80000000, "7450", 265 CPU_FTR_COMMON | 266 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | 267 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 268 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | 269 CPU_FTR_NEED_COHERENT, 270 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 271 32, 32, 272 __setup_cpu_745x 273 }, 274 { /* 7455 rev 1.x */ 275 0xffffff00, 0x80010100, "7455", 276 CPU_FTR_COMMON | 277 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | 278 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 279 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | 280 CPU_FTR_NEED_COHERENT, 281 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 282 32, 32, 283 __setup_cpu_745x 284 }, 285 { /* 7455 rev 2.0 */ 286 0xffffffff, 0x80010200, "7455", 287 CPU_FTR_COMMON | 288 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | 289 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 290 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | 291 CPU_FTR_L3_DISABLE_NAP | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS, 292 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 293 32, 32, 294 __setup_cpu_745x 295 }, 296 { /* 7455 others */ 297 0xffff0000, 0x80010000, "7455", 298 CPU_FTR_COMMON | 299 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | 300 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 301 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | 302 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT, 303 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 304 32, 32, 305 __setup_cpu_745x 306 }, 307 { /* 7457 */ 308 0xffff0000, 0x80020000, "7457", 309 CPU_FTR_COMMON | 310 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | 311 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | 312 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | 313 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT, 314 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 315 32, 32, 316 __setup_cpu_745x 317 }, 318 { /* 7447A */ 319 0xffff0000, 0x80030000, "7447A", 320 CPU_FTR_COMMON | 321 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_CAN_NAP | 322 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | 323 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | 324 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT, 325 COMMON_PPC | PPC_FEATURE_HAS_ALTIVEC, 326 32, 32, 327 __setup_cpu_745x 328 }, 329 { /* 82xx (8240, 8245, 8260 are all 603e cores) */ 330 0x7fff0000, 0x00810000, "82xx", 331 CPU_FTR_COMMON | 332 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB, 333 COMMON_PPC, 334 32, 32, 335 __setup_cpu_603 336 }, 337 { /* 8280 is a G2_LE (603e core, plus some) */ 338 0x7fff0000, 0x00820000, "8280", 339 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_CAN_DOZE | CPU_FTR_USE_TB | 340 CPU_FTR_CAN_NAP | CPU_FTR_HAS_HIGH_BATS, 341 COMMON_PPC, 342 32, 32, 343 __setup_cpu_603 344 }, 345 { /* default match, we assume split I/D cache & TB (non-601)... */ 346 0x00000000, 0x00000000, "(generic PPC)", 347 CPU_FTR_COMMON | 348 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 349 COMMON_PPC, 350 32, 32, 351 __setup_cpu_generic 352 }, 353 #endif /* CLASSIC_PPC */ 354 #ifdef CONFIG_PPC64BRIDGE 355 { /* Power3 */ 356 0xffff0000, 0x00400000, "Power3 (630)", 357 CPU_FTR_COMMON | 358 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 359 COMMON_PPC | PPC_FEATURE_64, 360 128, 128, 361 __setup_cpu_power3 362 }, 363 { /* Power3+ */ 364 0xffff0000, 0x00410000, "Power3 (630+)", 365 CPU_FTR_COMMON | 366 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 367 COMMON_PPC | PPC_FEATURE_64, 368 128, 128, 369 __setup_cpu_power3 370 }, 371 { /* I-star */ 372 0xffff0000, 0x00360000, "I-star", 373 CPU_FTR_COMMON | 374 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 375 COMMON_PPC | PPC_FEATURE_64, 376 128, 128, 377 __setup_cpu_power3 378 }, 379 { /* S-star */ 380 0xffff0000, 0x00370000, "S-star", 381 CPU_FTR_COMMON | 382 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 383 COMMON_PPC | PPC_FEATURE_64, 384 128, 128, 385 __setup_cpu_power3 386 }, 387 #endif /* CONFIG_PPC64BRIDGE */ 388 #ifdef CONFIG_POWER4 389 { /* Power4 */ 390 0xffff0000, 0x00350000, "Power4", 391 CPU_FTR_COMMON | 392 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, 393 COMMON_PPC | PPC_FEATURE_64, 394 128, 128, 395 __setup_cpu_power4 396 }, 397 { /* PPC970 */ 398 0xffff0000, 0x00390000, "PPC970", 399 CPU_FTR_COMMON | 400 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | 401 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP, 402 COMMON_PPC | PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC, 403 128, 128, 404 __setup_cpu_ppc970 405 }, 406 #endif /* CONFIG_POWER4 */ 407 #ifdef CONFIG_8xx 408 { /* 8xx */ 409 0xffff0000, 0x00500000, "8xx", 410 /* CPU_FTR_CAN_DOZE is possible, if the 8xx code is there.... */ 411 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 412 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 413 16, 16, 414 __setup_cpu_8xx /* Empty */ 415 }, 416 #endif /* CONFIG_8xx */ 417 #ifdef CONFIG_40x 418 { /* 403GC */ 419 0xffffff00, 0x00200200, "403GC", 420 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 421 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 422 16, 16, 423 0, /*__setup_cpu_403 */ 424 }, 425 { /* 403GCX */ 426 0xffffff00, 0x00201400, "403GCX", 427 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 428 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 429 16, 16, 430 0, /*__setup_cpu_403 */ 431 }, 432 { /* 403G ?? */ 433 0xffff0000, 0x00200000, "403G ??", 434 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 435 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 436 16, 16, 437 0, /*__setup_cpu_403 */ 438 }, 439 { /* 405GP */ 440 0xffff0000, 0x40110000, "405GP", 441 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 442 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 443 32, 32, 444 0, /*__setup_cpu_405 */ 445 }, 446 { /* STB 03xxx */ 447 0xffff0000, 0x40130000, "STB03xxx", 448 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 449 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, 450 32, 32, 451 0, /*__setup_cpu_405 */ 452 }, 453 #endif /* CONFIG_4xx */ 454 #ifdef CONFIG_44x 455 { /* 440GP Rev. B */ 456 0xf0000fff, 0x40000440, "440GP Rev. B", 457 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 458 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 459 32, 32, 460 0, /*__setup_cpu_440 */ 461 }, 462 { /* 440GP Rev. C */ 463 0xf0000fff, 0x40000481, "440GP Rev. C", 464 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 465 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 466 32, 32, 467 0, /*__setup_cpu_440 */ 468 }, 469 { /* 440GX Rev. A */ 470 0xf0000fff, 0x50000850, "440GX Rev. A", 471 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 472 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 473 32, 32, 474 0, /*__setup_cpu_440 */ 475 }, 476 { /* 440GX Rev. B */ 477 0xf0000fff, 0x50000851, "440GX Rev. B", 478 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 479 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 480 32, 32, 481 0, /*__setup_cpu_440 */ 482 }, 483 { /* 440GX Rev. C */ 484 0xf0000fff, 0x50000892, "440GX Rev. C", 485 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, 486 PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, 487 32, 32, 488 0, /*__setup_cpu_440 */ 489 }, 490 #endif /* CONFIG_44x */ 491 #if !CLASSIC_PPC 492 { /* default match */ 493 0x00000000, 0x00000000, "(generic PPC)", 494 CPU_FTR_COMMON, 495 PPC_FEATURE_32, 496 32, 32, 497 0, 498 } 499 #endif /* !CLASSIC_PPC */ 500 }; 501