1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Unaligned memory access handler
4 *
5 * Copyright (C) 2001 Randolph Chung <tausq@debian.org>
6 * Copyright (C) 2022 Helge Deller <deller@gmx.de>
7 * Significantly tweaked by LaMont Jones <lamont@debian.org>
8 */
9
10 #include <linux/sched/signal.h>
11 #include <linux/signal.h>
12 #include <linux/ratelimit.h>
13 #include <linux/uaccess.h>
14 #include <linux/sysctl.h>
15 #include <asm/unaligned.h>
16 #include <asm/hardirq.h>
17 #include <asm/traps.h>
18
19 /* #define DEBUG_UNALIGNED 1 */
20
21 #ifdef DEBUG_UNALIGNED
22 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
23 #else
24 #define DPRINTF(fmt, args...)
25 #endif
26
27 #define RFMT "%#08lx"
28
29 /* 1111 1100 0000 0000 0001 0011 1100 0000 */
30 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6)
31 #define OPCODE2(a,b) ((a)<<26|(b)<<1)
32 #define OPCODE3(a,b) ((a)<<26|(b)<<2)
33 #define OPCODE4(a) ((a)<<26)
34 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
35 #define OPCODE2_MASK OPCODE2(0x3f,1)
36 #define OPCODE3_MASK OPCODE3(0x3f,1)
37 #define OPCODE4_MASK OPCODE4(0x3f)
38
39 /* skip LDB - never unaligned (index) */
40 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
41 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
42 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
43 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
44 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
45 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
46 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
47 /* skip LDB - never unaligned (short) */
48 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
49 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
50 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
51 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
52 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
53 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
54 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
55 /* skip STB - never unaligned */
56 #define OPCODE_STH OPCODE1(0x03,1,0x9)
57 #define OPCODE_STW OPCODE1(0x03,1,0xa)
58 #define OPCODE_STD OPCODE1(0x03,1,0xb)
59 /* skip STBY - never unaligned */
60 /* skip STDBY - never unaligned */
61 #define OPCODE_STWA OPCODE1(0x03,1,0xe)
62 #define OPCODE_STDA OPCODE1(0x03,1,0xf)
63
64 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
65 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
66 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
67 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
68 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
69 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
70 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
71 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
72 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
73 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
74 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
75 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
76
77 #define OPCODE_LDD_L OPCODE2(0x14,0)
78 #define OPCODE_FLDD_L OPCODE2(0x14,1)
79 #define OPCODE_STD_L OPCODE2(0x1c,0)
80 #define OPCODE_FSTD_L OPCODE2(0x1c,1)
81
82 #define OPCODE_LDW_M OPCODE3(0x17,1)
83 #define OPCODE_FLDW_L OPCODE3(0x17,0)
84 #define OPCODE_FSTW_L OPCODE3(0x1f,0)
85 #define OPCODE_STW_M OPCODE3(0x1f,1)
86
87 #define OPCODE_LDH_L OPCODE4(0x11)
88 #define OPCODE_LDW_L OPCODE4(0x12)
89 #define OPCODE_LDWM OPCODE4(0x13)
90 #define OPCODE_STH_L OPCODE4(0x19)
91 #define OPCODE_STW_L OPCODE4(0x1A)
92 #define OPCODE_STWM OPCODE4(0x1B)
93
94 #define MAJOR_OP(i) (((i)>>26)&0x3f)
95 #define R1(i) (((i)>>21)&0x1f)
96 #define R2(i) (((i)>>16)&0x1f)
97 #define R3(i) ((i)&0x1f)
98 #define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
99 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
100 #define IM5_2(i) IM((i)>>16,5)
101 #define IM5_3(i) IM((i),5)
102 #define IM14(i) IM((i),14)
103
104 #define ERR_NOTHANDLED -1
105
106 int unaligned_enabled __read_mostly = 1;
107
emulate_ldh(struct pt_regs * regs,int toreg)108 static int emulate_ldh(struct pt_regs *regs, int toreg)
109 {
110 unsigned long saddr = regs->ior;
111 unsigned long val = 0, temp1;
112 ASM_EXCEPTIONTABLE_VAR(ret);
113
114 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
115 regs->isr, regs->ior, toreg);
116
117 __asm__ __volatile__ (
118 " mtsp %4, %%sr1\n"
119 "1: ldbs 0(%%sr1,%3), %2\n"
120 "2: ldbs 1(%%sr1,%3), %0\n"
121 " depw %2, 23, 24, %0\n"
122 "3: \n"
123 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
124 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
125 : "+r" (val), "+r" (ret), "=&r" (temp1)
126 : "r" (saddr), "r" (regs->isr) );
127
128 DPRINTF("val = " RFMT "\n", val);
129
130 if (toreg)
131 regs->gr[toreg] = val;
132
133 return ret;
134 }
135
emulate_ldw(struct pt_regs * regs,int toreg,int flop)136 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
137 {
138 unsigned long saddr = regs->ior;
139 unsigned long val = 0, temp1, temp2;
140 ASM_EXCEPTIONTABLE_VAR(ret);
141
142 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
143 regs->isr, regs->ior, toreg);
144
145 __asm__ __volatile__ (
146 " zdep %4,28,2,%2\n" /* r19=(ofs&3)*8 */
147 " mtsp %5, %%sr1\n"
148 " depw %%r0,31,2,%4\n"
149 "1: ldw 0(%%sr1,%4),%0\n"
150 "2: ldw 4(%%sr1,%4),%3\n"
151 " subi 32,%2,%2\n"
152 " mtctl %2,11\n"
153 " vshd %0,%3,%0\n"
154 "3: \n"
155 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
156 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
157 : "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
158 : "r" (saddr), "r" (regs->isr) );
159
160 DPRINTF("val = " RFMT "\n", val);
161
162 if (flop)
163 ((__u32*)(regs->fr))[toreg] = val;
164 else if (toreg)
165 regs->gr[toreg] = val;
166
167 return ret;
168 }
emulate_ldd(struct pt_regs * regs,int toreg,int flop)169 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
170 {
171 unsigned long saddr = regs->ior;
172 __u64 val = 0;
173 ASM_EXCEPTIONTABLE_VAR(ret);
174
175 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
176 regs->isr, regs->ior, toreg);
177
178 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
179 return ERR_NOTHANDLED;
180
181 #ifdef CONFIG_64BIT
182 __asm__ __volatile__ (
183 " depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */
184 " mtsp %4, %%sr1\n"
185 " depd %%r0,63,3,%3\n"
186 "1: ldd 0(%%sr1,%3),%0\n"
187 "2: ldd 8(%%sr1,%3),%%r20\n"
188 " subi 64,%%r19,%%r19\n"
189 " mtsar %%r19\n"
190 " shrpd %0,%%r20,%%sar,%0\n"
191 "3: \n"
192 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
193 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
194 : "=r" (val), "+r" (ret)
195 : "0" (val), "r" (saddr), "r" (regs->isr)
196 : "r19", "r20" );
197 #else
198 {
199 unsigned long shift, temp1;
200 __asm__ __volatile__ (
201 " zdep %2,29,2,%3\n" /* r19=(ofs&3)*8 */
202 " mtsp %5, %%sr1\n"
203 " dep %%r0,31,2,%2\n"
204 "1: ldw 0(%%sr1,%2),%0\n"
205 "2: ldw 4(%%sr1,%2),%R0\n"
206 "3: ldw 8(%%sr1,%2),%4\n"
207 " subi 32,%3,%3\n"
208 " mtsar %3\n"
209 " vshd %0,%R0,%0\n"
210 " vshd %R0,%4,%R0\n"
211 "4: \n"
212 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1")
213 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1")
214 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
215 : "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
216 : "r" (regs->isr) );
217 }
218 #endif
219
220 DPRINTF("val = 0x%llx\n", val);
221
222 if (flop)
223 regs->fr[toreg] = val;
224 else if (toreg)
225 regs->gr[toreg] = val;
226
227 return ret;
228 }
229
emulate_sth(struct pt_regs * regs,int frreg)230 static int emulate_sth(struct pt_regs *regs, int frreg)
231 {
232 unsigned long val = regs->gr[frreg], temp1;
233 ASM_EXCEPTIONTABLE_VAR(ret);
234
235 if (!frreg)
236 val = 0;
237
238 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
239 val, regs->isr, regs->ior);
240
241 __asm__ __volatile__ (
242 " mtsp %4, %%sr1\n"
243 " extrw,u %2, 23, 8, %1\n"
244 "1: stb %1, 0(%%sr1, %3)\n"
245 "2: stb %2, 1(%%sr1, %3)\n"
246 "3: \n"
247 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
248 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
249 : "+r" (ret), "=&r" (temp1)
250 : "r" (val), "r" (regs->ior), "r" (regs->isr) );
251
252 return ret;
253 }
254
emulate_stw(struct pt_regs * regs,int frreg,int flop)255 static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
256 {
257 unsigned long val;
258 ASM_EXCEPTIONTABLE_VAR(ret);
259
260 if (flop)
261 val = ((__u32*)(regs->fr))[frreg];
262 else if (frreg)
263 val = regs->gr[frreg];
264 else
265 val = 0;
266
267 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
268 val, regs->isr, regs->ior);
269
270
271 __asm__ __volatile__ (
272 " mtsp %3, %%sr1\n"
273 " zdep %2, 28, 2, %%r19\n"
274 " dep %%r0, 31, 2, %2\n"
275 " mtsar %%r19\n"
276 " depwi,z -2, %%sar, 32, %%r19\n"
277 "1: ldw 0(%%sr1,%2),%%r20\n"
278 "2: ldw 4(%%sr1,%2),%%r21\n"
279 " vshd %%r0, %1, %%r22\n"
280 " vshd %1, %%r0, %%r1\n"
281 " and %%r20, %%r19, %%r20\n"
282 " andcm %%r21, %%r19, %%r21\n"
283 " or %%r22, %%r20, %%r20\n"
284 " or %%r1, %%r21, %%r21\n"
285 " stw %%r20,0(%%sr1,%2)\n"
286 " stw %%r21,4(%%sr1,%2)\n"
287 "3: \n"
288 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
289 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
290 : "+r" (ret)
291 : "r" (val), "r" (regs->ior), "r" (regs->isr)
292 : "r19", "r20", "r21", "r22", "r1" );
293
294 return ret;
295 }
emulate_std(struct pt_regs * regs,int frreg,int flop)296 static int emulate_std(struct pt_regs *regs, int frreg, int flop)
297 {
298 __u64 val;
299 ASM_EXCEPTIONTABLE_VAR(ret);
300
301 if (flop)
302 val = regs->fr[frreg];
303 else if (frreg)
304 val = regs->gr[frreg];
305 else
306 val = 0;
307
308 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
309 val, regs->isr, regs->ior);
310
311 if (!IS_ENABLED(CONFIG_64BIT) && !flop)
312 return ERR_NOTHANDLED;
313
314 #ifdef CONFIG_64BIT
315 __asm__ __volatile__ (
316 " mtsp %3, %%sr1\n"
317 " depd,z %2, 60, 3, %%r19\n"
318 " depd %%r0, 63, 3, %2\n"
319 " mtsar %%r19\n"
320 " depdi,z -2, %%sar, 64, %%r19\n"
321 "1: ldd 0(%%sr1,%2),%%r20\n"
322 "2: ldd 8(%%sr1,%2),%%r21\n"
323 " shrpd %%r0, %1, %%sar, %%r22\n"
324 " shrpd %1, %%r0, %%sar, %%r1\n"
325 " and %%r20, %%r19, %%r20\n"
326 " andcm %%r21, %%r19, %%r21\n"
327 " or %%r22, %%r20, %%r20\n"
328 " or %%r1, %%r21, %%r21\n"
329 "3: std %%r20,0(%%sr1,%2)\n"
330 "4: std %%r21,8(%%sr1,%2)\n"
331 "5: \n"
332 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0")
333 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0")
334 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")
335 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0")
336 : "+r" (ret)
337 : "r" (val), "r" (regs->ior), "r" (regs->isr)
338 : "r19", "r20", "r21", "r22", "r1" );
339 #else
340 {
341 __asm__ __volatile__ (
342 " mtsp %3, %%sr1\n"
343 " zdep %R1, 29, 2, %%r19\n"
344 " dep %%r0, 31, 2, %2\n"
345 " mtsar %%r19\n"
346 " zvdepi -2, 32, %%r19\n"
347 "1: ldw 0(%%sr1,%2),%%r20\n"
348 "2: ldw 8(%%sr1,%2),%%r21\n"
349 " vshd %1, %R1, %%r1\n"
350 " vshd %%r0, %1, %1\n"
351 " vshd %R1, %%r0, %R1\n"
352 " and %%r20, %%r19, %%r20\n"
353 " andcm %%r21, %%r19, %%r21\n"
354 " or %1, %%r20, %1\n"
355 " or %R1, %%r21, %R1\n"
356 "3: stw %1,0(%%sr1,%2)\n"
357 "4: stw %%r1,4(%%sr1,%2)\n"
358 "5: stw %R1,8(%%sr1,%2)\n"
359 "6: \n"
360 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0")
361 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0")
362 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")
363 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0")
364 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0")
365 : "+r" (ret)
366 : "r" (val), "r" (regs->ior), "r" (regs->isr)
367 : "r19", "r20", "r21", "r1" );
368 }
369 #endif
370
371 return ret;
372 }
373
handle_unaligned(struct pt_regs * regs)374 void handle_unaligned(struct pt_regs *regs)
375 {
376 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
377 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
378 int modify = 0;
379 int ret = ERR_NOTHANDLED;
380
381 __inc_irq_stat(irq_unaligned_count);
382
383 /* log a message with pacing */
384 if (user_mode(regs)) {
385 if (current->thread.flags & PARISC_UAC_SIGBUS) {
386 goto force_sigbus;
387 }
388
389 if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
390 __ratelimit(&ratelimit)) {
391 printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
392 " at ip " RFMT " (iir " RFMT ")\n",
393 current->comm, task_pid_nr(current), regs->ior,
394 regs->iaoq[0], regs->iir);
395 #ifdef DEBUG_UNALIGNED
396 show_regs(regs);
397 #endif
398 }
399
400 if (!unaligned_enabled)
401 goto force_sigbus;
402 }
403
404 /* handle modification - OK, it's ugly, see the instruction manual */
405 switch (MAJOR_OP(regs->iir))
406 {
407 case 0x03:
408 case 0x09:
409 case 0x0b:
410 if (regs->iir&0x20)
411 {
412 modify = 1;
413 if (regs->iir&0x1000) /* short loads */
414 if (regs->iir&0x200)
415 newbase += IM5_3(regs->iir);
416 else
417 newbase += IM5_2(regs->iir);
418 else if (regs->iir&0x2000) /* scaled indexed */
419 {
420 int shift=0;
421 switch (regs->iir & OPCODE1_MASK)
422 {
423 case OPCODE_LDH_I:
424 shift= 1; break;
425 case OPCODE_LDW_I:
426 shift= 2; break;
427 case OPCODE_LDD_I:
428 case OPCODE_LDDA_I:
429 shift= 3; break;
430 }
431 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
432 } else /* simple indexed */
433 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
434 }
435 break;
436 case 0x13:
437 case 0x1b:
438 modify = 1;
439 newbase += IM14(regs->iir);
440 break;
441 case 0x14:
442 case 0x1c:
443 if (regs->iir&8)
444 {
445 modify = 1;
446 newbase += IM14(regs->iir&~0xe);
447 }
448 break;
449 case 0x16:
450 case 0x1e:
451 modify = 1;
452 newbase += IM14(regs->iir&6);
453 break;
454 case 0x17:
455 case 0x1f:
456 if (regs->iir&4)
457 {
458 modify = 1;
459 newbase += IM14(regs->iir&~4);
460 }
461 break;
462 }
463
464 /* TODO: make this cleaner... */
465 switch (regs->iir & OPCODE1_MASK)
466 {
467 case OPCODE_LDH_I:
468 case OPCODE_LDH_S:
469 ret = emulate_ldh(regs, R3(regs->iir));
470 break;
471
472 case OPCODE_LDW_I:
473 case OPCODE_LDWA_I:
474 case OPCODE_LDW_S:
475 case OPCODE_LDWA_S:
476 ret = emulate_ldw(regs, R3(regs->iir), 0);
477 break;
478
479 case OPCODE_STH:
480 ret = emulate_sth(regs, R2(regs->iir));
481 break;
482
483 case OPCODE_STW:
484 case OPCODE_STWA:
485 ret = emulate_stw(regs, R2(regs->iir), 0);
486 break;
487
488 #ifdef CONFIG_64BIT
489 case OPCODE_LDD_I:
490 case OPCODE_LDDA_I:
491 case OPCODE_LDD_S:
492 case OPCODE_LDDA_S:
493 ret = emulate_ldd(regs, R3(regs->iir), 0);
494 break;
495
496 case OPCODE_STD:
497 case OPCODE_STDA:
498 ret = emulate_std(regs, R2(regs->iir), 0);
499 break;
500 #endif
501
502 case OPCODE_FLDWX:
503 case OPCODE_FLDWS:
504 case OPCODE_FLDWXR:
505 case OPCODE_FLDWSR:
506 ret = emulate_ldw(regs, FR3(regs->iir), 1);
507 break;
508
509 case OPCODE_FLDDX:
510 case OPCODE_FLDDS:
511 ret = emulate_ldd(regs, R3(regs->iir), 1);
512 break;
513
514 case OPCODE_FSTWX:
515 case OPCODE_FSTWS:
516 case OPCODE_FSTWXR:
517 case OPCODE_FSTWSR:
518 ret = emulate_stw(regs, FR3(regs->iir), 1);
519 break;
520
521 case OPCODE_FSTDX:
522 case OPCODE_FSTDS:
523 ret = emulate_std(regs, R3(regs->iir), 1);
524 break;
525
526 case OPCODE_LDCD_I:
527 case OPCODE_LDCW_I:
528 case OPCODE_LDCD_S:
529 case OPCODE_LDCW_S:
530 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
531 break;
532 }
533 switch (regs->iir & OPCODE2_MASK)
534 {
535 case OPCODE_FLDD_L:
536 ret = emulate_ldd(regs,R2(regs->iir),1);
537 break;
538 case OPCODE_FSTD_L:
539 ret = emulate_std(regs, R2(regs->iir),1);
540 break;
541 #ifdef CONFIG_64BIT
542 case OPCODE_LDD_L:
543 ret = emulate_ldd(regs, R2(regs->iir),0);
544 break;
545 case OPCODE_STD_L:
546 ret = emulate_std(regs, R2(regs->iir),0);
547 break;
548 #endif
549 }
550 switch (regs->iir & OPCODE3_MASK)
551 {
552 case OPCODE_FLDW_L:
553 ret = emulate_ldw(regs, R2(regs->iir), 1);
554 break;
555 case OPCODE_LDW_M:
556 ret = emulate_ldw(regs, R2(regs->iir), 0);
557 break;
558
559 case OPCODE_FSTW_L:
560 ret = emulate_stw(regs, R2(regs->iir),1);
561 break;
562 case OPCODE_STW_M:
563 ret = emulate_stw(regs, R2(regs->iir),0);
564 break;
565 }
566 switch (regs->iir & OPCODE4_MASK)
567 {
568 case OPCODE_LDH_L:
569 ret = emulate_ldh(regs, R2(regs->iir));
570 break;
571 case OPCODE_LDW_L:
572 case OPCODE_LDWM:
573 ret = emulate_ldw(regs, R2(regs->iir),0);
574 break;
575 case OPCODE_STH_L:
576 ret = emulate_sth(regs, R2(regs->iir));
577 break;
578 case OPCODE_STW_L:
579 case OPCODE_STWM:
580 ret = emulate_stw(regs, R2(regs->iir),0);
581 break;
582 }
583
584 if (ret == 0 && modify && R1(regs->iir))
585 regs->gr[R1(regs->iir)] = newbase;
586
587
588 if (ret == ERR_NOTHANDLED)
589 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
590
591 DPRINTF("ret = %d\n", ret);
592
593 if (ret)
594 {
595 /*
596 * The unaligned handler failed.
597 * If we were called by __get_user() or __put_user() jump
598 * to it's exception fixup handler instead of crashing.
599 */
600 if (!user_mode(regs) && fixup_exception(regs))
601 return;
602
603 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
604 die_if_kernel("Unaligned data reference", regs, 28);
605
606 if (ret == -EFAULT)
607 {
608 force_sig_fault(SIGSEGV, SEGV_MAPERR,
609 (void __user *)regs->ior);
610 }
611 else
612 {
613 force_sigbus:
614 /* couldn't handle it ... */
615 force_sig_fault(SIGBUS, BUS_ADRALN,
616 (void __user *)regs->ior);
617 }
618
619 return;
620 }
621
622 /* else we handled it, let life go on. */
623 regs->gr[0]|=PSW_N;
624 }
625
626 /*
627 * NB: check_unaligned() is only used for PCXS processors right
628 * now, so we only check for PA1.1 encodings at this point.
629 */
630
631 int
check_unaligned(struct pt_regs * regs)632 check_unaligned(struct pt_regs *regs)
633 {
634 unsigned long align_mask;
635
636 /* Get alignment mask */
637
638 align_mask = 0UL;
639 switch (regs->iir & OPCODE1_MASK) {
640
641 case OPCODE_LDH_I:
642 case OPCODE_LDH_S:
643 case OPCODE_STH:
644 align_mask = 1UL;
645 break;
646
647 case OPCODE_LDW_I:
648 case OPCODE_LDWA_I:
649 case OPCODE_LDW_S:
650 case OPCODE_LDWA_S:
651 case OPCODE_STW:
652 case OPCODE_STWA:
653 align_mask = 3UL;
654 break;
655
656 default:
657 switch (regs->iir & OPCODE4_MASK) {
658 case OPCODE_LDH_L:
659 case OPCODE_STH_L:
660 align_mask = 1UL;
661 break;
662 case OPCODE_LDW_L:
663 case OPCODE_LDWM:
664 case OPCODE_STW_L:
665 case OPCODE_STWM:
666 align_mask = 3UL;
667 break;
668 }
669 break;
670 }
671
672 return (int)(regs->ior & align_mask);
673 }
674
675