1 /*
2 * FILE NAME
3 * arch/mips/vr41xx/common/cmu.c
4 *
5 * BRIEF MODULE DESCRIPTION
6 * Clock Mask Unit routines for the NEC VR4100 series.
7 *
8 * Author: Yoichi Yuasa
9 * yyuasa@mvista.com or source@mvista.com
10 *
11 * Copyright 2001,2002 MontaVista Software Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
24 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
26 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
27 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33 /*
34 * Changes:
35 * MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
36 * - New creation, NEC VR4122 and VR4131 are supported.
37 * - Added support for NEC VR4111 and VR4121.
38 *
39 * Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
40 * - Added support for NEC VR4133.
41 */
42 #include <linux/init.h>
43 #include <linux/spinlock.h>
44 #include <linux/types.h>
45
46 #include <asm/cpu.h>
47 #include <asm/io.h>
48 #include <asm/vr41xx/vr41xx.h>
49
50 #define CMUCLKMSK_TYPE1 KSEG1ADDR(0x0b000060)
51 #define CMUCLKMSK_TYPE2 KSEG1ADDR(0x0f000060)
52 #define MSKPIU 0x0001
53 #define MSKSIU 0x0002
54 #define MSKAIU 0x0004
55 #define MSKKIU 0x0008
56 #define MSKFIR 0x0010
57 #define MSKDSIU 0x0820
58 #define MSKCSI 0x0040
59 #define MSKPCIU 0x0080
60 #define MSKSSIU 0x0100
61 #define MSKSHSP 0x0200
62 #define MSKFFIR 0x0400
63 #define MSKSCSI 0x1000
64 #define MSKPPCIU 0x2000
65 #define CMUCLKMSK2 KSEG1ADDR(0x0f000064)
66 #define MSKCEU 0x0001
67 #define MSKMAC0 0x0002
68 #define MSKMAC1 0x0004
69
70 static uint32_t cmu_base;
71 static uint16_t cmuclkmsk, cmuclkmsk2;
72 static spinlock_t cmu_lock;
73
74 #define read_cmuclkmsk() readw(cmu_base)
75 #define read_cmuclkmsk2() readw(CMUCLKMSK2)
76 #define write_cmuclkmsk() writew(cmuclkmsk, cmu_base)
77 #define write_cmuclkmsk2() writew(cmuclkmsk2, CMUCLKMSK2)
78
vr41xx_supply_clock(unsigned int clock)79 void vr41xx_supply_clock(unsigned int clock)
80 {
81 spin_lock_irq(&cmu_lock);
82
83 switch (clock) {
84 case PIU_CLOCK:
85 cmuclkmsk |= MSKPIU;
86 break;
87 case SIU_CLOCK:
88 cmuclkmsk |= MSKSIU | MSKSSIU;
89 break;
90 case AIU_CLOCK:
91 cmuclkmsk |= MSKAIU;
92 break;
93 case KIU_CLOCK:
94 cmuclkmsk |= MSKKIU;
95 break;
96 case FIR_CLOCK:
97 cmuclkmsk |= MSKFIR | MSKFFIR;
98 break;
99 case DSIU_CLOCK:
100 if (current_cpu_data.cputype == CPU_VR4111 ||
101 current_cpu_data.cputype == CPU_VR4121)
102 cmuclkmsk |= MSKDSIU;
103 else
104 cmuclkmsk |= MSKSIU | MSKDSIU;
105 break;
106 case CSI_CLOCK:
107 cmuclkmsk |= MSKCSI | MSKSCSI;
108 break;
109 case PCIU_CLOCK:
110 cmuclkmsk |= MSKPCIU;
111 break;
112 case HSP_CLOCK:
113 cmuclkmsk |= MSKSHSP;
114 break;
115 case PCI_CLOCK:
116 cmuclkmsk |= MSKPPCIU;
117 break;
118 case CEU_CLOCK:
119 cmuclkmsk2 |= MSKCEU;
120 break;
121 case ETHER0_CLOCK:
122 cmuclkmsk2 |= MSKMAC0;
123 break;
124 case ETHER1_CLOCK:
125 cmuclkmsk2 |= MSKMAC1;
126 break;
127 default:
128 break;
129 }
130
131 if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
132 clock == ETHER1_CLOCK)
133 write_cmuclkmsk2();
134 else
135 write_cmuclkmsk();
136
137 spin_unlock_irq(&cmu_lock);
138 }
139
vr41xx_mask_clock(unsigned int clock)140 void vr41xx_mask_clock(unsigned int clock)
141 {
142 spin_lock_irq(&cmu_lock);
143
144 switch (clock) {
145 case PIU_CLOCK:
146 cmuclkmsk &= ~MSKPIU;
147 break;
148 case SIU_CLOCK:
149 if (current_cpu_data.cputype == CPU_VR4111 ||
150 current_cpu_data.cputype == CPU_VR4121) {
151 cmuclkmsk &= ~(MSKSIU | MSKSSIU);
152 } else {
153 if (cmuclkmsk & MSKDSIU)
154 cmuclkmsk &= ~MSKSSIU;
155 else
156 cmuclkmsk &= ~(MSKSIU | MSKSSIU);
157 }
158 break;
159 case AIU_CLOCK:
160 cmuclkmsk &= ~MSKAIU;
161 break;
162 case KIU_CLOCK:
163 cmuclkmsk &= ~MSKKIU;
164 break;
165 case FIR_CLOCK:
166 cmuclkmsk &= ~(MSKFIR | MSKFFIR);
167 break;
168 case DSIU_CLOCK:
169 if (current_cpu_data.cputype == CPU_VR4111 ||
170 current_cpu_data.cputype == CPU_VR4121) {
171 cmuclkmsk &= ~MSKDSIU;
172 } else {
173 if (cmuclkmsk & MSKSIU)
174 cmuclkmsk &= ~MSKDSIU;
175 else
176 cmuclkmsk &= ~(MSKSIU | MSKDSIU);
177 }
178 break;
179 case CSI_CLOCK:
180 cmuclkmsk &= ~(MSKCSI | MSKSCSI);
181 break;
182 case PCIU_CLOCK:
183 cmuclkmsk &= ~MSKPCIU;
184 break;
185 case HSP_CLOCK:
186 cmuclkmsk &= ~MSKSHSP;
187 break;
188 case PCI_CLOCK:
189 cmuclkmsk &= ~MSKPPCIU;
190 break;
191 case CEU_CLOCK:
192 cmuclkmsk2 &= ~MSKCEU;
193 break;
194 case ETHER0_CLOCK:
195 cmuclkmsk2 &= ~MSKMAC0;
196 break;
197 case ETHER1_CLOCK:
198 cmuclkmsk2 &= ~MSKMAC1;
199 break;
200 default:
201 break;
202 }
203
204 if (clock == CEU_CLOCK || clock == ETHER0_CLOCK ||
205 clock == ETHER1_CLOCK)
206 write_cmuclkmsk2();
207 else
208 write_cmuclkmsk();
209
210 spin_unlock_irq(&cmu_lock);
211 }
212
vr41xx_cmu_init(void)213 void __init vr41xx_cmu_init(void)
214 {
215 switch (current_cpu_data.cputype) {
216 case CPU_VR4111:
217 case CPU_VR4121:
218 cmu_base = CMUCLKMSK_TYPE1;
219 break;
220 case CPU_VR4122:
221 case CPU_VR4131:
222 cmu_base = CMUCLKMSK_TYPE2;
223 break;
224 case CPU_VR4133:
225 cmu_base = CMUCLKMSK_TYPE2;
226 cmuclkmsk2 = read_cmuclkmsk2();
227 break;
228 default:
229 panic("Unexpected CPU of NEC VR4100 series");
230 break;
231 }
232
233 cmuclkmsk = read_cmuclkmsk();
234
235 spin_lock_init(&cmu_lock);
236 }
237